Showing papers on "Analog-to-digital converter published in 1979"

An optical analog-to-digital converter - Design and analysis

Abstract: A design for an optical analog-to-digital converter using channel waveguide modulators is described. Optical and electrical power requirements and factors which limit the speed of operation are analyzed, and the implications of signal sampling with a repetitively pulsed light source are discussed.

Monolithic triple diffusion analog to digital converter

Abstract: A parallel analog-to-digital converter having high speed and high resolution, fabricated on a single integrated-circuit chip in such a manner as to avoid problems typically associated with high speed parallel converters. The converter disclosed by way of example has an eight-bit output, 256 matched comparators for quantizing an analog input signal, and encoding and latching logic for deriving digital outputs from the comparators. Problems related to comparator mismatching, high comparator input capacitance and high comparator input bias current, are effectively minimized by the use of a triple diffusion fabrication process, which substantially reduces the number of defects in the circuit and provides a relatively high component packing density.

Decimator apparatus for decreasing the word rate of a digital signal of the type employed in digital telephone systems

Abstract: There is disclosed a decimator structure which incorporates the cascade of an FIR filter with a low pass recursive filter. The input to the decimator is obtained from a high rate analog to digital converter. The output from the decimator is a low rate digital signal having an increased word length. The decimator serves to reduce the word rate and increase the word length of the output digital signal of the analog to digital converter. In this manner, the low rate digital signal at the output of the decimator can be easily accommodated by the telephone system. The decimator described does not require conventional hardware multipliers and hence, affords efficient and economical circuit components which can be implemented by conventional integrated circuit techniques. A register further reduces the pulse rate for transmission.

Analog to digital encoding system with an encoder structure incorporating instrumentation amplifier, sample and hold, offset correction and gain correction functions

Abstract: A new encoder for an analog to digital converter of the successive approximation type incorporates instrumentation amplifier and signal sample and hold functions within the encoder proper, thereby substantially simplifying the converter circuitry. An input analog current signal is applied to a sample and hold capacitor within the encoder through the encoder comparator at a time when the weighted reference signal to the comparator is set to zero. The capacitor stored analog voltage is subsequently applied to the encoder summing node and the encoding sequence ensues. The encoder may be provided with offset and gain correction circuitry, conventionally found exterior to the encoder. In one embodiment of the invention, offset correction is effected using the signal sample and hold capacitor.

Fast high resolution predictive analog-to-digital converter with error correction

Abstract: An analog-to-digital conversion system uses a fast analog-to-digital converter having a resolution less than the system resolution to convert the difference between a previously predicted value and the current analog value. The converted difference is summed with the predicted value to compute the actual value of the analog input signal to a resolution greater than that of the fast analog-to-digital converter. The high resolution digital value thus obtained becomes the predicted value for the next conversion. This predicted value is converted by a digital-to-analog converter having the same accuracy but not the same resolution as the system output to an analog signal which is compared with the input analog signal to obtain a difference signal. This difference signal is sampled and held to provide the input to the fast analog-to-digital converter. The system includes a gain scaling and switching circuit to compensate for errors which would occur when the difference between the true analog input and the prediction exceeds the range of the low resolution, fast analog-to-digital converter.

An Integrating Analog-to-Digital Converter for Differential Transducers

Abstract: An improved dual-slope analog-to-digital converter for measurements made with a pair of resistive or capacitive differential transducers is described. The converter can be contrasted with the conventional method in which the transducers are placed in a bridge, the bridge output is amplified, and the conversion is made. In the new converter the transducers are part of the integrator. As a result, conversion of the signal to a time interval takes place at an earlier stage, eliminating the bridge and the amplifier. The method has the same advantages as the dual-slope method and several additional ones. The fractional change in the transducers is obtained as the ratio of the difference and sum of two time periods. As a result, the converter does not need an accurate voltage reference. In addition, errors due to offset in the integrating amplifier are eliminated.

Parallel analog-to-digital converter

Abstract: An analog signal is converted into an n bit digital signal by n comparator circuits which compare the analog input to 2 n -1 reference inputs. Each comparator output alternates as the analog signal increases through the reference levels. Logic circuitry including n-1 exclusive-OR gates decodes the comparator outputs into an n bit code. A comparator circuit for comparing the analog input signal with each of several reference levels and providing an alternating output includes a pair of differential input transistors and a current sink transistor associated with each reference level. The collectors of the differential transistor pairs are cross coupled to two output resistors which are connected to a differential exclusive-OR gate. A latching circuit is operable to latch the comparator output when the comparator is in other than the comparing mode.

Sequential successive approximation analog-to-digital converter

Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Input gain adjusting apparatus and method

Abstract: In a voice operated gain adjust for a voice processor included an input range adjust (10), a sixteen channel amplifier (12), an analog to digital converter (14) and a microcomputer (16). An audio signal including voice signals and background noise is applied to the input of the range adjust (10) and the amplifier (12). The output of the input range adjust (10) is applied through the A/D converter (14) to the microcomputer (16). The microcomputer (16) distinguishes voice signals from background noise and controls the gain of the amplifier (12) in accordance with the amplitude of the voice signals. Also, the microcomputer (16) controls the gain of the input range adjust (10) so that the input signal to the A/D converter (14) is within the operating range of the converter (14).

D.C. Stabilized analog-to-digital converter

Abstract: A D.C. stabilized analog-to-digital converter of the type having a coarse converter responsive to a supplied analog signal for converting the analog signal to a coarse digital signal representation thereof, a reconverter for reconverting the coarse digital signal representation to a coarse analog signal and for determining the difference between the coarse analog signal and the supplied analog signal, and a fine converter responsive to the determined difference for converting said difference to a fine digital representation of the supplied analog signal. A reference signal is periodically supplied to the coarse converter such that this supplied reference signal is converted to a coarse digital signal representation thereof, the coarse digital signal representation of the reference signal is reconverted to a coarse analog reference signal and the difference between this coarse analog reference signal and the periodically supplied reference signal is determined. A detector is operative during the period that the reference signal is supplied to the coarse converter for detecting a D.C. drift in the operation of the reconverter. A uniform D.C. compensating signal is produced in accordance with the detected D.C. drift and is applied to the reconverter so as to compensate for such D.C. drift.

MOS Analog-to-digital converter

Abstract: An MOS, integrated circuit, analog-to-digital converter powered by a single power supply potential and suitable for converting an analog signal equal to that power supply potential is described. The input analog signal is capacitively divided by two; resistor strings interlaced with the resistance ladder of the digital-to-analog converter provides a reduced reference potential. A chopper amplifier is employed in the comparator which includes circuits for reducing offset potentials.

Digital error correcting trimming in an analog to digital converter

Abstract: A single chip integrated circuit analog-to-digital converter uses the successive approximation approach with resistor ladder-switching decoder digital-to-analog coverters coupled to a precision plural input comparator. An on board PROM is provided to store in digital form the information necessary to trim the digital-to-analog converters. The converter is actuated during wafer probing in the manufacturing process and the PROM is programmed with the trim information. Initially, the PROM is bypassed and the digital words needed for accurate trim applied externally. Once the correct trim words are found, the PROM is programmed with the correct words. A 13-bit converter is supplied with ten 7-bit trim words to achieve a fully trimmed product in wafer fabrication.

Tracking analog-to-digital converter for AC signals

Abstract: An electronic circuit is described for providing an analog-to-digital conversion system having an output "delta" format in which a pulse is produced for each defined change in the amplitude of the input signal. The circuit is characterized by minimal hardware complexity and low current drain. In performing its conversion function, the circuit advantageously employs a single capacitor for coupling the input signal into the system as well as for storing precisely controlled voltage increments for effecting the equality of the input signal and a reference potential. The AC coupling afforded by this configuration eliminates the problems attendant with the digitization of a small AC signal superimposed on a large DC component. Additionally, the circuit of the present invention lends itself to the multiplexing of input signals.

Analog to digital converter with offset error correction

Abstract: An analog to digital converter of the ramp-integrator type with provisions to reduce errors due to offset voltages. The cycle which is utilized includes a preconditioning cycle during which the capacitor is charged while the input to the buffer amplifier is connected to the datum level voltage, such as ground. A microprocessor is used to compute the unknown signal.

Folding circuit for an analog-to-digital converter

Abstract: In a folding circuit of an analog-to-digital converter a chain of emitters of transistors which are interconnected by threshold elements and fed by direct current sources are used to reduce the distortion. The circuit is controlled by a current source which produces the input signal.

Analog-to-digital converter: a new type using an electrooptic light modulator

Abstract: A new type of analog-to-digital converter (ADC), which consists of an electrooptic light modulator and electronic diode circuits, is proposed. This device allows direct translation of an analog signal into a Gray code with high speed and high resolution. It is demonstrated that an analog signal with a 60-V P–P voltage and a frequency of 11 MHz can be translated into 3 bits in a Gray code by this ADC.

Dual-slope integrating analog-to-digital converter with digital self-calibration

Abstract: With dual-slope integrating analog-to-digital (A/D) converters, which are most frequently used for relatively slow speed conversion, any drift in the operational amplifiers is a very critical factor in limiting their performance. A method has been proposed to eliminate the drift problem completely [1]. This short paper describes a similar but different approach to solve the problem. Some of the advantages are: no necessity for manual adjustments, the use of inexpensive amplifiers instead of costly units with no performance degradation for the temperature range limited only by digital circuits. The old method is more adaptable to ratiometric conversion, while the new method is more adaptable to normal dual-slope integrating A/D conversion with a reference voltage of opposite polarity to input signals. As is the case with the basic dual-slope converters, no precision components are required.

Charge coupled device feedback analog-to-digital converter using successive approximations

Abstract: An analog-to-digital converter includes a charge coupled device comparator receiving an analog signal which is to be converted to an eight bit binary word. An eight bit charge coupled device shift register addresses an eight bit digital-to-analog converter through eight separate resettable latches to generate a reference signal which is compared in successive approximations to the analog signal by the charge coupled device comparator to generate each binary bit of the eight bit word. Sensitivity of the charge coupled device comparator is enhanced by the use of charge coupled regenerative feedback to generate each binary bit of the eight bit binary word, which is read serially into an output register. The charge coupled device comparator decides whether each bit of the eight bit binary word is to be a logic one or a logic zero by comparing the analog input signal with reference signals selected in successive approximations by a shift register addressing the digital-to-analog converter. The analog signal is compared with a progressively increasing reference signal whose magnitude is increased by successively smaller increments. Eight such successive approximations and comparisons are made in order to generate the eight bit binary word.

Tilt compensating AGC

Abstract: A correcting bias is applied to the video signal from a hand-held optical character reader to compensate for horizontal tilt of the hand-held reader and also to increase the acceptability of photodiode arrays which are used in the reader and to correct uneven sensitivity of the photoelements in the photodiode arrays. The analog video is changed to a four bit video and this four bit video is processed to produce a tilt error signal indicative of magnitude and direction of the tilt. This tilt error signal is then applied back as a compensating factor in the four bit analog to digital converter to compensate for the tilt of the hand-held reader.

Gated precision offset circuit for a digital meter having a dual slope analog-to-digital converter

Abstract: An offset circuit for use in providing an offset signal to an analog-to-digital converter. The analog-to-digital converter has an integrator for performing signal integrate operations and is connected to a digital display. The offset circuit is gated to provide a variable offset current directly to the integrator of the analog-to-digital converter, thereby eliminating adverse loading effects on the high input impedance of the analog-to-digital converter.

Multichannel Analog to Digital Converter and Readout System for the Time Projection Chamber

Abstract: The Time Projection Chamber (TPC) project involves the characterization of signals arriving at approximately 20,000 separate detector wires and pad electrodes. The characterization requires measurement of the signal amplitudes in 100 ns time slices over a total time of 20 ?s (the total chamber drift time). Charge Coupled Devices (CCD's) are used to store an image of the 20 ?s span of signals and the image is "played back" at a low rate (50 ?s time slices, i.e., a time expansion of 500:1). Digitization of the 20,000 parallel signals at the output of the CCD's must therefore be accomplished in 50 ?s and readout of digital data into the computer system must also be accomplished in this time. Many zeros occur in the data, a fact which reduces the data handling demands on the readout system, but does not reduce the stringent requirements on the digitizer. Therefore, the requirements on the digitizer are highlighted by the need for low cost, low power consumption and by the need to perform 9-bit digitizing in less than 50 ?s. Furthermore, a double buffering scheme must be used to permit interleaving digitizing and digital readout cycles. We describe our implementation of this concept and some possible applications for other experiments which require many Analog to Digital Converter (ADC) channels.

Stabilizing circuit of analog to digital converter

Abstract: PURPOSE:To prevent the malfunction due to level variation and noise in advance and to perform stable digital signal conversion at all times, by constituting the converter so that the operation of conversion can not be made if the analog input signal is not changed a given level or more. CONSTITUTION:The circuit provides the A/D converter 11 converting the analog input signal X1 into digital signal, D/A converter 13 converting the digital signal into analog signal, level shift circuit 14 performing addition and subtraction of the output to a given finest increment and obtaining the upper and lower limits X+ and X-, and comparison circuit 15 comparing the level of the analog input signal Xi to the upper and lower limits X+ and X-. As the result of comparison, when reaching X1>X+ or Xi

Analog to digital converter

Abstract: An analog to digital converter as implemented by large scale integrated circuit techniques utilizing charge coupled device technology. On a single integrated circuit chip, the necessary gate and charge packet transfer paths form a cell which carries out analog to digital conversion. Depending on the amount of charge transferred from one location to the next two outputs of the cell denote digital voltage levels indicative of logic 0 or logic 1. Utilizing a plurality of the analog to digital converter cells with transfer gates on a single integrated circuit chip, a mufti-bit AID conversion register is constructed. Digital voltage levels indicative of logic 0's or logic 1's are generated from varying analog charge levels applied.

Analog to digital converter of integration type

Abstract: PURPOSE:To reduce the conversion time more and to decrease the amplitude of the integrator output, by constitututing an A/D converter of high accuracy with a monolithic integrated circuit operated at a low voltage.

A High Rate NaI Detector System

Abstract: Front end electronics (detector to ADC) have been developed to operate over an input count rate range of 105 to 106 counts per second with less than ± 1% gain shift and minimal resolution degradation. The system was developed to satisfy requirements for a nuclear hardened gamma densitometer utilizing multichannel analyzer pulse height analysis techniques for reactor background subtraction. The circuitry developed includes a fast current mode preamplifier with first order count rate dependent gain compensation, a baseline restorer, a single channel analyzer with pile-up rejection and live time measuring circuits, and a fast linear gate. The single channel analyzer is used for energy region of interest selection so that only those pulses within the energy region of interest are presented to the analog to digital converter.

High density analog-to-digital converter

Abstract: Combining integrated injection logic (I 2 L) and linear circuitry permits fabrication of a highly dense analog-to-digital (A-to-D) converter. The heart of the A-to-D converter is a linear-I 2 L plurality of high density variable current sources which are proportional to each other. These variable current sources, when used in combination with I 2 L constant current sources and current sensing means, provide a highly compact A-to-D converter.

Analog-to-digital converter

Abstract: An analog to digital converter device is disclosed. The device includes a plurality of serially connected stages representing bits, each stage including generally a source of current or fluid and a second current or fluid source of opposite polarity, a current or flow direction controlled voltage or pressure drop unit, a comparator unit and a current or flow switch or valve responsive thereto for controlling the source of current or fluid flow.

Charge-coupled device serial analog-to-digital converter and associated conversion method

Abstract: A plurality of charge-coupled device shift registers or shift register elements is used to generate a plurality of packets of charge, each proportional to a different reference potential. Using a sense amplifier or comparator, each of the packets of charge is compared, either simultaneously or sequentially, with one or more packets of charge generated by the potential of an analog signal. Signals from the comparator are then supplied to an encoder or a counter to generate a digital signal representative of the analog signal. In one embodiment the plurality of different reference potentials are generated by positioning the shift registers or shift register elements at various locations along a resistance having a potential applied across it.