Showing papers on "Bandgap voltage reference published in 1993"

A curvature-corrected low-voltage bandgap reference

Abstract: A curvature-corrected bandgap reference that can function at supply voltages as low as 1 V, at a supply current of only 100 mu A, is presented. After trimming, this bandgap reference has a temperature coefficient (TC) of +or-4 p.p.m./ degrees C. The reference voltage is about 200 mV and it can easily be adjusted to higher values. The temperature range of this circuit is from 0 to 125 degrees C. This bandgap reference is realized using a standard bipolar process with base-diffused resistors. >

Temperature compensation bandgap voltage reference and method

Abstract: An output curvature correction is provided for a band-gap reference circuit that exhibits a temperature dependent output error in the form of k 1 T - k 2 Tln(k 3 T) in the absence of the correction. A substantially constant collector current is driven through a correction transistor and used in connection with a proportional to absolute temperature (PTAT) transistor collector current in the uncorrected circuit. The difference between the base-emitter voltages for the two transistors has the form -k 1 'T + k 2 'ln(k 3 'T.sub.). This voltage differential is scaled by an appropriate selection of resistor ratios and combined with the uncorrected circuit output to provide a corrected output that is substantially insensitive to temperature variations.

Low voltage CMOS bandgap with new trimming and curvature correction methods

Abstract: A bandgap circuit for generating an accurate and stable reference voltage at low power supply voltages. Stacking of bipolar devices allows for a lower opamp closed-loop gain, which in turn reduces the error voltage contribution to the output due to opamp offset. A CMOS opamp having NMOS input reference transistors coupled with a new bandgap architecture allows a 1.2 v reference (unlike other stacked architectures) without sacrificing low voltage operation. A new trimming method provides for very efficient trimming of bandgap output voltage. Instead of fine tuning the output voltage by trimming ratioed resistors, the output voltage is trimmed by either changing the area of ratioed bipolar transistors, or changing the magnitude of ratioed currents in equally sized bipolar transistors. Therefore, very fine trimming resolution is possible because of the logarithmic function defining the current or transistor size ratios. A new curvature correction method reduces curvature without requiring additional circuitry. Curvature can be drastically reduced by using resistors with negative temperature coefficient.

Bandgap voltage reference generator.

Abstract: A bandgap voltage generator using a simple bandgap voltage reference supply circuit which has virtually no power supply rejection ratio (PSRR) which can produce an output bandgap voltage, V BG , using an extremely low power supply voltage, V DD . In order to increase the PSRR, a signal generated by the bandgap voltage reference supply circuit is amplified by a high gain amplifier circuit comprised of two cascode connected FETs. The highly amplified signal generated by the high gain amplifier circuit drives a voltage regulator, comprised of an FET used as a voltage controlled current sink, which regulates the voltage supplied from the power supply, V DD , to the bandgap voltage reference supply circuit. This combination of a bandgap voltage reference with virtually no PSRR and a high gain amplifier results in a bandgap voltage generator with a very high PSRR.

Substrate bias generating circuit

Abstract: A substrate bias generating circuit (20) provides a substrate bias voltage to a substrate (50) of an integrated circuit. A voltage-to-current converter circuit (22) provides a constant current proportional to a bandgap generated reference voltage. P-channel transistors (34 and 35) then provide constant current sources for a voltage level sensing circuit (36) based on the bandgap generated reference voltage. The voltage level sensing circuit (36) monitors the level of the substrate bias voltage, and when the substrate bias voltage reaches a predetermined voltage level, provides a first control signal for activating an oscillator (47). A level converter (43) is provided to amplify, or level convert the first control signal for more reliable control of the oscillator. A substrate bias generating circuit (20) provides a precisely controlled substrate bias voltage to the substrate (50) that is independent of process, temperature, and power supply variations.

Power factor boost converter power supply

Abstract: A boost-type power factor correction circuit is disclosed in which output voltage of the convertor is proportional to the peak input voltage. To achieve this, the circuit includes a peak rectifier D2, C2 which senses peak input voltage and provides a reference to which the output voltage derived through resistors R3, R4 is compared to give an error signal dependent upon variation from the peak input voltage derived reference. The error signal is used to control a MOSFET switch 120 to provide an output voltage V out dependent upon the reference.

Non-volatile semiconductor memory device with high voltage generator

Abstract: Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

Voltage supply circuit and semiconductor device including such circuit

Abstract: The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

Low-power inverter for crystal oscillator buffer or the like

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.

Second order low temperature coefficient bandgap voltage supply

Abstract: A voltage reference circuit (2) is provided which includes a 2nd order curvature correction circuit (3) that eliminates undesirable 2nd order polynomial temperature dependency characteristics. A bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) forms a bandgap current (I X ) that is dependent upon absolute temperature. A translinear cell (Q15, Q14, Q13, Q12, Q11 and Q10) transforms this current in a squaring transformation and divides the squared current by a temperature independent current (I X ). A current mirror (Q17 and Q16) adjusts the value of the squared current so that it approximates the value of the 2nd order term of the bandgap reference circuit.

Circuit for generating an internal source voltage

Abstract: A circuit for generating an internal source voltage (int.Vcc) applied to the memory elements of a semiconductor device includes a reference voltage generating circuit (100) for generating a reference voltage (Vref), a comparator (200) for comparing the internal source voltage (int.Vcc) with the reference voltage (Vref), a driver (90) for driving an external source voltage (ext.Vcc) into the internal source voltage (int.Vcc) under the control of the comparator (200), and a low reference voltage generating circuit (400) for generating a control signal (64) to fully turn on the driver (90) when the voltage level of the external source voltage (ext.Vcc) is lower than the voltage level of the reference voltage (Vref), whereby the control signal (64) of said low reference voltage generating circuit (400) prevents the driver (90) from receiving the output signal (G1) of the comparator (200) so as to apply the external source voltage (ext.Vcc) to the memory elements of the memory device.

Circuit including bandgap reference

Abstract: An apparatus comprises a bandgap reference voltage circuit with first and second current legs and circuitry for generating a bandgap reference voltage. A transistor is coupled to the first current leg for selectively providing current to the first leg of the bandgap reference voltage circuit. A control circuit controls the transistor to turn the transistor on when an external voltage supply is initially applied to the apparatus to provide a start up current to the bandgap voltage reference source and senses an output voltage developed by the bandgap reference current source. The control circuit turns off the transistor responsive to the sensed developed voltage when the sensed developed voltage rises above a predetermined threshold.

Reference voltage generator utilizing CMOS transistor

Abstract: A reference voltage generating circuit for converting a first source voltage to a second source voltage includes a positive thermal compensation circuit connected between the first source voltage and ground voltage and having a positive thermal coefficient for positively compensating the second source voltage with respect to temperature variations, and a negative thermal compensation circuit responsive to the output of the positive thermal compensation circuit and having a negative thermal coefficient for negatively compensating the second source voltage with respect to temperature variations, wherein the positive and negative thermal coefficients counter-balance each other so as to stabilize the second source voltage.

CMOS voltage reference circuit

Abstract: A simple CMOS voltage reference circuit develops a reference voltage from the sum of the threshold voltages of a pair of complementary devices. In a p-type substrate a p-channel device is formed in an isolated n-type well, with the well tied to the source at the reference node. The drain is coupled to the drain of a complementary n-channel device. An additional p-channel device functions as a current source. The voltage reference circuit may be advantageously cascaded to improve stability and insensitivity to the power supply voltage.

Switching circuit of low power consumption

Abstract: In a switching circuit comprising an output field effect transistor having an output drain electrode connected to a power supply through a load resistor and an output gate electrode supplied with an input voltage, a reference field effect transistor has a reference drain electrode connected to the power supply through a reference resistor and a reference gate electrode supplied with the input voltage. Each of the output and the reference field effect transistors is made of a metal oxide semiconductor. A comparator has a load input terminal connected to a load node of the output drain electrode and the load resistor and a reference input terminal connected to a reference node of the reference drain electrode and the reference resistor. The comparator compares a load sensing voltage from the load node with a reference voltage from the reference node to produce a compare output voltage when the load sensing voltage is higher than the reference voltage. A bias power circuit supplies a bias voltage to the output gate electrode and the reference gate electrode. A limiting circuit supplies a limiting voltage to the output gate electrode and the reference gate electrode when the limiting circuit is supplied with the compare output voltage. The limiting voltage is lower than the bias voltage.

Current monitoring circuit having controlled sensitivity to temperature and supply voltage

Abstract: An integrated circuit including a comparator having two output states and being responsive to a voltage developed across a shunt in the circuit so that the comparator assumes one of its two output states when the voltage developed across the shunt is greater than a threshold switching voltage and the other of its two output states when the voltage developed across the shunt is less than the threshold switching voltage. The integrated circuit additionally includes a threshold switching voltage sensitivity control circuit, coupled to and controlling the comparator, for controlling a sensitivity of the threshold switching voltage to changes in a supply voltage of the lamp circuit and for controlling a sensitivity of the threshold switching voltage to changes in temperature of the integrated circuit.

Low current bandgap reference voltage circuit

Abstract: A bandgap reference voltage circuit adapted for low current applications. A reference voltage is provided as a function of the difference between the V be voltages of a pair of bipolar transistors scaled by a ratio of the resistances of a pair of MOS transistors, to provide a predetermined reference voltage level. For a given reference voltage circuit size, use of the pair of MOS transistors achieves a low reference current in an integrated circuit, the size of which is far less than that implemented with conventional resistors. Alternatively, for a given reference current, the MOS transistor scaling provides a smaller reference circuit than is otherwise achievable.

Charge pump type booster circuit having output voltage stabilizing function

Abstract: PURPOSE:To stabilize the output voltage while enhancing the efficiency in voltage regulation by comparing the output from a booster circuit with a reference voltage and varying the ON resistance on one switching transistor depending on an error signal thereby controlling the charging operation. CONSTITUTION:A boosted voltage Vout appearing at the output terminal 105 of a booster circuit is divided by means of resistors R1, R2. A divided voltage V1 is applied to the positive input of a comparator 106 and compared with a reference voltage VR from a reference voltage supply 109. When the voltage V1 is higher than the reference voltage, the comparator 106 outputs a positive error signal to increase the gate bias of a transistor TR5 thus decreasing the drain/source resistance RDS. Consequently, the gate voltage of a transistor TR2 lowers to decrease the ON resistance thus lowering the output voltage Vout. When the voltage V1 drops below the reference voltage, the comparator 106 delivers a negative error signal to lower the gate bias of the TR5 and increase the resistance RDS thus increasing the output voltage Vout. This constitution realizes highly efficient stabilization and regulation of output voltage.

Reference voltage generation method and apparatus

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise. In addition, two cascaded voltage generator circuits create a reference voltage generator, that enables the voltage controlled device to detect changes in noise conditions, by providing it with a reference voltage that varies in a controlled and specific manner with the changes in transistor conductance parameters, power supply voltages, and operating temperatures. This reference voltage generator controls the variance of the reference voltage in two manners. First, this generator utilizes a positive temperature coefficient floating voltage source to increase (in a controlled fashion) the variance of the reference voltage with changes in the temperature. Second, this generator uses a feedback path, between the first and the second voltage generator circuits, to compensate for uncontrolled variations of the reference voltage due to process variations in transistor conductance parameters.

Substrate voltage generator and method therefor in a semiconductor device having selectively activated internal stepped-down power supply voltages

Abstract: A semiconductor device having an internal voltage down converter includes a circuit operating with an externally applied power supply voltage, a circuit operating with an external stepped-down voltage as an operation power supply voltage, and substrate voltage generators for generating a substrate potential, or a substrate bias voltage according to a state of the internal stepped-down voltage. The first substrate voltage generator includes a first generating circuit operating with the externally applied power supply voltage, a second generating circuit operating with the internal stepped-down voltage, and a circuit for operating the first generating circuit in a period from turn-on of the external power supply until the internal stepped-down voltage becomes stable, and for operating the second generating circuit thereafter. The second substrate voltage generator includes first and second generating circuits, and a circuit responsive to the substrate voltage for selectively activating the first and second generating circuits. Those constructions make it possible to stably apply a substrate voltage corresponding to an operation voltage to the substrate region.

Integrated high voltage differential sensor using the inverse gain of high voltage transistors

Abstract: An integrated high voltage differential sensor which uses the inverse gain of a pair of parasitic JFETs to provide a low power circuit for translating a differential high voltage signal down to a lower voltage level that can be easily sensed by the low voltage control circuitry in a power IC and without the use of a resistive voltage divider. The IC includes, between a first high voltage input and ground, a first series circuit of a first JFET, a first voltage level shifting resistor and a bias current source (I B ). A second series circuit of a reference resistor (R L ), a second JFET, a second voltage level shifting resistor and a bias current source (I B ) is coupled between a second high voltage input and ground. A feedback circuit including an operational amplifier is coupled between a low voltage point of the first series circuit and the gates of both JFETs so as to adjust the bias voltages of the JFETs. A comparator is coupled to a low voltage point of the second series circuit and switches about an input differential threshold value of I B R L .

Stress mode circuit for an integrated circuit with on-chip voltage down converter

Abstract: A stress mode circuit is provided on an integrated circuit memory to generate a voltage that is either (a) equal to a reference voltage (VREF), or (b) is proportional to an external supply voltage VCCEXT. The circuit includes two voltage divider circuits (60) to provide the proportional voltage. Two differential amplifiers (72, 74, 76, 78, 80, 82; 94, 96, 98, 100, 102, 104) are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage (VREF). The outputs operate switches (52, 64) that couple the reference voltage (VREF) or the proportional voltage to an output terminal.

Symmetrical bipolar bias current source with high power supply rejection ratio (PSRR)

Abstract: A bandgap reference voltage source (104) has positive and negative terminals (104a,104b) which are connected through high impedance constant current sources (124c,126c) to positive and negative voltage supplies (+VDD,-VEE) respectively. The effect of variations of the voltage supplies (+VDD, -VEE) on the voltage source (104) is low due to the high impedances of the currents sources (124c,126c), providing a high power supply rejection ratio (PSRR). The reference voltage (VREF) generated by the voltage source (104) is converted into a reference current (IREF) which flows through two equal series resistors (108,110), and also through current mirrors (124,126) which produce positive and negative output currents corresponding thereto. The current sources (124c,126c) for the voltage source (104) are also controlled by the current mirrors (124,126). A servo control amplifier (232) senses the voltage at the junction (234) of the resistors (108,110) and adjusts the voltage at either the positive or negative terminal (104a,104b) of the voltage source (104) to maintain the voltages at the terminals (104a,104b) symmetrical with respect to ground, thereby preventing the voltage source (104) from latching to one of the voltage supplies (+VDD,-VEE) during startup.

Voltage generating circuit causing no threshold voltage loss by FET in output voltage

Abstract: An improved substrate bias voltage generating circuit provided in a semiconductor device such as a DRAM is disclosed. In a conducting period of an NMOS transistor (8) provided in a last stage, a higher enough voltage than a source voltage (i.e. an output voltage V BB ) can be applied to a gate of the transistor (8). Loss for a threshold voltage of the transistor (8) does not occur in the output voltage V BB ; the substrate bias voltage V BB of a level -Vcc can be generated.

Testing semiconductor memory device having test circuit

Abstract: A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2·Vcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2·Vcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time.

Zero-curvature band gap reference cell

Abstract: In one band gap reference cell, first and second transistors have the bases thereof coupled together. A first supply voltage line is operatively connected to the collectors of the transistors and a second supply voltage line is operatively connected to the emitters of the transistors. The voltage supply lines produce a current proportional to temperature when the device is operating. A first resistor is connected between the emitter of one of the transistors and the second supply line. A third transistor has the base thereof coupled to the bases of the first and second transistors. A current is established in a curve-compensation resistor which is equal to the sum of the currents in the first and second transistors less a nonlinear portion which arises from variations in VBE with respect to temperature. A second resistor is connected across the base-emitter junction of one of the transistors. A current complementary to temperature is established in the resistor when the device is operating. The currents in the transistors and in the resistor are combined to produce a reference current having a predetermined temperature coefficient characteristic. Appropriate selection of resistor values enables providing a reference voltage greater than the band gap voltage.

Method and apparatus for controlling an inverter

Abstract: An inverter control apparatus comprises a controller, a mode decision circuit and a voltage reference conversion circuit. The mode decision circuit determines one of three kinds of modes which may be used to control the inverter, namely, a normal mode, a rectangle mode and zero correction mode selected according to values and polarities of multi-phase voltage reference signals. The voltage reference conversion circuit corrects the voltage reference signals according to the determined mode in the mode decision circuit. In the case of the normal mode, the mode decision circuit outputs the previous voltage reference signal V~ without change as the new or corrected voltage reference signals. In the case of the rectangle mode, the circuit fixes the voltage reference signal V~ having the greatest value of the three phase (U-phase, V-phase and W-phase) to a minimum voltage reference Vmin which is of opposite polarity to the selected greatest value signal, or, in another embodiment, to a zero value. Further the circuit converts the others voltage reference signals to corrected voltage reference signals without change of line voltage. The control circuit permits control of the inverter even in a regime of low reference voltage which would otherwise result in an uncontrolled region of the inverter.

Input buffer for translating TTL levels to CMOS levels

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the amplitude of the first control voltage for small amplitude values of the first control voltage, and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltage to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls.

Semiconductor integrated circuit apparatus including supply voltage conversion circuit

Abstract: Disclosed is a DRAM including a power-on reset signal generating circuit for outputting a voltage of a predetermined level for a definite period by utilizing a rise of an external supply voltage, and a supply voltage conversion circuit for lowering the external supply voltage to a constant voltage. In this DRAM, the power-on reset signal generating circuit is driven by the external supply voltage not an output voltage of the supply voltage conversion circuit. The output voltage of the supply voltage conversion circuit is applied to various internal circuits including smaller-scale MOS transistors, to drive these internal circuits. Since the supply voltage conversion circuit often includes circuit components with a large time constant in order to decrease power consumption, the output voltage of the supply voltage conversion circuit rises rather slowly than the external supply voltage. However, the power-on reset signal generating circuit receives the external supply voltage as a driving voltage and hence immediately outputs a normal one-shot pulse in response to the supply of power to the DRAM.

A precision CMOS voltage reference with enhanced stability for the application to advanced VLSIs

Abstract: A precision CMOS voltage reference circuit is very important for the design of the stable voltage-down converter of high density VLSIs. By using the active mode operation of the component MOS transistors, a CMOS bandgap type reference voltage circuit is redesigned for the enhancement of the circuit stability against the internal noises. The voltage supply independence, temperature independence and the stability characteristics of the reference circuit are analyzed by using an analytical model. The designed circuit is incorporated into a 5-V to 3.3-V down converter and integrated into a 16-M DRAM by using 0.6-/spl mu/m CMOS technology. The measured characteristics of the fabricated voltage-down converter show a voltage dependence of 47.5 mV/V and 18 ppm/C temperature coefficient at V/sub ext/ = 3.2 V and 255 ppm/C at V/sub ext/ = 5.45 V, respectively. >