Showing papers on "Binary number published in 1986"

Digital optical computing with symbolic substitution.

Abstract: Symbolic substitution logic is based on optical pattern transformations This space-invariant mechanism is shown to be capable of supporting space-variant operations An optical implementation is proposed It is based on splitting an image, shifting the split images, superimposing the results, regenerating the superimposed image with an optical logic array, splitting the regenerated image, shifting the resulting images, and superimposing the shifted images Experimental results are presented Examples demonstrate how symbolic substitution logic can be used to implement Boolean logic, binary arithmetic, cellular logic, and Turing machines

Logical minimization of multilevel coded functions.

Abstract: Discrete numerical values in digital processing systems may be encoded in two-level (binary) or higher-level (multilevel) representations. Multilevel coding can produce smaller and more efficient processors. In truth-table lookup processing, the number of entries (reference patterns) can be reduced using multilevel coding. Since parallel-input/parallel-output optical truth-table lookup processors can be constructed based on holographic content-addressable memories, it is essential to know the minimum storage required to implement various functions. A new simple method for reducing multivalued functions is presented. This method is based on an extension of the Quine-McCluskey minimization method used for binary logic functions. This minimization method is then applied to the truth tables representing (1) modified signed-digit addition, (2) residue addition, and (3) residue multiplication. A programmable logic array gate configuration for the modified signed-digit adder is presented.

New implementation of symbolic substitution logic.

Abstract: Symbolic substitution is a spatial logic for digital optical computers that utilizes the specific advantages of optical signal processing. Previous implementations used the optical intensity for coding the binary values. In this implementation we are using polarization for coding, and we show how a complete recognition–substitution processor can be implemented. The advantages of this type of coding are: better utilization of the device area, an equal distribution of intensity, and symmetry between the two logic states.

Digital Simulation with Multiple Logic Values

Abstract: Multiple-valued logics have long been used, often in intuitive fashion, for simulating transients, errors, unknown states, variable-strength signals, etc., in binary digital circuits. This paper presents a rigorous algebraic method for analyzing such logics, and for systematically constructing new ones. Starting with a basis such as 2-valued Boolean algebra, new algebras suitable for a broad range of practical simulation tasks are obtained systematically via a small set of expansion operations. This approach is applied in detail to the construction of families of simulation algebras for gate-level logic circuits; switch-level simulation is also considered. It is concluded that current simulation programs frequently lack essential logic values, and occasionally have superfluous ones. Some major discrepancies in the number of distinct logic values claimed by commercial simulators are also explained.

Multiplication-free multi-alphabet arithmetic code

Abstract: Method and apparatus which cyclically generate a compressed, arithmetically-coded binary stream in response to binary occurrence counts of symbols in an uncoded string The symbols in the uncoded string are drawn from a multi-character alphabet which is not necessarily a binary one Coding operations and hardware are simplified by deriving from the binary occurrence counts an estimate of the probability of each unencoded symbol at its precise lexical location The probability estimation eliminates any requirement for division or multiplication by employing magnitude-shifting of the binary occurrence counts The encoded stream is augmented by the estimated symbol probability at the same time that an internal variable is updated with an estimate of the portion of a probability interval remaining after coding the current symbol, the interval estimate being obtained from the left-shifted occurrence counts Decoding is the dual of encoding The unencoded symbol stream is extracted, symbol-by-symbol, by subtracting the estimated symbol probability that comes closest to, but does not exceed the magnitude of the compressed stream, re-estimating the symbol probabilities based upon the decoding, and testing the difference of the subtraction against the re-estimated probability

Computational method and apparatus for finite field multiplication

Abstract: A Galois field multiplier (10) is used for obtaining a product (D), which is stored in an accumulating register (20), of two elements (B, C) which are stored in shift registers (12, 14). The product (D) is represented in normal basis form with each binary digit of the bit vector (the product, D) being determined by a sum of the product of the binary digits (bi, ci) representing the two elements. By grouping like ones of one of ordinary digits in the expression for the binary digit of the product and offsetting the suffixes of the binary digits, it is possible to accumulate grouped terms of each of the binary digits of the product simultaneously.

Shadow casting for multiple-valued associative logic

Abstract: The operating characteristics of digital optical computers utilizing spatial light modulator based shadow casting are reviewed. The geometric and physical limitations of this method are examined. Because of the highly parallel nature of this approach, such systems are capable of truth-table processing. A detailed analysis of the relative advantages of both direct and associative truth table processing is presented. For each case, the use of binary or of multiple-valued logic is considered. The respective merits from the point of view of the number of computations per second and the energy required per computation are outlined. Switching energy considerations based on the use of multiple wavelengths in these systems are also discussed. The characteristic features of this type of optical logic are compared to those of electronic logic.

Digital phase aligner

Abstract: This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0°) and anti-phase (180°) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0° or 180°. A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.

Condition code producing system

Abstract: A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: a storing device for storing each bit of the condition code; a device for producing a plurality of detection signals from values of predetermined bits of the binary floating point data. This data is transferred to a bus within the arithmetic unit by a micro instruction which involves a data transfer, where the micro instruction is one of a plurality of micro instructions constituting the micro program. The micro instruction comprises a condition control field constituted by a plurality of bits having values depending on at least precision and data portions of the binary floating point data which is transferred. The system also includes a device for producing a new condition code from the plurality of detection signals and the condition code already stored in the storing device depending on a value of the condition control field and for setting the new condition code in the storing device.

Optical binary coded ternary arithmetic and logic.

Abstract: Two ternary, an ordinary ternary (OT) and a binary balance ternary (BT), number representations to be used for optical computing are discussed. An unsigned OT number is represented by a string of symbols (0, 1, 2), while for the BT, the three logic symbols take on the set (−1, 0, +1). The BT symbols can represent a signed number. Using a particular binary encoding method, the three ternary symbols are converted to a pair of binary symbols. The binary coded ternary (BCT) representation has two advantages. First, it allows use of the well-developed binary optical components. Second, compared with other optical multiple-valued number encoding schemes, it reduces the number of input–output channels and thus is able to conserve the optical space–bandwidth product. As an example for arithmetic operations, BCT full addition algorithms are given. As examples for multiple-valued logic computing, BCT Post, Webb, and residue logic elements are discussed. Using the two-port Sagnac interferometric switches, optical implementations of various BCT arithmetic and logic operations are described.

Negative base encoding in optical linear algebra processors

Abstract: In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

Algorithms for Iterative Array Multiplication

Abstract: Algorithms for the parallel multiplication of two n- bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays for one n-bit × n-bit multiplication, are compared to a straightforward iterative array algorithm having a 2n-cell delay and its higher radix version having an n-cell delay.

Radiotelephone system employing digitized speech/data and embedded signalling

Abstract: A radiotelephone system in which the signalling protocol for the system is embedded in the frame synchronization of the digital messages transmitted on the system. System state communication is achieved by utilizing a sequence of normal synchronization words and their ones complement inverses. Reliability of the coding is achieved by detecting normal or inverse words as binary levels when fewer than a predetermined number of bit errors exist in the bit sequence. If the predetermined number of bit errors is exceeded, a selected binary one or zero is subtituted (3003). This selected sequence of binary levels is decoded (3101) and the Hamming distance between a masked decoded sequence and a masked selected sequence is calculated (3207). If the Hamming distance calculation yields a number greater than the error correction capability of thge coding function, a new set of substituted binary levels is tried (3205), otherwise the decoded sequence is accepted as correct.

Binary phase-only optical correlation system

Abstract: A binary phase-only optical correlation system incorporating therein a binary phase-only filter. The binary phase-only optical filter is made by mathematically generating preselected phase-only information by a fast Fourier Transform technique. This generated phase-only information is binarized into a function having two values. This binarized function is utilized to produce a mask which in turn is used in conjunction with an appropriate optical substrate to produce the binary phase-only filter. The manufacture of the binary phase-only filter is substantially easier than the production of a phase-only filter yet virtually the same correlation results when the binary phase-only filter when it is used in an optical correlation system.

Optical techniques for real-time binary multiplication

Abstract: An optical system which performs the multiplication of binary numbers is described and proof-of-principle experiments are performed. The simultaneous generation of all partial products, optical regrouping of bit products, and optical carry look-ahead addition are novel features of the proposed scheme which takes advantage of the parallel operations capability of optical computers. The proposed processor uses liquid crystal light valves (LCLVs). By space-sharing the LCLVs one such system could function as an array of multipliers. Together with the optical carry look-ahead adders described, this would constitute an optical matrix–vector multiplier.

A Signed Bit-Sequential Multiplier

Abstract: Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion.

Mixed binary multiplication of optical signals by convolution in an inhomogeneously broadened absorber

Abstract: We have employed the recently developed technique of real-time optical waveform convolution in inhomogeneously broadened absorbers [ Appl. Phys. Lett.45, 714 ( 1984)] to perform mixed binary multiplication of digital optical signals. We demonstrate that an output signal representing the mixed binary product of up to three numbers encoded into discrete input signals can be generated in a single convolution cycle. We have studied the effect of material relaxation on output signal shapes and intensities. We find that mixed binary product signals up to ∼0.5% as intense as the input signals can be expected in weakly relaxing materials. This method of all-optical multiplication may be useful in high-speed applications, since its bit rate is limited fundamentally only by the inhomogeneous absorption bandwidth of the material used.

Circuitry for complementing binary numbers

Abstract: Circuitry for forming the twos complement or ones complement of N-bit binary numbers is described. The circuitry includes N stages each of which contains an exclusive NOR gate (300, 310, 320, 330, 340, 350). A first input terminal (B) of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal (C) is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal (C) of the exclusive NOR gate (300) of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing (302, 312, 322, 334, 342) a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal to each stage is ORed (612, 622, 632, 642, 652) with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal (C) of the exclusive NOR gate. This circuitry complements only negative values, passing positive values unchanged.

Stark-broadening simulation in hydrogen: study of the binary and complete binary collision hypotheses

Abstract: The binary collision and complete binary collision approximations used in electronic Stark-broadening calculations have been analysed by means of a computer simulation technique for the Lyman alpha line in hydrogen. A simulation process has been developed in which three spectral profiles are simultaneously obtained, corresponding to the exact calculation and each of the two above approximations. Calculations have been performed under four different temperature and density conditions.

Method and system for binary-to-decimal interconversion

Abstract: A process for performing binary-to-decimal conversion distinguishes between two major subdivisions of the information represented by the binary values and signifies the type of information for each value by a so-called attribute bit. The attribute bits for several binary values can be encoded into a single decimal digit while each binary value is itself converted to a reduced number of decimal digits.

Surface segregation in binary alloys

Abstract: A semiempirical calculation is outlined that allows analysis of experimental results for the apparent surface concentration of binary alloys, obtained by x‐ray photoelectron spectroscopy, (XPS). A segregation profile giving the enrichment of the segregating element at and near the surface is obtained from the analysis. Using previously published data for Cu17 Ni83(100) and Cu17 Ni83(111), it is shown that copper segregation is not restricted to the first few layers, but instead extends significantly into the selvedge (near‐surface) region. This occurrence is not explainable by the use of present ideal solution models. An extended ideal solution model is presented, in which the bond strengths vary gradually from top‐layer values to bulk values. This model is consistent with the observed penetration of copper enrichment into the selvedge. The parameters describing the gradual change of bond strengths are determined via comparison of the results of the model with XPS data.

Saving cycles in floating point division

Abstract: In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor have been normalized

Synchronous binary counter

Abstract: A synchronous binary circuit comprising a counter including J-K flip-flops constituting lower l bit stages and higher m bit stages, first logic means for feeding, to J and K input terminals on each of flip-flops among the lower l bit stage flip-flops higher than the second bit stage, an AND of non-inverted outputs of all the lower stage flip-flops than the pertinent stage, second logic means for feeding, to the J and K input terminals of the first stage flip-flops among the higher m bit stage flip-flops, a first logical product of the non-inverted output of a one bit lower stage flip-flop and non-inverted outputs of the first to (l-1)-th bit stage flip-flops among the lower bit stage flip-flops, and third logic means for feeding, to the J and K input terminals of flip-flops among the higher m bit stage flip-flops higher than the second stage, a second logical product of non-inverted outputs of the lower first to (l-1)-th bit stage flip-flops and a third logical product, the third logical product being a logical product of an non-inverted output of a flip-flop lower by one bit than each of the flip-flops lower than the second stage and a fourth logical product, and the fourth logical product being a logical product of non-inverted outputs of flip-flops lower by more than two bit stages in the higher bit stage flip-flops.

Device for summing of squares

Abstract: This device for summing squares is designed to calculate the sum of the squares of "n" numbers with "m" binary elements, where n and m are whole numbers equal to or greater than "2"; it is made up from a systolic network 14 formed of identical cells arranged in lines and columns and around which is arranged a first peripheral circuit 16 to supply signals to the upper line, a second peripheral circuit 18 to supply signals to the input column also receiving signals from a presentation circuit 20 acting as an interface between the "n" numbers and the systolic network and finally an output circuit 22 connected to the lower line. Each line of the network is allocated to the calculation of the square of each of the numbers. Calculations are carried forward from the upper to the lower line via links between the lines. The output circuit consists of an adder component supplying the result from the calculations brought forward from the last line.

Mixing binary and continuous connection schemes for knowledge access

Abstract: We present BACAS, a Binary and Continuous Activation System which is a parallel process content-addressable memory model. BACAS is designed for the representation and retrieval of 'knowledge of the world' for automatic natural language understanding. In its present form, BACAS is a two-layered system with 10 K-structures (like scripts) in the binary output macro-layer represented by 46 Threshold Knowledge Units and 184 processing elements (like action events) in the continuous activation micro-layer. We discuss the problems of combining two types of connection system and describe a simulation in which the system moves from one pattern to the next in response to external input. A new tool for connection systems, the pulse-out. is introduced. This is a device which replaces the Boltzmann Machine in creating energy leaps. The pulse-out also has the advantage, in the current system, of setting the state of the system a short Hamming distance from an appropriate pattern.

Logical Signal Processing With Optically Connected Threshold Gates

Abstract: The characteristic features of deterministic and nondeterministic optical threshold logic gates are reviewed. Analog, binary, multiple-valued, multiple-class, and polynomial threshold gates are considered. Threshold synthesis techniques are outlined. Bulk optical and integrated optical implementations of reconfigurable threshold gates are discussed. Examples of deterministic logic operations involving binary addition and digital picture processing are presented. Applications to nondeterministic operations such as pattern recognition and heteroassociative processing are considered. The sensitivity of deterministic and nondeterministic mul-tiple-input optical threshold gates to physical errors is analyzed. The particular advantages of optically connected threshold gates with respect to electronic threshold gates are discussed.