Showing papers on "Bit plane published in 2014"

Calibration and noise reduction of analog to digital converters

Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k−1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k−1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Security for an Image using Bit-slice Rotation Method-image Encryption

Abstract: Image encryption plays a major role in information security. It is mainly used to convert the original image into another form. In this work, we propose a bit plane slicing of digital image to provide the more security. The main aim of BPS is used to divide the digital image into 8 bit planes. The bit plane is further rotated in order to provide better encrypted image and to make hacking more difficult. It focuses on two techniques such as bit plane slicing and image rotation for efficient image encryption. The classification of bit plane is used for analyzing the importance played by each bit of an image. It is used to estimate the each pixel of an image. The proposed technique involves rotation of bit planes is employed to make highly secure image encryption. By this method scrambling of an image is based on efficient technique even it is intercepted, the information cannot be understood. It is mainly useful for image compression because it exhibits high coding efficiency. This method which makes the decryption of an image more difficult compared to other techniques.

Method and apparatus for performing a vector bit reversal and crossing

Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

Fragility evaluation of intermediate significant bit embedding (ISBE) based digital image watermarking scheme for content authentication

Abstract: Digital image watermarking is being extensively used for protecting sensitive image data transmitted over insecure channels. Watermarks are primarily used for two fold operations, copyright protection and content authentication. Robust image watermarks are used for copyright protection and fragile watermarks used for the content authentication. In this paper fragility evaluation of a fragile image watermarking scheme has been carried out to ascertain the areas where the embedded watermark could be more fragile. The embedding has been carried out in spatial domain in various image bit planes using Intermediate Significant Bit Embedding (ISBE). The evaluation has been carried out by subjecting the watermarked image to various image processing attacks like histogram equalization, Low Pass Filtering, addition of white Gaussian noise, JPEG compression etc. The experimental results show that irrespective of the nature of attacks the higher the order of bit plane in which data is embedded lower the fragility of the system and vice-versa.

Image encoding method and apparatus for performing bit-plane scanning coding upon pixel data and related image decoding method and apparatus

Abstract: An image encoding method includes at least following steps: receiving a plurality of target pixels within a frame, wherein pixel data of each target pixel has at least one color channel data corresponding to at least one color channel; determining a bit budget of the target pixels; and performing bit-plane scanning coding upon selected pixels according to the bit budget and a scanning order, and accordingly generating encoded pixel data of the selected pixels as encoded data of the target pixels, wherein the selected pixels are derived from the target pixels, and the bit-plane scanning coding extracts partial bits of pixel data of each selected pixel as encoded pixel data of the selected pixel. In addition, a corresponding image decoding method is provided.

Method for transmitting and method for receiving a binary data stream, transmitter and receiver for carrying out the method

Abstract: A transmitter of a binary data stream comprises: a serial/parallel converter to split the binary data stream into m different parallel bit streams, each bit stream having a rate D/m which is m times lower than the initial rate D; m first encoding modules to error-correcting encode each bit stream individually; a time-interleaver to intermix the information bits originating from different encoded bit streams; an encoder to error-correcting encode the m interleaved bit streams into p bit streams; p electro-optical modulators to modulate each of the p bit streams delivered by the interleaver by means of p optical carriers of different wavelengths; and a wavelength-division multiplexer to combine the less p optical carriers into a single optical signal.

Bit error pattern analyzer and method

Abstract: The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

Techniques and devices for performing arithmetic

Abstract: A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.

Increased bandwidth encoding scheme and synchroniation using data edges

Abstract: Various methods, devices and systems are described herein that correspond to an encoding scheme that can be used with various communication protocols for increased bandwidth over a single wire bus or a wireless single transmission channel. For example, a method of encoding a series of data bits to increase bandwidth may comprise selecting a data bit in the series of data bits, generating an inverted version of the selected data bit, positioning the inverted version of the selected data bit in a consecutive fashion with respect to the selected data bit to signify an edge of a clock signal, and transmitting the inverted version of the selected data bit and the series of data bits with each bit being transmitted in a single unique time slot.

Method of searching character string, character string searching device, and recording medium

Abstract: A method includes comparing, in units of a first bit length, a first bit sequence of the first bit length included in a search character bit sequence to a second bit sequence of a second bit length included in a target character bit sequence; when a third bit sequence of the first bit length following the first bit sequence in the search character bit sequence matches a fourth bit sequence of the first bit length following a location matching the first bit sequence in the second bit sequence, creating a fifth bit sequence of the second bit length starting from a location matching the first bit sequence in the target character bit sequence; comparing, in units of the first bit length, the fifth bit sequence to a sixth bit sequence of the second bit length starting from the first bit sequence in the search character bit sequence; and determining.

A New Digital Image Hiding Algorithm Based on Wavelet Packet Transform and Singular Value Decomposition

Abstract: The paper presents a new digital image hiding algorithm based on wavelet packets transform and singular value decomposition. The low-frequency sub-band of wavelet packets transform has strong anti-jamming capacity and the singular value has very strong stability. The presented algorithm implements bit plane decomposition on the secret image and wavelet packet decomposition on the carrier image. Then, it hides the bit planes with important information into the singular value matrix of the low frequency coefficient matrix, and also hides the bit planes with secondary information into the remainder sub-band matrix with higher entropy energy. The hiding location is adaptively determined by the carrier image. The experimental results indicate that, the proposed image hiding algorithm has strong robustness and anti-attack, and it also has good invisibility and big capability.

Context-Adaptive Modeling for Wavelet-Domain Distributed Video Coding

Abstract: The authors propose a bit-level context-adaptive correlation model to exploit high-order statistical correlation for wavelet-domain distributed video coding (DVC). The magnitude and sign of each coefficient are coded separately in a bit-plane fashion. The context for magnitude bit plane are designed based on the side information (SI), the local neighborhood, and the parent coefficient. The sign bit plane takes the sign of the SI as the context. The authors also introduce SI binning to classify the SI based on its quality. The SI's class is then included in the contexts for both magnitude coding and sign coding. Experimental results show that the proposed scheme provides significant coding gain over existing DVC systems.

Nonvolatile logic array with built-in test result signal

Abstract: A system on chip (SoC) (100) provides a nonvolatile memory array (1 10) that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

An Efficient Bit Plane X-OR Algorithm for Irreversible Image Steganography

Abstract: The science of hiding secret information in another message is known as Steganography; hence the presence of secret information is concealed. It is the method of hiding cognitive content in same or another media to avoid recognition by the intruders. This paper introduces new method wherein irreversible steganography is used to hide an image in the same medium so that the secret data is masked. The secret image is known as payload and the carrier is known as cover image. X-OR operation is used amongst mid level bit planes of carrier image and high level bit planes of data image to generate new low level bit planes of the stego image. Recovery process includes the X-ORing of low level bit planes and mid level bit planes of the stego image. Based on the result of the recovery, subsequent data image is generated. A RGB color image is used as carrier and the data image is a grayscale image of dimensions less than or equal to the dimensions of the carrier image. The proposed method greatly increases the embedding capacity without significantly decreasing the PSNR value.

Radio communication apparatus and communication method

Abstract: Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into or ‘0’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.

Efficient address translation caching in processor that supports large number of different address spaces

Abstract: A processor includes translation-lookaside buffer (TLB) (206) and a mapping module (204). The TLB (206) includes a plurality of entries (300), wherein each entry of the plurality of entries (300) is configured to hold an address translation (306, 308) and a valid bit vector (302, 304), wherein each bit of the valid bit vector (302, 304) indicates, for a respective address translation context, the address translation (306, 308) is valid if set and invalid if clear. The TLB (206) also includes an invalidation bit vector (302, 304) having bits corresponding to the bits of the valid bit vector (302, 304) of the plurality of entries (300), wherein a set bit of the invalidation bit vector (302, 304) indicates to simultaneously clear the corresponding bit of the valid bit vector (302, 304) of each entry of the plurality of entries (300). The mapping module (204) generates the invalidation bit vector (302, 304).

LSB replacement steganalysis method based on grey co-occurrence matrix statistic features

Abstract: The invention discloses an LSB replacement steganalysis method based on grey co-occurrence matrix statistic features. The method includes the steps of image bit plane decomposition, grey co-occurrence matrix calculation, feature selection and extraction and classification. Firstly, a grey image is decomposed into eight bit planes, differential matrixes between the lowest bit plane and other seven bit planes are respectively calculated, then a sum matrix of the differential matrixes is calculated, a grey co-occurrence matrix of the sum matrix is generated, the obvious features are extracted and calculated by researching and analyzing the characteristics of the co-occurrence matrix, and a support vector machine is used as a classifier to distinguish carrier images and hidden images. According to the method, the number of feature dimensions is small, curse of dimensionality is effectively avoided, detection precision is high, an algorithm is stable, robustness of image processing of retaining operations of JPEG compression, median filtering, noise addition and the like is achieved, satisfying generalization ability is achieved, and calculation complexity is low.

Binary difference operations for navigational bit streams

Abstract: A computing device may identify a series of bits representative of a first binary large object (BLOB) for navigation data including road segments and road attributes. The computing device duplicates each bit of the series of bits a predetermined number of times to form a first bit string. The first bit string is larger than the series of bits by a factor of the predetermined number. The computing device performs a binary difference of the first bit string to a second bit string representative of a second BLOB. A result of the binary difference is stored in a navigation patch file.

Fast motion estimation based on enhanced constrained one-bit transform

Abstract: An enhanced constrained one-bit transform (C1BT)-based fast motion estimation (ME) method is proposed. Binary transform-based ME identifies the proper motion vector by transforming the 8-bit pixels in the original image into a low bit depth of the bit plane, substantially reducing the computational complexity and facilitating hardware implementation by using the number of non-matching points (NNMPs) instead of the sum of absolute difference (SAD). However, a motion block size is N × N , therefore the dynamic range of NNMP (0 ≤ NNMP ≤ N × N ) is decreased to 1/256 compared to that of the SAD with 8-bit images (0 ≤ SAD ≤ 256 × N × N ). The higher the NNMP between the current bit plane and the previous bit plane, the more probable that it will be the block most similar to each other. Therefore, the matching error criterion of NNMP is extended to improve ME performance. Experimental results show that the proposed algorithm improves the performance of ME accuracy by 0.27, 0.38 and 0.67 dB compared to the C1BT-based ME, two-bit transform (2BT)-based ME and 1BT-based ME, respectively.

Real-time electronic image stabilizing method with wide-range rotation and horizontal movement estimating function

Abstract: The invention relates to a real-time electronic image stabilizing method with the wide-range rotation and horizontal movement estimating function to solve the problems that according to an existing real-time electronic image stabilizing method based on gray information, the wide-range rotation movement of an image cannot be accurately estimated, the wide-range image interframe rotation and horizontal movement cannot be accurately estimated through a block matching searching algorithm, the image stabilizing effect on a shaking video with the monotonous gray level hue is poor due to the fact that only the block matching image stabilizing method is adopted, and the robustness is weak. According to the image stabilizing method, an image bit plane pyramid middle layer is utilized for carrying out block matching to resolve the interframe rotation movement angle. The image bit plane pyramid self-adaptation block selecting matching is matched with a projection method based on the image bit plane pyramid to estimate the adjacent interframe horizontal movement, and searching is carried out through an improved hexagon search algorithm. The real-time electronic image stabilizing method is used on real-time electronic image stabilizing occasions where the wide-range rotation and horizontal movement estimation needs to be carried out.

Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors

Abstract: A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.

Identification of Retinal Image Features Using Bitplane Separation and Mathematical Morphology

Abstract: This paper demonstrates a method for the detection and extraction of features like optic disc and macula from the retinal images. Digital fundus images are becoming popular for the diagnosis of ophthalmic pathologies. Due to this, there is an increasing possibility of applying digital image processing techniques and methods in these images to m the make the diagnosis more easier. In this paper first bit plane separation is done to the pre-processed retinal image. To carry the vital information of the location of optic disc and macula are found by bit plane 0 and bit plane 1. The exact boundary is identified by applying mathematical morphology. The proposed algorithm is simple and has been evaluated on the images collected from a reputed eye hospital. An accuracy of 91% was obtained in extracting the optic disc and macula from the retinal image.

Bit line sensing methods of memory devices

Abstract: Bit line sensing methods may be provided The methods may include pre-charging a first bit line and a second bit line with a bit line pre-charge voltage The first bit line may be connected to a first input terminal of a first inverter, and the second bit line may be connected to a second input terminal of a second inverter The method may also include adjusting voltages of the first bit line and the second bit line corresponding to either threshold voltages of first and second pull-down circuits included in the first and second inverters respectively or threshold voltages of first and second pull-up circuits included in the first and second inverters respectively The method may further include sharing charges of one of the first bit line and the second bit line with charges of a corresponding memory cell and amplifying a voltage difference between the first bit line and the second bit line

An analysis of the effects of bit plane extraction in fingerprint recognition

Abstract: This paper discusses about the effects of bit plane extraction in fingerprint recognition. An alternative approach to recognise a fingerprint from extracted bit plane is analysed in attempt to find the best bit plane used for recognition. An 8-bit greyscale fingerprint image is extracted into 8 different bit planes. Each bit plane of the images is then used as the input image for recognition. A fingerprint recognition algorithm using phase-only correlation (POC) is applied on the extracted bit planes. Based on the results of the analysis, the average recognition rate achieved in bit plane 7 is higher compared to the other bit planes. Three hundred samples of fingerprint images from FingerDOS are used for the experimental purposes.

Systems and methods for improving communication sensitivity

Abstract: A method for improving communication sensitivity by a wireless communication device is described. The method includes obtaining a string of bits. The method also includes mapping each bit in the string of bits to a pre-allocated bit pattern to create a series of concatenated pre-allocated bit patterns. The method further includes generating a modulated signal based on the series. The method additionally includes transmitting the modulated signal.

Analog-to-digital converter and method of converting an analog signal to a digital signal

Abstract: An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit.

An EVCS for Color Images with Real Size Image Recovery and Ideal Contrast Using Bit Plane Encoding

Abstract: Conventional visual secret sharing schemes generate noise-like random pixels on shares to hide secret images. It suffers a management problem, because of which dealers cannot visually identify each share. This problem is solved by the Extended Visual Cryptography scheme (EVCS). However, the previous approaches involving the EVCS for general access structures suffer from a low contrast problem. This paper proposes a new (k,n)-threshold image sharing scheme using extended visual cryptography scheme for color images based on bit plane encoding that encrypts a color image in such a way that results of encryption is in the form of shares. Shares do not reflect any information directly, information is scrambled instead. The traditional binary EVCS is used to get the sharing images at every bit level of each principle component of a color image. This scheme provides a more efficient way to hide natural images in different shares. Furthermore, the size of the hidden secret can be recovered by inspecting the blocks in the shares. This new scheme for color images gives the ideal contrast in the recovered image.

High-speed digital signal processing systems

Abstract: Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.

Image encoding method and apparatus with rate control by selecting target bit budget from pre-defined candidate bit budgets and related image decoding method and apparatus

Abstract: An image encoding method with rate control includes at least the following steps: defining a plurality of candidate bit budgets corresponding to different pre-defined maximum encoded bit lengths for one coding unit respectively; when encoding pixel data of a plurality of pixels within a current coding unit of an access unit of a frame, determining a target bit budget selected from the candidate bit budgets and allocating the target bit budget to the current coding unit; and outputting encoded pixel data of the pixels within the current coding unit that is generated from the encoder, wherein a bit length of the encoded pixel data is smaller than or equal to the target bit budget.