Showing papers on "Bus network published in 1998"

Bus interface system and method

Abstract: A system and method for reconfiguring a peripheral device (54) connected by a computer bus (60) and port to a host (52) from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device (76) for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.

On-chip bus architecture that is both processor independent and scalable

Abstract: A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.

Avoiding the babbling-idiot failure in a time-triggered communication system

Abstract: In a distributed hard real-time system based on a broadcast bus for inter-node communication, it is important to prevent a single faulty node from monopolizing the communication bus. In a time-triggered system, in which messages are broadcast according to a pre-determined transmission pattern, this kind of failure is characterized by the faulty node transmitting messages at arbitrary points in time, thus corrupting the transmissions on the bus. This type of failure is known as the babbling-idiot failure. Within the presented approach, a special device, the bus guardian, is added to each node to protect the communication bus from the babbling-idiot failure. The regular transmission pattern of a time-triggered system is exploited in order to enforce a fail-silent behaviour of the node in the time domain. The paper describes the requirements imposed on the bus guardian to enforce fail-silent behaviour of the node. The mechanisms of the bus guardian are presented, along with the node architecture necessary for implementing the presented technique.

Intelligent sensor system with network bus

Abstract: This invention disclosure describes an intelligent sensor system in which different types of sensors are connected to a network communication bus. Analog and digital signals are transferred bi-directionally on the common communication bus between the distributed sensors and an application specific controller referred to as a bus converter/controller module (BCM). The traditional analog type sensors are connected to the communication bus through interface devices referred to as transducer-to-bus interface modules (TBIM). The TBIM provides sensor identification, self-test and data correction functions.

High frequency bus system

Abstract: A high frequency bus system (450) which insures uniform arrival times of high fidelity signals to the devices (510), despite the use of the bus (450) on modules (420) and connectors. The high frequency bus system (450) includes a first bus segment having one or more devices (510) connected between a first and second end. The high frequency bus system (450) also includes a second bus segment which has no devices connected to it. The first end of the first segment and the second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device (510) connected to the first bus segment at substantially the same time. Conversely when two signals originate at a device (510) substantially at the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data, or control, carried by the signals.

Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices

Abstract: The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primacy bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.

Apparatus and methods for home networking

Abstract: A multimedia data distribution system comprises a distribution system adapted to distribute and deliver Asynchronous Transfer Mode signals to the level of an individual home network bus, a micro-PBX connected to the distribution system and to the home network bus; and a converter connected to the home network bus and having an outlet adapted for connecting to conventional single media and multimedia electronic devices, such as telephones, personal computers, fax machines, television sets, and the like. The micro-PBX is adapted to translate between the public network data protocol and a Local Area data protocol on the home network bus, and to manage the home network bus as a Carrier Sense Multiple Access/Collision Detect (CSMA/CD) type bus, and the converter is adapted to convert signals on the home network bus to a form required by one of the single media and multimedia electronic devices. In an alternative embodiment of the invention signals on the home network are provided as high-frequency, spread-spectrum signals.

System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system

Abstract: A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the

Apparatus and method for processing packetized information over a serial bus

Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

Diagnostic/control system using a multi-level I2C bus

Abstract: A diagnostic/control system using a multi-level I 2 C bus, includes: multiple I 2 C bus master devices (MD 0 to MDn) connected to a primary I 2 C bus; a I 2 C bus multiplexer module, which separates multiple secondary I 2 C buses from said primary I 2 C bus, and which connects as many I 2 C bus slave devices (SD 00 to SD 0 N, SD 10 to SD 1 N, . . . , SDN 1 to SDNN) are needed on said secondary I 2 C bus; and I 2 C bus slave devices (SD 00 to SD 0 N, SD 10 to SD 1 N, SDN 1 to SDNN) connected to said secondary I 2 C bus. The I 2 C bus multiplexer module provides access at any instant between any I 2 C bus master device (MD 0 to MDn) and any I 2 C bus slave device on the secondary I 2 C bus.

Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system (10) are disclosed herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system (10). These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system (10). In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses (50, 52, 54) which make up the bus arrangement. Systems (10) disclosed may include any number of individual buses within their bus arrangements. In one implementation, a system includes a single address bus (50) and two or more data buses (52, 54) such that different data transfers may be executed simultaneously on each data bus.

Architecture for a high-performance network/bus multiplexer interconnecting a network and a bus that transport data using multiple protocols

Abstract: A high-performance network/bus multiplexer that exchanges data transfer commands and data between different communications mediums, such as the Fibre Channel and one or more SCSI buses. High-performance is achieved by avoiding transmitting read bus operations through bus bridges, and by limiting contention for buses by connecting Fibre Channel host adapters to a first internal bus and SCSI adapters to a second internal bus.

Method of peer-to-peer mastering over a computer bus

Abstract: A method of communication between requester and target devices in a computer system having a multiple bus architecture. The method supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The method employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The method comprises the act of establishing a handshake with a host master and issuing a request over the host bus. The method further comprises the act of acknowledging the request and transmitting a deferred response to the requester.

Hot plug connected I/O bus for computer system

Abstract: A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at least one of the bridge controller ports via one or more first buses. There are one or more second buses coupled to the I/O bus bridge.

Serially linked bus bridge for expanding access over a first bus to a second bus

Abstract: A bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is coupled between the second bus and the link. The first interface and the second interface are operable to (a) send bus-related information serially through the link in a format different from that of the first bus and the second bus, (b) approve an initial exchange between the first bus and the second bus in response to pending transactions having a characteristic signifying a destination across the bridge, (c) exchange bus-related information between the first bus and the second bus according to a predetermined hierarchy giving the first bus a higher level than the second bus, and (d) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

Device for blocking bus transactions during reset

Abstract: The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.

Microcomputer having multiple bus structure coupling CPU to other processing elements

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

High-speed processor system having bus arbitration mechanism

Abstract: A high-speed processor system having a bus arbitration mechanism constructed on a single semiconductor chip. The processor system comprises at least one bus master, a plurality of buses and a plurality of bus slaves. Each bus comprises an independent address bus, an independent data bus and individual data transfer capability. Every bus master comprises a plurality of independent bus interfaces each connected to one of the buses. Each bus slave is connected to a bus that has corresponding data transfer capability. For a system having more than two bus masters, the system further comprises a plurality of bus arbitrators for arbitrating the access of each bus independently. The bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus. The bus arbitrator comprises a plurality of priority order information storage devices for storing priority order information for all the bus masters connected to the bus. At every bus cycle, one set of priority order information is selected continuously and cyclically. When more than one bus master requests the bus access at the same time, the bus arbitrator determines which bus master may access the bus according to selected priority order information.

Intelligent system and method for universal bus communication and power

Abstract: A bus hub for connection via a serial bus to a serial bus host hub includes a connector to a power supply, a bus controller and a switch coupled to the bus controller and to the power supply. The switch switches the bus hub between being powered by the power supply and being powered by the power from the serial bus host hub by switching the mode of operation between self-powered mode and bus-powered mode. A system for controlling communication and power in a serial bus includes a serial bus hub for detachably coupling at least one peripheral to a computer system, and a serial bus host hub capable of delivering power to the serial bus hub. The system also includes a power supply coupled to the serial bus hub that delivers power to the serial bus hub. The system also includes a bus controller that receives signals from the computer system through the serial bus, and receiving signals from the serial bus hub. The system also includes a switch that switches the serial bus hub between being powered by the power supply and being powered by the power from a serial bus host hub.

Multiple interface input/output port allows communication between the interface bus of the peripheral device and any one of the plurality of different types of interface buses

Abstract: A multiple interface input/output port allows communication between an interface bus of a peripheral device and any one of a plurality of different types of interface buses that may be provided in a host computer. An interface bus detection circuit detects which type of interface bus the peripheral device is connected to on the host computer, and communications are then routed through an appropriate interface adapter that enables communication between the interface buses of the peripheral device and host computer. The interface bus detection circuit compares signal levels on selected ones of the lines of the interface bus of the host computer to a reference potential to determine which of the selected lines are grounded. The circuit then identifies the type of interface bus to which it is connected based on the determination of which of the selected lines of the interface bus are grounded.

Bus mastering interface control system for transferring multistream data over a host bus

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.

Information system for informing users of a public transport network about waiting times at stops in the network

Abstract: An information system for informing users of a bus network about waiting times for buses at stops in the network. The system includes a system for locating buses coupled to a central point which broadcasts said positions at successive instants θ to receivers adapted to calculate waiting times for the buses on the basis of their positions, which positions reach the receivers after a certain average length of “transit” time T. In order to ensure that calculated waiting times as are accurate as possible, the central computer point broadcasts to the receivers estimated positions that the buses are expected to occupy at instant θ+T.

Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Method and apparatus for exchanging information between buses in a portable computer and docking station through a bridge employing a serial link

Abstract: A docking system can give a portable computer access over a first bus in the portable computer to a second bus in a docking station The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices The docking system has a serial link cooperating with a first and a second interface to act as a single bridge The first interface is coupled between the first bus and the link The second interface is coupled between the second bus and the link The first interface and the second interface are operable to (a) send bus-related information through the link in a format different from that of the first bus and the second bus, and (b) allow the portable computer, communicating through the first bus, to individually address one or more of the bus-compatible devices on the second bus using on the first bus substantially the same type of addressing as is used to access devices on the first bus

Redundant bus bridge systems and methods using selectively synchronized clock signals

Abstract: A redundant bus bridge system for communicating between a first bus and a second bus includes a first clock generator operative to produce a first clock signal and a second clock generator operative to produce a second clock signal. A first bus bridge, e.g., a first RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. A second bus bridge, e.g., a second RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. According to aspects of the present invention, the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the second clock signal when the second bus bridge is operational, and the first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with the first clock signal when the second bus bridge is non-operational.

Data bus system for motor vehicles

Abstract: A data bus system for motor vehicles with a number of electronic bus stations, each having an input port that is connected to the motor vehicle battery to supply power to the bus stations. Each bus station is equipped with a detector circuit and a controllable switch. Each bus station is turned off in the ground state when the ignition is turned off, with the exception of the detector circuit assigned to it, by positioning the controllable switch into an open position in a selective wake state. The controllable switch of each selected bus station is closed by its detector circuit while the temporarily required data exchange between selected bus stations takes place. At least one of the bus stations is defined as the main bus station to control the wake state.

Apparatus and method for bus timing compensation

Abstract: A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

Interfacing vehicle data bus to intelligent transportation system (ITS) data bus via a gateway module

Abstract: A data exchange gateway for enabling the exchange of data between a vehicle data bus (VDB) and an intelligent transportation system (ITS) data bus The gateway includes a memory accessible by both a VDB interface and an ITS data bus interface so that data and commands may be shared between each respective bus through the shared memory