Showing papers on "Bus network published in 2000"

Control system for a marine vessel

Abstract: A control system for a marine vessel incorporates a marine propulsion system that can be attached to a marine vessel and connected in signal communication with a serial communication bus and a controller. A plurality of input devices and output devices are also connected in signal communication with the communication bus and a bus access manager, such as a CAN Kingdom network, is connected in signal communication with the controller to regulate the incorporation of additional devices to the plurality of devices in signal communication with the bus whereby the controller is connected in signal communication with each of the plurality of devices on the communication bus. The input and output devices can each transmit messages to the serial communication bus for receipt by other devices.

A homogeneous linear programming algorithm for the security constrained economic dispatch problem

Abstract: This paper presents a study of the simplified homogeneous and self-dual (SHSD) linear programming (LP) interior point algorithm applied to the security constrained economic dispatch (SCED) problem. Unlike other interior point SCED applications that consider only the N security problem, this paper considers both (N-1) and (N-2) network security conditions. An important feature of the optimizing interior point LP algorithm is that it can detect infeasibility of the SCED problem reliably. This feature is particularly important in SCED applications since line overloading following a contingency often results in an infeasible schedule. The proposed method is demonstrated on the IEEE 24 bus test system and a practical 175 bus network. A comparison is carried out with the predictor-corrector interior point algorithm for the SCED problem presented previously (see ibid., vol. 12, no.2, p.803-10, 1997).

Bus system optimization

Abstract: A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimise transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.

Multi-tier point-to-point ring memory interface

Abstract: Methods and apparatus for a memory system using a ring memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains point-to-point bus connections with each of two memory modules; the two modules maintain a third point-to-point bus connection between themselves, such that the three connections together form a ring bus. When data is sent from the controller to a module, half of the data is sent to the module in one direction along the ring and half is sent in the other direction, through the other module. Reverse bus communications from the module to the controller follow the reverse of these paths. This allows the bus to be half the width as it would otherwise be. In an alternate embodiment, each module contains two banks of memory that are arranged in a second ring bus local to the module. This can double the density of devices mounted on a module, while reducing pin count and simplifying signal routing on the module.

Firewall including local bus

Abstract: A gateway for screening packets transferred over a network. The gateway includes a plurality of network interfaces, a memory and a memory controller. Each network interface receives and forwards messages from a network through the gateway. The memory temporarily stores packets received from a network. The memory controller couples each of the network interfaces and is configured to coordinate the transfer of received packets to and from the memory using a memory bus. The gateway includes a firewall engine coupled to the memory bus. The firewall engine is operable to retrieve packets from the memory and screen each packet prior to forwarding a given packet through the gateway and out an appropriate network interface. A local bus is coupled between the firewall engine and the memory providing a second path for retrieving packets from memory when the memory bus is busy.

Bus diagnostic and control system and method

Abstract: A system and method allow for remote control of a bus or other vehicle and for collection of bus operating and diagnostic data collected from an bus onboard data collection and control system. The system allows for wireless communication between the bus and a local bus operating center. The bus operating center may include an Internet web site and an Internet server that receives the data from the bus. The data may be aggregated for several buses, or may be retained on an individual bus basis. The system and method provides for non-intrusive diagnosis of the bus or other vehicle. The system includes an onboard computer that contains vehicle operating and diagnosis programs. The computer may be interfaced locally at the bus, or remotely from another location. Parameter values of bus components may be displayed using human to machine interfaces. The interfaces may include virtual objects that represent actual bus components or that are used to display component parameters in a readily readable fashion.

Communication management system and method

Abstract: Broadband multimedia system including a communication bus, a router, connected to the communication bus and further between a plurality of media sources and a plurality of network transmitters, a session manager, connected to the communication bus, where the session manager provides routing instructions to the router, for directing data received from the media sources to the network transmitters for transmitting over a broadband network.

Quad pumped bus architecture and protocol

Abstract: A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

Bus-invert coding for low-power I/O - a decomposition approach

Abstract: This paper proposes a new bus-invert coding scheme for reducing the number of bus transitions. Unlike the previous schemes in which the entire bus lines or one subset of the bus fines are considered for bus-invert coding, in the proposed scheme the bus lines are partitioned and each partitioned group is considered independently for bus-invert coding to maximize the effectiveness of reducing the total number of bus transitions. Experimental results show that the decomposed bus-invert coding scheme reduces the total number of bus transitions by 47.2% and 11.9% on average than those of the conventional and the partial bus-invert coding schemes, respectively.

Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors

Abstract: Disclosed is a fully-interconnected, heterogenous, multiprocessor data processing system. The data processing system topology has a plurality of processors each having unique characteristics including, for example, different processing speeds (frequency) and different cache topologies (sizes, levels, etc.). Second and third generation heterogenous processors are connected to a specialized set of pins, connected to the system bus. The processors are interconnected and communicate via an enhanced communication protocol and specialized SMP bus topology that supports the heterogeneous topology and enables newer processors to support full downward compatibility to the previous generation processors. Various processor functions are modified to support operations on either of the processors depending on which processor is assigned which operations. The enhanced communication protocol, operating system, and other processor logic enable the heterogenous multiprocessor data processing system to operate as a symmetric multiprocessor system.

I2C bus protocol controller with fault tolerance

Abstract: In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, cyclic redundancy check (CRC), and byte count check operations. The I2C bus controller may include a control unit connected to an I2C core module having a base address. The I2C bus controller may also include a second I2C core module having a base address plus one (BP1). The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or, in the master mode, from itself through the BP1 I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus. The control unit may format CRC values and byte count values into messages, and include a byte counter to compare actual bytes received to the expected byte count indicated by a received byte count value.

Mechanism for managing multiple out-of-order packet streams in a PCI host bridge

Abstract: A circuit is provided that includes a bridge circuit for connecting a first bus to a second bus. The bridge circuit also includes a first bus interface coupled to the first bus and is adapted to receive a plurality of transactions from the first bus. Each transaction has an address targeting the second bus and data the length of which defines a transaction size. A request data engine for issuing requests on a second bus is also provided. The request data engine is capable of assigning a unique encoded header to data streams. Control logic is provided that is adapted to store a first portion of a first transaction of the plurality of transactions in a memory coupled between the first bus and the second bus. Management logic is provided that is adapted to manage multiple out-of-order data streams wherein the data streams may remain outstanding to the bridge circuit. Additionally, a method is provided that includes capturing a data stream request header. Determining which data stream a request is mapped into. Assigning a unique encoded header to a data packet. Issuing request packets with the unique encoded header. Receiving completion request data packets. Setting a first pointer in a memory. Incrementing a portion of a memory address. Checking if all data packets are stored in the memory. And, managing multiple out-of-order data streams wherein the data streams may remain outstanding to a bridge circuit.

Communication apparatus and method between distributed objects

Abstract: Disclosed is a communication apparatus between distributed objects comprising: a plurality of separate software buses adapted to determine whether or not a communication service of which function and property is provided in a distributed platform; a platform administrator adapted to build and administrate a communication architecture in the distributed platform; a bus manager adapted to manage both a standard of types of the plurality of software buses and a bus object instance in the distributed platform by a strategic plan and an instruction of the platform administrator; a bus trader adapted to provide a trade function through an interaction with the bus manager, and a client object and a server object of an application level; an object trader adapted to allow the client to dynamically find an appropriate server; a repository adapted to provide a function which stores persistently instance information and various types of the plurality of software buses; a bus adapter adapted to provide the client and server objects with an application programing interface (API) associated with a bus binding process for use of the distributed platform, and adapted to perform a necessary trade and the bus binding process through an interaction with the bus trader and the plurality of buses; and a bus factory adapted to create a bus object coinciding with the standard of types of the plurality of software buses.

Method and mechanism to use a cache to translate from a virtual bus to a physical bus

Abstract: Intermediary inclusive caches (IICs) translate between some number of processors using virtual addressing and a physically addressed bus. The IICs support at least one virtual bus (upper bus) connecting the IICs to central processor units (CPUs), and at least one physical bus (lower bus) connecting the IICs to a memory controller, input/output (I/O) devices and perhaps other IICs. Whenever a CPU makes a request of memory (on the upper bus), the request is looked up in an IIC. Should the data reside in the IIC, the data is provided to the CPU from the IIC through the upper bus (except in the case of coherency filters which do not cache data). If the request misses the IIC, the request is repeated on the lower bus. When the requested data comes back from the lower bus, the data is cached in the IIC and passed up to the requesting CPU through the upper bus. Whenever a snoop request comes in from the lower bus, the snooped (requested) data is looked up in the IIC. Should the snoop miss the IIC, that is the requested data is not in the IIC, the request need not be repeated on the upper bus. In the case of the snoop hit on the IIC, the snoop may be repeated on the upper bus if a coherency protocol requires.

Bridging a host bus to an external bus using a host-bus-to-processor protocol translator

Abstract: An expansion module for a Handspring Visor (which conforms to the Springboard bus specification) includes a multi-master AMBA Advanced System Bus (ASB). Optionally, an Arm7 processor is attached to this bus via an Arm7 to ASB interface as one master. The Springboard bus of the visor is coupled to the ASB bus via a Springboard-to-ASB-bus bridge. This bridge comprises a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of said buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition. A programmable counter adjusts maximum counts to compensate for different clock frequencies, in measuring a write-wait state duration to ensure valid writes from the Visor to the ASB bus. Using this basic design framework, a developer of Springboard expansion modules can take immediate advantage of the performance and the variety of peripherals available for the ASB bus. Furthermore, using the same translator and merely changing the interface to the external bus, a Springboard developer can take advantage of peripherals developed for other external buses as well.

Connection control apparatus

Abstract: There is provided a connection control apparatus (10) which, even when a plurality of such connection control apparatuses are connected to a bus such as the 1394 bus through which packet-based bidirectional serial communication is possible and to which a plurality of AV devices can be connected, makes it possible to know to which connection control apparatus the right of controlling each device connected to the bus belongs by collecting information about the control status of each connection control apparatus, thereby to carry out a high level of management of connections to and controls of the bus. Each connection control apparatus (10) connected to a bus, through which packet-based bidirectional serial communication is possible and to which a plurality of AV devices can be connected, comprises a control flag register (44) and a control information register (46) for storing the status of connection of the present device through the bus to other devices as well as the status of connection of the other devices to one another through the bus.

Serial bus communication system

Abstract: A method includes determining a first transfer function that characterizes a distortion introduced by a serial bus. A filter is designed to substantially cancel the distortion introduced by the first transfer function, and a signal is transmitted to the serial bus through the filter.

Portable terminal with bus manager switching function

Abstract: A portable terminal, includes a host detector, a hub circuit and a bus manager circuit. The host detector detects whether a host operates as a bus manager. The hub circuit has a hub function and is connectable to an external device. The bus manager circuit has a bus manager function. The bus manager circuit stops the bus manager function such that the host can operate as the bus manager for the portable terminal and the external device connected to the portable terminal, when the host operates as the bus manager. Also, the bus manger circuit carries out the bus manager function such that the bus manager circuit can operate as the bus manager for the portable terminal and the external device connected to the portable terminal, when the host does not operate as the bus manager.

Bus architecture for system on a chip

Abstract: A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Information communication system, information communication method, information signal processing device and information signal processing method, and storage medium

Abstract: When a plurality of information signal processing apparatuses are connected via IEEE 1394 communication control buses, these buses are connected via bridges, and bus reset occurs on a remote bus other than connected buses (step S1501), occurrence of remote bus reset is notified (steps S1502, S1505). Thus, even if bus reset occurs, the consistency of bus reset processing in an upper protocol layer can be ensured to realize normal data communication between buses.

Routing processing and method for home bus system

Abstract: In a home bus system in which a multiplicity of networks each having a multiplicity of appliances connected thereto are connected one another, information is easily exchanged between appliances over different networks. An address configuration that is processed in application software and communication middleware has a network ID and a network appliance ID. On each network, there is provided a particular router having information about all the connections of other networks than the each network. Under this configuration, an appliance transmits a message directed to another network, only to a particular router and the particular router establishes an appropriate route for transmission, as considering the actual states of the networks.

Method and apparatus to reduce power consumption on a bus

Abstract: Method and apparatus for reducing the power consumed by a bus. In one embodiment, the method may comprise placing a bus node in a reduced power consumption state wherein the signaling integrity of a multiport bus interface continues such that The multiport bus interface forwards messages received when the bus node is in the reduced power consumption state. The bus node is returned from the reduced power consumption state to a fully powered state upon receiving one of a plurality of wake events that may serve other purposes as normal signaling on the bus. In one embodiment, an apparatus may comprise complex logic to control what state the apparatus is in; a link circuit coupled to the complex logic; and a physical layer (PHY) coupled to the link circuit to provide a bus interface. The PHY and the link circuit remain active when the apparatus is in a particular state, such as reduced power state. In this way, the apparatus may act as a repeater for traffic on the bus.

Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor

Abstract: A wireless communication system-on-a-chip (20) comprises a system bus (24), a set of fixed function processors (32) connected to the system bus (24), an embedded processor (28) connected to the system bus (24), and reconfigurable logic (30) connected to the system bus (24). The reconfigurable logic (30) supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.

Software interface between a parallel bus and a packet network

Abstract: A bridge device, for coupling a parallel bus to a packet network, includes a bus interface adapter, coupled to the parallel bus so as to receive bus cycles from a master device on the bus. An outbound packet register, having a bus address in an address space of the bus, is adapted to store an outbound network address header and payload data written to the bus address of the register by the master device in one or more of the bus cycles received by the bus interface adapter. A network interface adapter is coupled to the network so as to transmit over the network an outbound packet containing the outbound network address header and payload data from the register, to a target device on the network specified by the network address header.

Terminal for field bus, control method for the terminal and field bus system having the terminal

Abstract: PROBLEM TO BE SOLVED: To provide a terminal for a field bus whose power consumption can be reduced, to provide a control method for the terminal and a field bus system having the terminal. SOLUTION: The terminal is provided with a field bus interface circuit 3A and a microprocessor 3B. The field bus interface circuit 3A is provided with a reception means 31, a transmission means 35, a microprocessor 3B, a data register 32 that sends/receives data between the reception means 31 or the transmission means 35, a frame identification means 34 that outputs a 1st signal 34b when a received transmission frame RF is a burst token frame PT addressed to its own station, a response permission means 33 that outputs a 2nd signal 33b when the microprocessor 3B makes no communication request, and a return token transmission means 37 that outputs the 2nd signal 33b and a return token frame RT when receiving the 1st signal 34b.

Latency-guided on-chip bus network design

Abstract: Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra high level of integration mandates design of systems-on-chip that encompass numerous intra-synchronous blocks with decreased functional granularity and increased communication demands. To address these issues we have developed an on-chip bus network design methodology and corresponding set of tools which, for the first, time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus network design component optimizes the bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan and to communicate information about the most constrained parts of the network.

A new method for protection zone selection in microprocessor-based bus relays

Abstract: Use of graph theory simplifies representation of complex bus arrangements in power system stations. This paper presents a new method, based upon graph theory, for selecting bus protection zones in microprocessor-based relays. We use a typical bus arrangement to illustrate the graphical representation of station arrangements, graph operations, and associated matrix operations. We also describe an implementation of the zone selection method and use two examples to demonstrate the advantages of the method. Using the status of switching devices in the station, the zone selection method provides the relay with real-time bus arrangement information. The bus relay uses this information to assign input currents to a differential protection zone and to select which breakers to trip for a bus fault or breaker failure.

Expansion bridge apparatus and method for an I2C bus

Abstract: The present invention is an I 2 C (inter-IC control) bridge device which implements a communication protocol layered on top of a standard I 2 C protocol. The layered protocol used by the bridge device is termed the “Layered I 2 C Protocol”—abbreviated “LIP”. Thus the bridge device is called a “LIP bridge device”. The LIP bridge device provides I 2 C address extension, data integrity checking, and fault detection and isolation when inserted between an I 2 C bus master and it's intended target I 2 C device. Each LIP bridge device has at least two attached I 2 C busses—a parent bus and a child bus. The LIP bridge operates as a slave on its parent bus, and a master of its child bus. The Layered I 2 C protocol is specified to operate on a bus between one or more bus masters and the parent bus of one or more LIP bridge devices. The child bus is used for attaching multiple I 2 C devices and/or one or more LIP bridge devices. In an exemplary implementation, the LIP bridge device is constructed using a microcontroller to create a LIP bridge device with one parent and one child I 2 C bus port and a group of LIP bridge configuration pins. The parent bus traffic to a given LIP bridge device consists entirely of LIP packets, and the child bus traffic consists of standard I 2 C packets to communicate with standard child bus I 2 C devices. The child bus traffic may also consist of LIP packets to communicate with LIP bridges attached to the child bus. By design, the LIP packets and standard I 2 C transactions do not interfere with one another. The LIP bridge device interprets LIP command packets from a bus master and translates them into the intended I 2 C data stream that is then broadcast over the child bus. Likewise, data from the child bus is used to create LIP packets that are returned to the proper bus master. The use of LIP packets on a given I 2 C bus provides an extra level of I 2 C addressing.

Network comprising a plurality of network nodes for media access checks

Abstract: The invention relates to a network comprising a plurality of intercoupled network nodes. Controlled by a bus guardian the network nodes transmit messages during a respectively assigned time slot and receive messages from other network nodes outside this time slot. Each network node comprises a test signal generator which delivers a test signal outside the respectively assigned time slot, and includes a test signal detector which detects outside the respective time slot, after receiving a test signal from at least another network node, that there is a defective circuit portion in the assigned network node and/or in at least another network node.

Global access bus architecture

Abstract: Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.