Showing papers on "Circuit diagram published in 1990"

Method of and apparatus for designing circuit block layout in integrated circuit

Abstract: There are provided a method of and an apparatus for designing a circuit block layout in an integrated circuit wherein minimization of a total wiring length among the circuit blocks and compaction of the circuit blocks are automatically achieved upon automatically laying out the circuit blocks and determining wiring among those circuit blocks, by initially laying out the circuit blocks using a spring model of a mass point system where circuit blocks with no size are coupled through springs, configuring at least partial circuit blocks as circles to re-lay out the circuit blocks such that there is eliminated any overlapping among the circuit blocks, compacting the external shape of an assembly of the circuit blocks by matching the external shape with the frame of a die and altering the shape of each circuit block from the circle to an actual shape.

Structured logic design method using figures of merit and a flowchart methodology

Abstract: The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart. The Boolean equations are then converted to a logic diagram either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.

Method of designing three dimensional electrical circuits

Abstract: A computer aided design package is used to create a mathematical representation of a three-dimensional object. This object is defined as a set of surfaces oriented in space. A map of the flattened object is created by concatenating selected ones of the surfaces on a single plane. The outline of this map is then used in a computer aided circuit layout package as a printed circuit board on which an electrical circuit is placed and routed. The circuit is translated into a three-dimensional form corresponding to the surface of the object by translating and rotating the representation of the object to align each selected surface with the circuit description generated by the circuit layout package. The portion of the circuit corresponding to the surface is then transferred to a three-dimensional data structure having a format that is compatible with numerically controlled machining apparatus. This data structure is used to drive a numerically controlled phototool which creates a three-dimensional mask that may be used to print the circuit on the surface of the three-dimensional object.

Improved high-voltage, high-frequency square-wave generator

Abstract: This paper describes the design and operation of a prototype high-voltage full-floating high-frequency square-wave generator which is an improved version of the generator developed by Bernius and Chutjian (1989). The present design overcomes possible momentary simultaneous ON states in the MOSFET configuration and is less susceptible to deleterious effects caused by the component aging and replacements with nonidentical parts. The circuit performs well over a wide voltage and frequency range, until a limit is imposed by the operating characteristics of the active MOSFET elements. Circuit diagrams are presented.

LiB: a cell layout generator

Abstract: An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB. >

ALE: a layout generating and editing system for analog LSIs

Abstract: An analog LSI layout design system called ALE (analog layout editor) is described. It is applicable to block layouts for bipolar analog LSIs. ALE has two functions: a layout generator and a layout editor. With the layout generator, layouts are generated from circuit diagrams, automatically preserving the relative positions of device cells and wires. Therefore, when circuit constraints are expressed in the circuit diagram, the generated layout satisfies these conditions. The layout editor, which can be used for either circuit diagrams or layouts, provides interactive tools, making it easier to take into account constraints particular to analog circuits. This system reduces layout design time by up to 50% without any degradation of characteristics such as layout area and circuit performance. >

Schematic generation with an expert system

Abstract: A study of schematic generation by a knowledge-based system (KBS) is reported. Schematics must demonstrate features (continuity of signal flow and logical clustering) of a design while remaining simple (few turns and crossings). Algorithmic and manual techniques deal poorly with the multiple conflicting objectives. A successful switchbox router in a KBS suggested the same approach to schematic generation. Schematic generation in a KBS still needs to be partitioned into subproblems to make is tractable. Subproblems include ordering of symbols and the placement of nets (i.e., routing). The ordering of symbols in the direction of information flow is based on a precedence augmented with a rule-based component which recognizes cycles and breaks them intelligently. A heuristic length-based ordering in the other direction tries to minimize crossings. The KBS paradigm is particularly applicable to the routing steps. >

Performance driven analog layout compiler

Abstract: An approach to developing an automated analog layout compiler which results in a circuit layout based on a user-specified performance is described. The final layout is derived from sensitivities of the circuit performance with respect to layout interconnect parasitics and recognition rules of various configurations and topologies. The parasitic effects, which are important from an analog layout point of view, are minimized by this approach. This methodology is currently implemented in an analog circuit layout compiler. >

Equivalent Circuit and Output Characteristics of Super High-speed Reluctance Generator Taking Iron Losses into Consideration

Abstract: Reluctance Generator (RG) can be operated at super high-speed because of its simple, robust rotor. Thus it is found acceptable for its high ratio of power/volume or power/weight as a small power source in airplanes, vehicles, etc., where electricity cannot be transmitted from external power source.While describing the output characteristics of RG, equivalent circuit or phasor diagram is generally applied. But although the iron and copper losses are caused by different mechanisms, they were treated by using a constant equivalent resistance in the past papers. In viewpoint of loss, it was same to that only the copper loss was considered. On the other hand, the iron loss is variable with the change of voltage and frequency. And the iron loss makes up the great part of the total losses especially when the machine driven at high speed. Therefore it is natural that the iron loss should be treated precisely.In this paper, the following points are discussed.(1) A new equivalent circuit with taking iron loss into consideration is developed by introducing an iron loss conductance. A measurement method (circuit diagram method) of the circuit parameters is also proposed.(2) The circuit parameters of the test machine are measured by applying the proposed circuit diagram method. And experimental results on the test machine show the validity of the new equivalent circuit.(3) Based on the new equivalent circuit, the relationship of the RG output characteristics and circuit parameters is studied. Thus the bases to choose the circuit parameters are given.

An equivalent circuit model for arbitrarily-shaped metallisation areas on printed circuit boards

Abstract: The author describes an equivalent circuit model which has been developed to predict the electrical behaviour of large or irregularly shaped areas of metallisation on printed circuit boards An understanding of the behaviour of such areas can be vital in achieving successful implementation of RF circuit designs The underlying theory for the model is described briefly, and steps taken to ensure the efficiency of the implementation are mentioned The method of subdivision of these areas into a set of rectangular and triangular patches is detailed, and it is shown how these are associated with components in the equivalent circuit Results are presented to show the accuracy which can be achieved with this model, and the usefulness of the results in gaining an understanding of the behaviour of these areas< >

Circuit diagram display device

Abstract: PURPOSE:To efficiently design a circuit diagram by enlarging a macro block while holding a connective relation and a relative positional relation as they are. CONSTITUTION:The display device is composed of an input part 1, a processing part 2, an arithmetic part 3, and a display part 4. In the input part 1, the circuit diagram, in which hierarchical expression is used, is taken onto a memory. In the processing part 2, macro block enlarging processing 5 calculates the scale of the internal circuit of the macro block when scale matching is executed between upper and lower hierarchies, and peripheral part rearranging processing 6 adjusts the distortion of the peripheral part of the macro block caused by the macro block enlarging processing 5 while holding the connective relation and the relative positional relation as they are. Further, in the display part 4, the internal circuit is expanded and displayed in the enlarged macro block. Thus, the upper and lower hierarchies can be simultaneously seen on the same screen, and it becomes unnecessary to reload the internal circuit diagram again.

Circuit diagram editor

Abstract: PURPOSE:To eliminate the troublesome operations and input mistakes and to attain an automatic feedback operation even to the correction by using an automatic hierarchical symbol production processing means and a symbol editing processing means to automatically produce the hierarchical symbols when a hierarchical circuit is edited. CONSTITUTION:An automatic hierarchical symbol production processing means 25 collects the data on the names, the input and output attributes, etc., of the external input and output terminals of the lower rank circuits from the circuit information. Then the means 25 decides the forms of the hierarchical symbols according to the number of terminals divided right and left in response to the input and output attributes. At the same time, the means 25 sorts ascendingly the pin names corresponding to the external terminals and allocates them on the symbols to produce the hierarchical symbols of the lower rank circuits. A symbol editing processing means 23 corrects the produced hierarchical symbols and those of the existing circuits in accordance with the external input. Thus it is possible to eliminate the complicated operations for production of the hierarchical symbols as well as the input mistakes. In addition, an automatic feedback operation is attained to the hierarchical symbols even with the correction given to a produced circuit.

Automatic layout device

Abstract: PURPOSE:To automatically lay out a chip according to an IC assembling diagram and a circuit diagram by automatically laying out by considering pad positions, a limit of a chip size by the assembling diagram and reference. CONSTITUTION:A limit of a chip size which can be placed on an island 1 is set with a distance 6 from the island 1 to a chip 1 set to a predetermined length by an IC assembling diagram. A limit of a pad position is established by a limit of a distance 7 from pads 4 to inner loads 3 to a predetermined length, a limit of an interval 8 of bonding wires 5 for connecting the pads 4 to the leads 3, and a limit of an adhering part 9 of the wires 5 to the leads 3 to a predetermined length. The chip is automatically laid out with the assembling reference and design reference utilized for the automatic layout. Thus, the chip can automatically be laid out by the IC assembling and circuit diagrams.

Hierarchical symbolic design methodology for large-scale datapaths

Abstract: A hierarchical symbolic layout methodology for designing large-scale datapaths is proposed. The methodology constructs a datapath hierarchically by taking note of the bit-slice regular structure. It gives a globally optimized layout with a rapid optimizing loop. This approach has reduced design effort to 1/10 compared with conventional handcraft design (maintaining equivalent layout quality) for a datapath which includes 21 K transistors. Macrocells without bit-sliced structure are also considered to be easily embedded into the final datapath layout. Moreover, as a design entry, an LT-diagram entry is allowed for a designer. The diagram is a special logic diagram which includes topological information for gates and wirings. A stick-diagram is automatically synthesized from the LT-diagram and mask layout is generated through compaction. >

Circuit diagram generating system

Abstract: PURPOSE:To generate a circuit approximated to an old circuit by easily deciding a bundle symbol by extracting a virtual bundle symbol based on old circuit diagram information, and judging whether or not it should be set as the bundle symbol based on a bundle signal name rule. CONSTITUTION:The logical connection information of a circuit diagram targeted to generate is stored in a storage part 1, and the old circuit diagram information targeted to generate is stored in a storage part 2, and symbol groups with the same X- and Y-coordinates are found from the information in the second storage part 2, and the group is extracted with an extraction part 3 as the virtual bundle symbol when the logical connection information for the group exists in the storage part 1. A connection signal name relating to each pin of an extracted virtual bundle symbol is fetched, and it is judged whether or not it can be set as the bundle signal name with a judging part 4, and it is judged whether or not the connection signal name from the judging part 4 can be made into the group as the bundle signal name with a judging part 5 based on the bundle signal name rule in a storage part 6. An arranging wiring part 7 distinguishes a bundle symbol group decided at the judging part 4 from the symbol other than that, and arranges them on the circuit diagram, and performs wiring by distinguishing a bundle wire from a single wire.

Integrated circuit with a configuration circuit

Abstract: An integrated circuit configuration includes a configuration circuit with a potential lead and a connection device for a control potential. An electronic circuit connects the connection device to the potential lead.

Automated generation of analog schematic diagrams

Abstract: An approach to the automated generation of analog schematic diagrams is presented. The algorithms expressly address the esthetic requirements for analog schematics. There are four major algorithms: (1) functional clustering; (2) block placement; (3) wiring between blocks; and (4) block expansion. Experiments show that schematics can be automatically generated with favorable run times for large networks. Typical SPICE networks of 100 components are generated in less than five minutes. >

Method and system for automatically producing network diagram or logic circuit diagram

Abstract: PURPOSE:To effectively produce a network diagram or a logic circuit diagram containing the easy-to-understand contents shown in the diagrams and the easy- to-see connecting relation by detecting a loop out of the network diagram or the logic circuit diagram and then an area where the detected loop has the maximum duplication and deciding the cutting point of the loop based on the detected area. CONSTITUTION:A loop is detected out of a network diagram or a circuit diagram in a 1st step. An area of the detected loop where the detected loop duplication is maximum is detected in a 2nd step. In a 3rd step the cutting point is decided out of the areas detected in the 2nd step. Thus it is possible to perform the highly efficient arrangement and wiring of a network diagram or a logic circuit diagram that contains the easy-to-see connecting relation and the easy-to- understand contents shown in the diagrams.

Electric circuit diagram design system

Abstract: PURPOSE:To express a large-scale circuit with a simple drawing by substituting a generated circuit diagram with one part to register it and allowing one symbolic shape to correspond to this circuit diagram to handle it as the part. CONSTITUTION:Parts are selected from a part library 1-2 by a circuit diagram generation processing part 1-3 and are arranged and wired on a drawing on a graphic display device 1-9 to generate a circuit diagram. When this generated circuit diagram indicates a circuit which is functionally closed and has a general usefulness, a part library generation processing part 1-1 is started again to generate a shape of the part with which this circuit is substituted, and this part and the circuit diagram are allowed to correspond to each other, and this part is stored in the part library 1-2 together with circuit diagram alternative part information. The alternative part of the circuit diagram generated in this manner can be handled in the same manner as the other parts by the circuit diagram generation processing part 1-3. Thus, a circuit diagram corresponding to a block diagram is generated.

Correct cell selecting device for logic circuit

Abstract: PURPOSE:To select a correct cell in a short time by using a ratio in which a delay time of a logical gate to be taken notice of is occupied in the passing time of a signal and two degrees of freedom as evaluation functions, and deciding whether a cell used by the logical gate to be taken notice of is changed to a cell whose driving capacity is different or not and changing it. CONSTITUTION:This device is provided with a circuit diagram file 1, a data base 2 for degree of freedom 1, a data base 3 for degree of freedom 2, a delay time calculating device 4, an evaluation value calculating device 5, and a cell replacing device 6. In this state, by an evaluation value calculated from a value obtained from the degree of freedom of a change of a cell used by each logical gate and the degree of freedom of a cell used by a logical date being in its pre-stage, and a ratio to an average value of the delay time of all the logical gates, of the delay time of each logical gage known already as a result of delay calculation, the logical gate whose correction effect is considered to be high is recognized. In such a way, as for a delay time calculation required for changing the driving capacity of plural logical gates of one logic circuit, it will suffice that it is executed once.

Logic circuit diagram segmenting system

Abstract: PURPOSE:To prevent an extreme difference of circuit density between segmented diagram sheets and to obtain a diagram easy to see by taking not only circuit symbol shape areas but also connection relations, the number of symbols, etc., as the consideration object for diagram division. CONSTITUTION:A logic circuit segmenting mechanism 4 consists of a circuit symbol area calculating part 41 which reflects the connection density corresponding to the connection wiring state of each circuit symbol to calculate the shape area of the circuit symbol of a constituting element in accordance with logic circuit diagram information, a diagram storage value generating part 42 which generates diagram storage values which can be stored in the diagram for segmentation in consideration of not only calculated circuit symbol areas but also the number of circuit symbols, and a diagram segmenting processing part 43 which executes the diagram segmentation processing satisfying these diagram storage values. Thus, an extreme difference of circuit density between segmented circuit diagram sheets is prevented to obtain the circuit diagram easy to see.

Electronic circuit data editing device

Abstract: PURPOSE:To easily grasp a signal path by displaying an electronic circuit to be edited in both a circuit diagram and a block diagram. CONSTITUTION:Circuit diagram 2 contains constituent element data of the electric circuit and connection data among constituent elements. Block diagram data 3 contains an input and an output signal when the respective constituent elements are put in function blocks and information accompanying the input and output signals. A processor 7 edits or retrieves data in a data base according to a command inputted from a command input device 5 and displays the result on a display device 6. Consequently, even when a design engineer is not skilled, the engineer easily understands the signal path in the electronic circuit diagram according to the block diagram.

Preparation system for circuit data for logical simulation

Abstract: PURPOSE:To shorten a processing time when a circuit in a part of pages in a circuit diagram is altered by controlling preparing dates for respective pages in the circuit diagram and respective partial circuit data. CONSTITUTION:A circuit diagram preparing date control means 1 inputs the circuit diagram 21, adds preparation date information and outputs a circuit diagram with preparation date information 22. A circuit data selection means 2 which has received the diagram reads partial circuit data with preparation date information 25 from a partial circuit data preparation date control means 4 and compares date information. When partial circuit data does not exist, the page is selected and selection information 23 is outputted. A partial circuit data preparing means 3 receives selection information 23, and generates and outputs partial circuit data 24 only when a circuit diagram with preparation date information 22 is a new page. A link means of inter-partial circuit 5 receives partial circuit data with preparation date information 25, settles the reference relation of inter-partial circuit and outputs circuit data for logical simulation 26. Thus, the time required for the partial alteration processing of the circuit diagram can be shortened.

Test pattern generating system for logic circuit

Abstract: PURPOSE:To make a decision for an easiness of a test while proceeding a logic design along with a high speed generation of the test pattern by propagating to an outside output and setting an outside input at a macro element level. CONSTITUTION:A data bus part, in which macro element blocks defined beforehand as described at the system setting are connected with a path, is designed to correctly operate on the logic design. By a symbolic values assigning part 3, the macro element objective for the test generation is selected from the data bus part along the specification for a storage system design for circuit diagrams 1 of the logic design, and the symbolic values are assigned to this input. At the same time, a macro element library 12 is referenced and one capable to be the objective element among functions is selected, then the output values of the symbolic values are assigned to the output in accordance with the function. In a propagating and setting part 4, the propagation to the outside output and the setting of the outside input at the macro element level are performed for the above arrangement. Then, the test pattern is generated by means of substituting the materialized pattern into these symbolic values in a materialization processing part 5.

Sequence program checking system

Abstract: PURPOSE:To shorten the debugging time by securing such a constitution where an operator can be aware of a stack using mistake if occurs in one net of a program and also can easily correct this mistake in an interactive way. CONSTITUTION:A desired circuit diagram is shown on the display screen of a program producing device 1. While a programmable controller PC10 receives an external signal from an input circuit 12 and outputs it via an output circuit 13 after converting the signal level. In this case, a read stack instruction of a step 2 and an AND stack instruction of a step 3 are formed into a pair and show a contact (s). The AND stack instruction of a step 4 is excessive and deleted, and an assumptive ladder diagram converted from an approximate program is displayed. If the key input of an operator shows 'YES' when a message 'OK?' asking the correct or wrong state of the ladder diagram, both the approximate program and the ladder diagram are decided as the sequence equivalent to one net. While an error message is displayed for study if the key input of the operator shows 'NO'.

Device for forming parts list

Abstract: PURPOSE:To automatically form a parts list based upon parts names used for a circuit diagram and their relating information by providing the parts list forming device with a circuit diagram information storing means, a parts information storing means, a circuit diagram information reading means, a parts list forming means, a parts list display means, a parts list editing means, and a parts list output means. CONSTITUTION:The circuit diagram information reading means C reads out necessary circuit diagram information from the circuit diagram information storing means A and extracts the identification(ID) codes of respective parts used for the circuit and the parts list forming means D retrieves the parts names of respective parts and their relating information from the parts informa tion storing means B based upon the ID codes to form a parts list. The formed parts list is displayed on the parts list display means E, the displayed parts list is edited by the parts list editing means F by means of an external input and the edited result is printed out by the parts list output means G. Thus the parts list based upon the parts names of the parts used for the circuit and their relating information can be automatically formed.

Building blocks type electronic circuit experimental plate

Abstract: The utility model discloses a building blocks type electronic line experimental plate used for experimentally assembling an electronic circuit, composed of building blocks and a bottom plate. Magnet, clips, and holes are arranged on building blocks, the feet of electronic components inserting in the holes of one building block are mutually communicated. The bottom plate is made of permeability magnetic materials, building blocks are adsorbed on the bottom plate through magnetic force, and an experimental line is formed. The positions of the electronic components in the experimental line and the positions of the electronic components in a circuit diagram can be caused to be corresponding through selecting and combining different building blocks. The utility model can help to rapidly assemble the experimental line, having the advantages of convenience and simple use.

Circuit diagram input device

Abstract: PURPOSE:To easily check the position of modification and change in a circuit diagram by judging whether or not an inputted graphic element changes the graphic element of the displayed circuit diagram and displaying the inputted graphic element so that it can be distinguished from the displayed graphic element when the inputted graphic element changes the displayed graphic element CONSTITUTION:When an operator instructs the position of change, a number management means 9 registers a symbol number SymID=4 and a signal number SigID=2 which are to be deleted in a deleted number registration means 11 The number management 9 adds number SymID=6, 7 and a number SigID=5, 6 to the symbol and signal line which are to be added or modified an stores them in a storage device The number management means 9 supplies the required graphic element and its number to a number comparison means 7 in order The number comparison means 7 compares the symbol registered in a maximum number registration means 10 with the maximum number of the signal line each time it receives the graphic element and its number and when the supplied number is larger than the maximum number, judges the addition and the modification of the graphic element and notifies the display processing means 8 of it

Method for displaying simulation result

Abstract: PURPOSE:To make simulation results and circuit diagrams correspond to each other instantaneously and to obtain the results of all signal lines of a circuit line at a time by simulating pieces of information on respective parts of the circuit line by a computer and combining the results with the circuit diagrams. CONSTITUTION:Pieces of information from storage devices 1 and 2 stored with circuit diagram information and input information of simulation are inputted to the computer 3 to perform simulation. A storage device 4 for output information is stored with the simulation results of all the signal line of the circuit diagrams. Further, the circuit diagram information from the device 1 and the simulation result from the device 4 are combined by a display controller 5 to display the circuit diagram and simulation results on a graphic display 6 at a time.

Lsi design supporting system

Abstract: PURPOSE:To easily execute design work and to shorten a designing period by simultaneously displaying a formed state transition diagram, a formed state transition table and a formed circuit diagram on the same screen to execute the design work CONSTITUTION:A status transition diagram forming part 1 inputs transition relation between plural states corresponding to the specifications of an LSI to be designed and forms the state transition diagram The state transition table forming part 3 forms the state transition table for setting up a condition for transitting respective states in the state transition relation formed by the forming part 1 to the succeeding states An intra-state operation circuit forming part 5 forms an intra-state operation circuit diagram or its description indicating the operation of a circuit in respective states formed by the forming part 1 by a graphic input or a description input Data inputted respective input parts and an initial value setting part 7 are applied and stored to/in a data base 9 and inputted/outputted through a data I/O part 15 to be controlled by an input control part 11 and an output control part 13