Showing papers on "Clock generator published in 2022"

A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter

Abstract: With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a speed of 6.4Gb/s has recently been announced [1]. One of the most critical issues of high-performance DRAM is the supply-noise induced jitter (SIJ) generated by the clock distribution network (CDN) and the transmit and receive paths. Conventional CDN SIJ coping methods use supply voltage regulators and decoupling capacitors. Unfortunately, a supply regulator is not suitable for low-voltage mobile DRAM due to the required drop-out voltage headroom, while the decoupling capacitor cannot sufficiently filter low-frequency noise without requiring excessive area. In this paper, we propose an SIJ cancelation technique based on an adaptive filter (AF) using a least mean square (LMS) algorithm; it cancels jitter along the CDN and the transmit and receive paths, which include serializers and pre-drivers. The proposed technique includes a 2nd-order AF to maximize jitter cancellation in the clock path, which has a non-linear supply-to-jitter characteristic [2]. Implemented in 28nm CMOS, the proposed SIJ cancellation scheme reduces the RMS jitter of the RDQS_c clock from 27.33 to 4.20ps and improves the data eye opening from 22.34 to 99.12ps when operating at 6.4Gb/s with a $60\text{mV}_{\text{p-p}}$ 1 MHz supply noise.

A 280nW leakage-ratio-based CMOS temperature sensor with supply/clock sensitivity suppression

Abstract: This paper presents a low-cost digital temperature sensor for radio frequency identification (RFID). The proposed sensor utilizes the leakage channel current ratio of different transistors with exponential temperature dependence, which results in ultra-low-power consumption and compact size. Thanks to a dual-differential scheme, it can operate without any extra assistance from a voltage regulator or accurate clock generator. The sensor is fabricated in a standard 55nm CMOS process, and measurement results show that the proposed design achieves an inaccuracy of +0.8/-0.75°C between -20 and 80°C while occupying a silicon area of only 5700µm2. Beneficial from the low total capacitance, the power consumption is 280nW, and the conversion time is 37ms.

A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS

Abstract: Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm2 and consumes 7.7 mW from a 1.2 V supply.

Investigation of injection‐locked ring oscillators for process, voltage, and temperature‐aware low phase‐noise reference clock generation

Abstract: In this paper, injection‐locked coupled ring oscillators (ROs) are studied regarding their capabilities for process, voltage, and temperature (PVT) compensated reference clock generation. A PVT resilient RO is implemented by means of injection‐locked coupled ROs where the injection locking mechanism is realized by employing adjustable coupling factors. It is shown that the oscillation frequency can be highly compensated for temperature‐related variations through the coupling factors. In addition, it is possible to compensate the center oscillation frequency for process‐induced variations and supply voltage fluctuations. The proposed technique is fully open loop without any frequency tracking loop and can be easily adopted by other architectures of oscillators such as RC and LC counterparts. A 2.4 GHz reference clock generator is implemented in a 0.18 μm standard CMOS process. While the temperature coefficient (TC) of the free‐running ROs is about 640 ppm/°C, the coupled structure offers a TC of 80 ppm/°C. Furthermore, the phase‐noise of the coupled structure is about 4 dB lower compared with the free‐running ROs. The proposed RO consumes about 2.8 mW and occupies a silicon area of 0.09 mm2.

A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INL_pp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links

Abstract: The continuously growing need to move data keeps pushing demands on wireline transceiver speed and power consumption. Multiple I/O transceivers are integrated on a single chip, and the global clock distribution and local clock generation take a significant portion of the total power consumption (Fig. 17.6.1). The phase interpolator (PI) is a crucial block in a transceiver's local clock generator as it provides phase deskew and frequency shifting for the local clock. A local multi-phase clock generator (MPCG) generates the multi-phase input clocks for the PIs from the global differential clock. Conventional 4-phase-clock-interpolation PIs have poor linearity due to intrinsic constellation phase errors and linearity degradation caused by AM-to-PM conversion [1]. Eight-phase-clock-interpolation PIs improve the linearity but 8-phase clock generation requires a power-hungry and noisy ring oscillator [2]–[4]. The 8-phase clock generator also occupies a large area and its operating frequency is limited by the ring oscillator's oscillation frequency. Injection-locked PIs demonstrate great linearity and power efficiency, but their operating frequency is also limited by their core ring oscillator, which has a high number of stages [5].

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Abstract: We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.

A Novel Blind Zone Free, Low Power Phase Frequency Detector for Fast Locking of Charge Pump Phase Locked Loops

Abstract: AbstractPhase Frequency Detector (PFD) being one of the important block of the high frequency clock generator encounters two major problems in its design. One being the dead zone and other is blind zone. The presence of the dead zone leads to phase noise. Blind zone increases the lock time of the clock generator. This paper presents a novel edge detector based PFD. In the proposed PFD, zero blind zone is achieved by eliminating the reset pulse beyond the dead zone region. The proposed PFD is designed in UMC 0.18 \(\upmu \)m CMOS process. It consumes power of 648 \(\upmu \)W at an operating frequency of 1 GHz. It is observed that the proposed PFD locks 43\(\%\) faster than the conventional PFD.KeywordsPhase frequency detectorDead zoneBlind zoneReset pulseClock generator

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Abstract: Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

An Improved Measurement Matrix Generator for Compressed Sensing of ECG Signals

Abstract: Compressed sensing (CS) is being widely used to compress and reconstruct data for processing electrocardiogram (ECG) signals obtained through Wireless Body Area Networks. However, the conventional measurement matrix generator and compression computations for CS are in parallel, resulting in significant power consumption and a large area. This paper proposes a serial measurement matrix generator, which reduces the clock frequencies by using linear feedback shift registers and latches. A CS circuit for ECG signals processing based on the proposed measurement matrix generator is proposed and implemented in a SMIC 55 nm CMOS process. The experimental results show that the power consumption is only 1.690 μW at 1.2 V, and the chip area is 0.608 mm2, which has obvious advantages over the traditional parallel architecture. The reconstruction results show that the Percentage Root-mean-square Difference is 1.32%, which means that the design meets the basic clinical requirements.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Abstract: A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

Abstract: SUMMARY This paper proposes a reference-clock-less quick-start-up CDR that resumes from a stand-by state only with a 4-bit preamble utilizing a phase generator with an embedded Time-to-Digital Converter (TDC). The phase generator detects 1-UI time interval by using its internal TDC and works as a self-tunable digitally-controlled delay line. Once the phase gen- erator coarsely tunes the recovered clock period, then the residual time difference is finely tuned by a fine Digital-to-Time Converter (DTC). Since the tuning resolution of the fine DTC is matched by design with the time resolution of the TDC that is used as a phase detector, the fine tuning completes instantaneously. After the initial coarse and fine delay tuning, the feedback loop for frequency tracking is activated in order to improve Consecutive Identical Digits (CID) tolerance of the CDR. By applying the frequency tracking architecture, the proposed CDR achieves more than 100bits of CID tolerance. A prototype implemented in a 65nm bulk CMOS process operates at a 0.9 − 2.15Gbps continuous rate. It consumes 5.1 − 8.4mA in its active state and 42µA leakage current in its stand-by state from a 1.0V supply. key words: Clock-and-data recovery (CDR),

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Abstract: A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting

Abstract: Implantable biomedical devices (IMDs) capable of recording electrophysiological signals effectively facilitate medical treatment, but they also face strict volume requirements [1]–[6]. An effective way to miniaturize the IMDs is to eliminate the bulky components such as battery and crystal. Wireless power transfer (WPT) helps to remove the battery [1]–[5], while a bulky crystal is still required to provide a precise clock to ensure the performance of signal-acquisition and communication blocks (Fig. 1 left, top). To eliminate the crystal, prior work [1] uses an on-chip oscillator as the clock generator (Fig. 1 left, middle), while suffering from off-chip tuning and SNR degradation of analog front-end (AFE), ADC, and wireless transmission. Recently, clock recovering from power-harvesting tone has become a promising solution to further reduce the volume of battery-less systems (Fig. 1 left, bottom) [2]–[5]. However, it's difficult to deal with a trade-off: A high power-harvesting frequency leads to power-hungry clock-recovery circuits [4], while a low frequency requires a large-size antenna [5].

Microwave and Millimeter-wave Signal Generation using Injection Locked Technique

Abstract: High-speed clock generator is crucial for high-speed wireless/wire transmission, and it usually have some features of low phase noise, low jitter, low dc power consumption, and multi-phase outputs. In this paper, several advanced techniques are introduced for generating millimeter-wave and terahertz (THz) signal, such as multi-phase voltage-controlled oscillator (VCO), phase-locked loop (PLL), and sub-harmonically injection-locked methods. A few self-aligned techniques, including sub-harmonically injection-locked PLL (SILPLL) and frequency-locked loop (SILFLL), are presented to overcome the variations of the process, voltage, and temperature. Due to the self-aligned techniques, the SILPLL and SILFLL demonstrate excellent performance and good robustness. Furthermore, some advanced digital modulation signals, such as n-level quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM), are generated using the injection-locked methods for the modern 5G applications.

Design and Experimental Verification of a 2.1nW 0.018mm2 Slope ADC-Based Supply Voltage Monitor for Biofuel-Cell-Powered Supply-Sensing Systems in 180-nm CMOS

Abstract: This brief presents a slope analog-digital converter (ADC)-based supply voltage monitor (SVM) for biofuel-cell-powered supply-sensing systems operating in a supply voltage range of 0.18-0.35V. The proposed SVM is designed to utilize the output of energy harvester extracting power from biological reactions, realizing energy-autonomous sensor interfaces. A burst pulse generator uses a dynamic leakage suppression logic oscillator to generate a stable clock signal under the sub-threshold region for pulse counting. A slope-based voltage-to-time converter is employed to generate a pulse width proportional to the supply voltage with high linearity. The test chip of the proposed SVM is implemented in 180-nm CMOS technology with an active area of 0.018mm2. It consumes 2.1nW at 0.3V and achieves a conversion time of 117-673ms at 0.18-0.35V with a nonlinearity error of -5.5/+8.3mV, achieving an energy-efficient biosensing frontend.

Transition sensitive finite state machine

Abstract: This work proposed a transition sensitive finite state machine – TSFSM using the novel master-slave transition detector for low-power or high-speed applications. To solve the problems of hazard-free requirements and difficult synthesis of the exisiting locally clock finite state machine, TSFSM uses multi-bit XOR gate as the input burst detector and the local clock generator. The measured results show that the proposed implementation reduce the difficulty of its design and synthesis, and it also reduces the the area and power consumption by about 86% and 18.2%.

A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems

Abstract: The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the $2^{\mathrm{nd}}$ -order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8 $\mu \text{W}$ power.

A 12bit 39ps two-step Time-to-Digital Converter in 40nm CMOS

Abstract: This paper presents a two-step time-to-digital converter(TDC). Using a proposed self-biased phase-locked loop (PLL) based 64-phase multiphase clock generator as clock source of the phase interpolator, this TDC achieves a fine resolution of 39 ps and is not sensitive to process, voltage and temperature (PVT) variations. A dual-edge counter synchronization circuit is adopted to avoid the synchronization error between the coarse and fine stage of the TDC with low power and a small area. Designed in 40-nm CMOS, the proposed TDC achieves 39-ps resolution, 12-bit dynamic range with 1.1-ns conversion time, 0.2-mW power consumption, a core active area of 0.021 mm ² , as shown by the post-layout simulation results.

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

Abstract: This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

A low power clock generator 400–1800 MHz for ADPLL

Abstract: Abstract This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 to 50 MHz and generates an output signal ranging from 400 to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28 nm CMOS technology of TSMC. The power consumption and chip area of the block are 1.5 mW and 80 × 80 μm 2 correspondingly. A wide range of reference and output frequencies makes this block versatile in application.

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

Abstract: An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter =15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm ² and dissipates 3.56 mW at 1.6 GHz.

A Flexible 0.73–15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS

Abstract: This brief presents a compact and flexible 0.73–15.5GHz clock generator with only a single LC-VCO. A 50% duty cycle divide-by-1.5 divider (Div-1.5) is employed to reduce the required VCO tuning range in the wide-range clock generator to 50%, which becomes viable for a single LC-VCO to cover. The divider is realized by duty cycle interpolation (DI) between two digital divide-by-1.5 (DDiv-1.5) clocks with 33.3% duty cycle and 66.7% duty cycle, respectively. The clock generator was fabricated in 12nm CMOS process with an active area of 0.17 mm2. At a 13.28125GHz output, it achieves a 101fs integrated jitter and a −74.79dBc reference spur, while consuming 19.5mW. The measured worst deterministic jitter induced by the 50% duty cycle Div-1.5 is 550fs.

A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy

Abstract: The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.

Design of 0.6v 0.01mm2 Sub Sampling PLL Based On Dynamic Double Loops

Abstract: In order to solve the power consumption and cost problems caused by the massive nodes of the Internet of things chip, a new sub sampling PLL circuit is proposed in this paper. The circuit uses dynamic double loop technology to solve the harmonic locking problem of sub sampling, uses leakage compensation technology to reduce the capacitance area, and uses high matching sub sampling charge pump technology to reduce spurious. The test results show that when the output frequency is 1920MHz, the RMS jitter is less than 2.5ps, the power consumption is 0.8mW at 0.6V power supply voltage, and the area is only 105μm×95μm, which meets the clock requirements of the Internet of things chip system.

A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic

Abstract: A pad-less 5GHz RFID employing complementary pass-transistor adiabatic logic (CPAL) for low power operation is proposed. The power clock that drives the whole CP AL is improved to enable a smaller input RF power and higher speed data frequency by using a novel power clock shaper which pulls the power clock to GND when a falling edge is detected. As the loss in the RF rectifier decreases, the loss due to the leakage current of low- Vt transistors used in the CP AL circuit becomes dominant. A new CP AL circuit exploiting both the threshold voltage and W IL of the transistors is proposed to reduce this latter loss. Measurements using a test chip fabricated in a O.18µm CMOS process confirm that the proposed RFID can communicate at up to a distance of 11cm with 12dBm transmission power, as well as at a 100kbps data rate across a distance of 1cm.

Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators

Abstract: Digitally modulating the injection point in an injection-locked ring oscillator (ILRO) allows it to simultaneously serve as both a multiphase generator and phase interpolator (PI) or phase rotator. The resulting mostly-digital architecture is compact and promises low power in nanoscale CMOS, making it suitable for multi-Gbps dense I/O applications. This paper describes design considerations for such time-modulated ILROs, including the tradeoffs associated with determining their injection strength, modulation frequency, and pattern. These tradeoffs are illustrated in the design of a 14GHz PI in a 16nm FinFET technology. The proposed PI time-modulates between four different injection points within a ring oscillator to generate 96 fine phase settings (6.6 bits resolution). Based on post-extracted layout simulations, the overall PI consumes 24.1mW and occupies an area of 0.0033 $\mathrm{mm}^{2}$. The locking range is 12.4 - 14.3GHz in the typical process corner. The simulated jitter is 592fs-rms (including thermal noise and determinstic jitter) while the PI is rotating at a 200ppm frequency offset from 14GHz. A novel linearity calibration mechanism is used to correct for systematic and random phase imbalances.

A Wide-Input-Range Multi-phase Clock Generator Design for CMOS Image Sensors

Abstract: This paper proposes a novel phase-interpolator-based multi-phase clock generator, which could be applied in the single slope ADCs of the CMOS image systems. To widen the input range of the multi-phase clock generator, a fast reset method for the phase interpolator is proposed. Besides that an improvement using RC-based phase interpolator is also provided to deal with the deviation of the power supply voltage. The simulation results in CMOS 55nm process show that the duty cycle distortion of the proposed design is within ±3% when the input frequency ranges from 100MHz to 250MHz and the supply voltage ranges from 1V to 1. 4V.

Body-Heat Powered Biosensor Readout using Current-mode Relaxation Oscillators

Abstract: This paper presents a multi-sensor biochemical measurement IC that can be powered using thermoelectric energy harvesting, such as from body heat. A current-mode relaxation oscillator (RxO) readout approach is used to enable ultra-low-power sensor front-end circuits. A system-on-chip with integrated energy harvester was implemented in a 0.18µm CMOS process as a proof-of-concept. The fabricated IC is used to demonstrate pH and glucose measurement using off-chip sensors. An RxO using a V-to-I input converter demonstrating pH measurement consumes 2.2µW at maximum, where the RxO consumes 0.7µW. Measured linearity of the readout circuits demonstrate R ² >0.999. Glucose measurement is also demonstrated using an on-chip potentiostat circuit while powering from body heat using an thermoelectric generator on the skin surface.

Fully Analog Clock Signal Generator for SPICE based simulators

Abstract: Clock signals are vital in synchronous circuits because they synchronize various data signals coming from different parts of an integrated circuit, ensuring the correct functioning of the entire circuit. As simulation has become the main verification concept in circuit design, accurate clock signal generator models are mandatory in order to build high quality circuit models. This paper proposes a fully analog clock signal generator modeling method, which can be used in any SPICE based simulator. All synchronous circuit models currently implemented use a digital primitive based clock signal, which only works in the simulator it was designed for. The main advantage of our proposed method is the compatibility with all SPICE based simulators like PSpice Allegro, SIMetrix, TINA, LTSpice, which greatly widens the user's simulation alternatives.