Showing papers on "Clock synchronization published in 1996"

Optimal clock skew scheduling tolerant to process variations

Abstract: A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This methodology emphasizes the use of non-zero clock skew to reduce the system-wide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, difficulty in controlling the delays of the clock paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local data path while incorporating process dependent delay values of the clock signal paths. Graph-based algorithms are presented for determining the minimum clock period and for selecting a range of process tolerant clock skews for each local data path in the circuit, respectively. These algorithms have been demonstrated on the ISCAS-89 suite of circuits. Furthermore, examples of clock distribution networks with intentional clock skew are shown to tolerate worst case clock skew variations of up to 30% without causing circuit failure while increasing the system-wide maximum clock frequency by up to 20% over zero skew-based systems.

High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

Abstract: A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

System for controlling access to a function having clock synchronization

Abstract: The system includes a first card-like unit adapted to communicate with a second unit. The second unit grants conditional access to a function or service in accordance with an authentication operation. Both units are capable of running software for generating passwords by means of encryption of several dynamic variables as for example a time dependent variable and/or a variable representing the number of formulated authentication requests. The encryption may be performed using a dynamic key. In order to synchronize the values of the variables generated in concert but independently in the units, only some of the least significant digits of the variables are transferred from the card-like unit to the other unit, with the transfer being performed by adding the digits to the password. This synchronization information is combined with corresponding variables in the second unit and used to calculate therein a value which has to match with the password calculated in the second unit in order to gain access to the function or service.

Multipoint multimedia teleconference system with adaptive synchronization

Abstract: This paper discusses major issues involved in the design and implementation of a multipoint multimedia conference system, such as system architecture, conference management, session control, and intramedium and intermedia synchronization. In particular, emphasis is given to conference management and adaptive synchronization algorithms. The management of multiparticipants is based upon a distributed architecture for greater flexibility. The proposed synchronization algorithm is adaptive to network changes, eliminates the need for a global clock, and is immune to the clock frequency drift, while its realization is very simple and the involved overhead is minimal. The essence of the algorithm is partitioning the vicinity of the arrival epochs of multimedia objects into three regions and counting arrivals at each region. The function of the synchronizer is to shift the playback clock (PBC) according to the individual counter contents. The ideas proposed are implemented within a teleconference system on the Ethernet/FDDI using the TCP/UDP. Experimental results show that the proposed synchronization algorithm performs well in our network testbed environment.

Synchronization method and apparatus for isolated clock system

Abstract: A system for automatically synchronizing, isolated clocks is disclosed. In the preferred embodiment, the internal clock of an automated external defibrillator (AED) or an external defibrillator (ED) is integrated with a radio broadcast to receive standard time. The system may also include a mechanism for synchronizing the clock or a computer tracking the time of emergency calls such as 911. Further, the system enables synchronization between the AED or ED internal clock and the 911 clock such that response times can be accurately determined.

Plausible Clocks: Constant Size Logical Clocks for Distributed Systems

Abstract: In a Distributed System with N sites, the detection of causal relationships between events can only be done with vector clocks of size N. This gives rise to scalability and efficiency problems for accurate logical clocks. In this paper we propose a class of logical clocks called plausible clocks that can be implemented with a number of components not affected by the size of the system and yet they provide good ordering accuracy. We develop rules to combine plausible clocks to produce more accurate clocks. Several examples of plausible clocks and their combination are presented. Using a simulation model, we evaluate the performance of these clocks.

Emulation devices, systems and methods with distributed control of test interfaces in clock domains

Abstract: An emulation device (11) distributes common control information (8801) to each of a plurality of clock domains (1213, 1215, 1217) into which the emulation device is partitioned, and also provides the clock domains with individualized clock control (8905, 8907, 8913).

Optimal Clock Synchronization Under Different Delay Assumptions

Abstract: The problem of achieving optimal clock synchronization in a communication network with arbitrary topology and perfect clocks (that do not drift) is studied. Clock synchronization algorithms are presented for a large family of delay assumptions. Our algorithms are modular and consist of three major components. The first component holds for any type of delay assumptions; the second component holds for a large, natural family of local delay assumptions; the third component must be tailored for each specific delay assumption. Optimal clock synchronization algorithms are derived for several types of delay assumptions by appropriately tuning the third component. The delay assumptions include lower and upper delay bounds, no bounds at all, and bounds on the difference of the delay in opposite directions. In addition, our model handles systems where some processors are connected by broadcast networks in which every message arrives at all the processors at approximately the same time. A composition theorem allows combinations of different assumptions for different links or even for the same link; such mixtures are common in practice. Our results achieve the best possible precision in each execution. This notion of optimality is stronger than the more common notion of worst-case optimality. The new notion of optimality applies to systems where the worst-case behavior of any clock synchronization algorithm is inherently unbounded.

Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer

Abstract: A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.

A test of precision GPS clock synchronization

Abstract: This paper describes tests of precision GPS time transfer using geodetic-quality TurboRogue receivers. The GPS data are processed with the GIPSY-OASIS II software, which simultaneously estimates the GPS satellite orbits and clocks, receiver locations and clock offsets, as well as other parameters such as Earth orientation. This GPS solution technique, which emphasizes high accuracy GPS orbit determination and observable modeling, has been shown to enable sub-1 ns time transfer at global distance scales. GPS-based monitoring of clock performance has been carried out for several years through JPL's high precision GPS global network processing. The paper discusses measurements of variations in relative clock offsets down to a level of a few tens of picoseconds. GPS-based clock frequency measurements are also presented.

Rendering an audio-visual stream synchronized by a software clock in a personal computer

Abstract: A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically does not have a 27 MHz clock, but instead has a system clock, that runs at the frequency of the processor. Therefore, in order to play a DVD-based audio-visual work in a personal computer, a clock running at 27 MHz is needed. As such, a software clock running at 27 MHz is provided which facilitates the integration of a DVD CD-ROM into a personal computer. By using a software clock, synchronization of the audio-visual stream is facilitated and both cost and development time are reduced.

Jitter-tolerant clock routing in two-phase synchronous systems

Abstract: Due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. In the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. Appropriate skew or useful skew can serve as a safety margin to guard against clock jitter. In two-phase clocking, the nonoverlapping interval of two-phase clocks provides an additional degree of freedom to improve either the clock tree cost or jitter-tolerance. We construct a two-phase jitter-tolerant useful-skew tree (JT-UST) such that the susceptibility to clock jitter and the clock tree cost is minimized. Following the Deferred-Merge Embedding (DME) framework, we use a simulated annealing approach to explore the routing topologies and embeddings. Experimental results have shown 63% to 100% reduction of jitter-prone sink pairs over previous clock routing methods while having very comparable clock tree costs.

Clock distribution using coupled oscillators

Abstract: This paper presents a robust, low complexity clock distribution technique applicable to both printed circuit boards and integrated circuits. The technique exploits the natural tendency of certain oscillators to lock in frequency and nearly lock in phase when coupled together. Experimental and theoretical results are presented that indicate the technique has the potential to dramatically reduce clock skew in digital circuits. A clock distribution architecture using the technique is proposed.

Distributed source-destination synchronization using inband clock distribution

Abstract: This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property.

Procedure for radio synchronization of time shared systems

Abstract: The invention relates to a procedure for radio synchronization of time shared systems, especially DECT, including at least two in other respects independent systems with each at least one fixed control unit and respective portable units. According to the invention a first system establishes itself as master system, whereas the other systems start as slave systems and via radio listen in to the master system and synchronize themselves with this. The synchronization can be repeated periodically, with fixed time interval or a time interval which can be adjusted adaptively. The invention solves the problem of achieving synchronization between independent time shared wireless telecommunications systems in a way that they become locally synchronized with each other. The local synchronization can increase the capacity with up to 60%.

Characterization of timing signals and clocks

Abstract: The characteristics of timing signals at the output of autonomous and slave clocks are thoroughly investigated : first, a mathematical model of timing signals is introduced, then models for describing autonomous and slave clocks are presented whereby an analysis of their behaviour in a synchronization network is carried out. Further, two commonly used measurement configurations are described in order to identify the measurement set-ups more useful for telecommunication applications ; the most frequently used quantities for characterizing time and frequency stability are introduced and deeply investigated. Finally, the stability quantities behaviour both for autonomous and slave clocks is studied, with the aim at providing synchronization network designers with powerful tools for network planning and for assessing network performance.

Time-of-day clock synchronization in commincations networks

Abstract: A system for service control and operations for a telecommunications network. In particular, an architecture and method for a service control and operations element system. The system communicates with a plurality of interconnected telecommunications network elements via a switching and signaling subsystem. The system provides and controls the functions of the telecommunications network, including a method of measuring delay between the time a customer dials a phone number of a called party and the time the customer hears a ringback tone indicating that the called party was alerted to the call, a method of synchronizing clocks located at individual network elements with a centralized time source, and a method of time-of-day clock surveillance.

Real time clock suitable for a mobile telephone

Abstract: A real time clock is arranged to generate output signals indicative of time of day. An oscillating device (101) produces a first clocking signal which is adjusted in response to a calibration value to produce an output clocking signal. A processor (102) re-calculates the calibration value in response to external clocking signals received from a cellular base station for mobile telephones. The clock may be provided within a mobile telephone and the oscillating device may also be used to provide sleep clock signals allowing a high frequency system clock to be de-activated for periods while the telephone is in a stand-by condition.

Apparatus and method for switching asynchronous clock signals

Abstract: Within a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.

An optimal clock period selection method based on slack minimization criteria

Abstract: An important decision in synthesizing a hardware implementation from a behavioral description is selecting the clock period to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock period explicitly or require that the delays of the operators used in the design be specified in multiples of the clock period. An unfavorable choice of clock period could result in operations being idle for a large portion of the clock period and, consequently, affect the performance of the synthesized design. In this article, we demonstrate the effect of clock slack on the performance of designs and present an algorithm to find a slack-minimal clock period. We prove the optimality of our method and apply it to several examples to demonstrate its effectiveness in maximizing design performance.

Verification of an optimized fault-tolerant clock synchronization circuit

Abstract: In previous work, we explored the interaction between different formal hardware development techniques in the implementation of a fault-tolerant clock synchronization circuit. This case study presents a clever optimization of the earlier design and illustrates how we have extended our framework to support its incremental design refinement. The primary design tool represents circuits as systems of stream equations, where each stream corresponds to a signal within the circuit. These signals are annotated with invariants which can be established using proof by co-induction. These invariants are exploited to verify localized design refinements. This study lays groundwork for a more formal integration of disparate reasoning tools.

Apparatus for phase synchronizing clock signals in a fully redundant computer system

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed. For higher frequency operation, it is desirable to incorporate certain correction circuitry which minimizes phase offset at apparent phase lock which is an inherent characteristic of this type of phase locked loop.

Digital phase locked loop having adaptive bandwidth for pulse stuffing synchronized digital communication system

Abstract: A bandwidth-adaptive digital phase locked loop-based clock control arrangement controls the generation of a read-out clock used for retiming digital data signal interfaced with a synchronous data channel of a communication system, in which pulse-stuffing synchronization is employed to maintain clock synchronization of the digital data signal that is not bit-synchronous with a synchronous digital data channel over which the digital data signal is transported. The bandwidth-adaptive digital phase locked loop includes a loop filter to which the error signal is applied and a phase accumulator, coupled to the output of the loop filter and being operative to stepwise adjust the read-out clock signal. The loop filter has a first scaled path that includes a first, controllably stepped gain stage, and a second scaled path that includes a second, controllably stepped gain stage coupled to a frequency accumulator. The output of the frequency accumulator and the first stepped gain stage are summed and coupled to the phase accumulator. The gain of each of the first and second gain stages is incrementally adjusted in accordance with the magnitude of the error signal.

Data transmission method, system, and apparatus

Abstract: A data transmission method for transferring predetermined transmission data between a slave side and a master side to which the predetermined transmission data is transmitted and which are connected through a predetermined communications network, wherein the master side generates an independent synchronization clock signal and transmits synchronization data showing the frequency of the independent synchronization clock signal to the slave side, the slave side generates a slaved synchronization clock signal synchronized with the synchronization clock signal of the master side based on the synchronization data transmitted from the master side and generates the transmission data and transmits it to the master side in synchronization with the generated slaved synchronization clock signal, and the master side receives the transmission data transmitted from the slave side in synchronization with the independent synchronization clock signal.

Wave pipelines via look-up tables

Abstract: Look-up tables (LUTs) allow the delay of digital blocks with different types of gates or different logic depth to be equalized; thus, they could be a useful building block for the construction of wave pipelined circuits. In this paper, this alternative is explored by using a RAM-based FPGA. An experimental LUT-based wave pipeline 7-bit array multiplier has been constructed. The main results, for an intentionally skewed clock synchronization strategy, show that it is possible to obtain throughputs as high as 80 MHz with 8 waves running in a 13-LUT logic depth combinational circuit. The prototype presents a continuous range of frequency operation and exhibits an acceptable dependence with power supply variations. In terms of fast-prototyping, wave pipelining on FPGAs allows the designers to obtain a unique combination of high-throughput and minimum-latency.

Redundancy clock supply module for exchange system

Abstract: An exchange system comprising a plurality of redundant clock supply modules for receiving respective clock signals to maintain synchronization. Each redundant clock supply module includes a phase locked loop coupled to receive a network synchronizing reference signal, for generating a most significant clock of the exchange system synchronized to the network synchronizing reference signal; a clock generator for counting the most significant clock to generate a plurality of system clocks including a least significant clock and a first frame pulse; and a redundancy synchronizer for synchronizing the first frame pulse and a second frame pulse from a counterpart redundancy module to generate a redundancy synchronization signal for establishing synchronization between redundancy modules from the most significant clock to the least significant clock.

Fault-tolerant clock synchronization of large multicomputers via multistep interactive convergence

Abstract: We present a fault-tolerant algorithm that internally synchronizes clocks in multicomputer systems employing not completely connected networks (NCCNs). The algorithm is referred to as multistep interactive convergence, and is locally implemented in each node by a time sewer process (TSP). The algorithm proceeds in rounds, and bases its operation on a logical mapping of the system's TSPs into an m-dimensional array. A TSP executes m steps per round, each step including a call to an interactive convergence procedure. Clock readings in step i are gathered only from TSPs sharing a row along dimension i of the array, which reduces the number of messages by orders of magnitude over a conventional interactive convergence algorithm. The algorithm can be used in systems of arbitrary topology, and provides the added benefit of increased locality of communication in regular NCCNs. These advantages can be combined with a variety of message staggering mechanisms to maintain network contention at a minimum. We characterize the maximum clock skew maximum clock drift, maximum clock discontinuity, and number of messages produced by the algorithm, and show that it tolerates arbitrary faults. A comparison with other algorithms is provided.

Accelerating light clocks.

Abstract: The behavior of light clocks which undergo constant acceleration in flat space-time is considered. Time dilation, the Doppler shift, and clock synchronization are shown to be different from that of comoving unaccelerated clocks. These results are discussed in relation to the nature of time in accelerating systems. \textcopyright{} 1996 The American Physical Society.