Showing papers on "CMOS published in 1975"

Process Optimization of Radiation-Hardened CMOS Integrated Circuits

Abstract: The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed.

Self-aligned CMOS process for bulk silicon and insulating substrate device

Abstract: The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Capacitive voltage converter employing CMOS switches

Abstract: A CMOS circuit for approximately tripling battery voltage particularly adaptable for use with liquid crystal displays such as used in watches. P-wells of the CMOS circuit are coupled to active circuit nodes rather than to battery potentials. In the presently preferred embodiment a hybrid circuit with external capacitors is used to increase overall efficiency.

A CMOS implantable multielectrode auditory stimulator for the deaf

Abstract: Describes an implantable multielectrode neural stimulator developed for electrical stimulation of the auditory nerves with the aim of producing a sensation of sound in sensory deaf ears. Power and digitally coded amplitude and frequency data are transcutaneously transmitted to the implantable stimulator using an inductively coupled RF link and an ultrasonic link, respectively. A novel low-power low-component count CMOS charge-redistribution digital-to-analog (D/A) demultiplexer which produces a high resolution neuro-compatible charge output is described. An extended missing pulse code is developed which assures higher reliability and protection against excess and erroneous stimulations. An experimental 4-electrode system capable of stimulating up to a 5-kHz rate and consuming less than 10 mW of power is presented.

Simultaneous fabrication of CMOS transistors and bipolar devices

Abstract: A process for the simultaneous fabrication of CMOS transistors and bipolar devices on the same integrated circuit. The process follows the standard Silicon-Gate Deep Depletion technology up through gate definition. An additional mask step is included for definition of the base implant region. After the base diffusion the process again follows the standard approach resulting in a new structure which permits the fabrication of CMOS/SOS as well as a bipolar driver transistor.

Initial reset signal generator and low voltage detector

Abstract: A circuit for generating an initial reset signal for a custom design CMOS digital system and for providing a diagnostic low voltage detect signal when the power supply voltage drops below a predetermined level. The circuit is fabricated with CMOS technology in conjunction with two external resistors and a diode.

Design Optimization of Radiation-Hardened CMOS Integrated Circuits

Abstract: Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre-and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented.

High speed, high yield CMOS/SOS process

Abstract: A process for producing complementary metal-oxide-semiconductor/silicon-on-sapphire (CMOS/SOS) devices wherein undesirable effects of phosphorous on sapphire are avoided.

High speed divide-by-N circuit

Abstract: Disclosed is a high speed divide-by-N circuit which uses both a synchronous down-counter and a ripple down-counter to obtain the advantages of each. The advantage of a ripple counter is that count propagation time is not critical, and the advantage of a synchronous counter is that its state can be decoded quickly. Therefore, by combining the two different types of counters, keeping the gate delays per clock cycle as low as possible, using look-ahead techniques, and giving more time-consuming operations more time to occur, a high speed divide-by-N circuit is obtained. Said circuit is intended for integration on a single chip, particularly using CMOS design and processing.

Cmos power-on reset circuit

Abstract: For each IC and adapted circuit is accommodated on the same semiconductor substrate in order to define a specific initial state of the circuit groups, which generally consist of flip-flops. The use of the invention ensures a high constancy over a wide temperature range. Moreover, the spread in the tolerances of the circuit elements is substantially eliminated.

CMOS/SOS serial-parallel multiplier

Abstract: A 24-bit serial-parallel multiplier was integrated in CMOS/silicon-on-sapphire (SOS) technology on a 155 mil/spl times/170 mil chip. The operation of this multiplier is described, showing how the parallel loaded multiplier x combines with the serial loaded multiplicand, a, to form the serial product. An addend, b, can also be accommodated to produce ax+b. The design of the multiplier cells are based on functional majority logic adders and weak or trickle inverter master-slave latches. The chip operates at clock rates up to 18 MHz. Power dissipation at 10 MHz and V/SUB DD/ of 5 V is about 20 mW, and the energy consumption for multiplying two 16-bit numbers is about 64 nJ. Typical application areas are mentioned.

Exclusive or integrated logic circuits using complementary MOSFET technology

Abstract: An Exclusive OR circuit fabricated in CMOS technology is arranged to (1) minimize circuit switching elements and (2) generate inverted inputs within the circuit.

High speed memory cell

Abstract: An improved very high speed, static random access memory cell disclosed which is comprised of complementary metal oxide semiconductor field effect transistors which may be formed by silicon on sapphire techniques. To maximize the speed of the read operation while, at the same time, decreasing the overall cell area and consequently the cost, the cell is made highly non-symmetrical in design. As an example, selected ones of the semiconductor transistors may have reduced channel widths with respect to one another.

Radiation Hardened CMOS/SOS

Abstract: This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l?A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ?1V for the n-channel devices and ?2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.

CMOS drive system for liquid crystal display units

Abstract: The present disclosure is directed toward a system for driving a plurality of liquid crystal display units each having a common electrode, a plurality of segment electrodes and a liquid crystal composition interposed between the said electrodes. First, second and third voltage levels are determined with respect to a reference level in such a manner that a voltage difference between any possible combinations and the reference level except the combination of the third level and the reference level is not higher than a given threshold voltage which initiates enabling of the liquid crystal display units. When the liquid crystal display units are desired to be energized, signals of the reference level and the third level are alternatively applied to the common electrode, whereas the inversion thereof is applied to the segment electrodes. When the liquid crystal display units are desired to be disabled, a signal either of the first or second level is applied to at least one of said electrodes.

Complementary field effect transistor sense amplifier for one transistor per bit ram cell

Abstract: A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and one of the regenerative sense amplifiers for each of the rows, respectively. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected after redistribution of charge initially stored in the selected storage cell onto the sense-write conductor takes place. The sense voltage resulting from the charge redistributed on the opposite sense-write conductor is subsequently amplified by the sense amplifier, and provided in inverted and noninverted form on the two respective sense-write conductors. A CMOS transmission gate clocked by a first control signal and its logical complement balances the two sense-write conductors to precisely the same voltage. First and second clocked CMOS inverters are cross-coupled to form a label with its output nodes each coupled, respectively, to one of a pair of the sense-write conductors. The clocking of the latch circuit is performed by a second clock signal and its logical complement delayed somewhat from the first clock signal and its logical complement to effectively electrically isolate the pair of sense-write conductors during the balancing and sensing charge redistribution operations.

High speed, low power GaAs JFET integrated circuits

Abstract: Enhancement mode GaAs junction field-effect transistors have been explored in their application to digital and linear integrated circuit design. A 3-input NAND-gate and a one stage differential amplifier have been fabricated in integrated form on a 30 × 30 mil2chip. The electrical performance characteristics will be described. With a 4 micron gate length the monolithically integrated 3- input NAND-gate has a propagation delay time of 1 ns with a power dissipation of 2mW per gate, i.e., speed-power product of 2 pJ. The differential amplifier has a response time of 2 ns and flat frequency response to about 150 MHz. GaAs enhancement (normally-off) JFET integrated circuits offer better speed-power products than CMOS or Schottky-clamped bipolar ones at operating frequencies of 1 MHz and above. Optimized devices are capable of operating with a speed-power product of 1-2 pJ in the subnano-second switching range. The temperature range from 2°K to 650°K (or 380°C) for GaAs JFET's encompasses applications which are not possible with silicon devices GaAs JFET's and IC's are superior to Si devices and IC's in gamma and neutron environments and offer a potential design in radiation hardened integrated electronics.

CMOS differential amplifier circuit utilizing a CMOS current sinking transistor which tracks CMOS current sourcing transistors

Abstract: A control circuit comprising several CMOS transistors operating in cooperation with certain dimension relationships among the CMOS transistors to provide a first reference voltage to the gates of two current sourcing transistors and to provide a second reference voltage to the gate of a current sinking transistor, the two reference voltages being related, resulting in a desired tracking between the current sinking transistor and the two current sourcing transistors. The current sink transistor operates to current limit at a value which is approximately twice the current limiting value of either of the two current source transistors such that a substantial improvement in circuit performance is obtained.

CMOS structure and method utilizing retarded electric field for minimum latch-up

Abstract: CMOS device and method utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.

CMOS/SOS NAND Gate Sapphire Photocurrent Compensation

Abstract: Sapphire photocurrent is the dominant transient radiation response of CMOS/SOS circuits at high dose rates. Radiation-induced leakage current flowing through this photoresistive path accounts for most of the SOS transistor drain photocurrent observed experimentally. Sapphire photoconduction effects were modeled by incorporating radiation-induced linear photoconductance models in parallel with the channel conductances of the MOS transistors. This approach was used to predict the performance of CMOS/SOS NAND gates at high dose rates. NAND gates designed in accordance with optimum-W geometry rules for sapphire photocurrent compensation are predicted to have symmetrical dose-rate failure thresholds exceeding 1010 rads/sec. Radiation test results from experimental CMOS/SOS NAND gates have demonstrated dose-rate failure thresholds in the range from 2 × 1010 to 1011 rads/sec. The maximum achievable dose-rate failure threshold is approximately inversely proportional to fan-in. Consequently, more-radiation-resistant CMOS/SOS digital integrated circuits can be designed using CMOS/SOS NAND gates having limited fan-in. This design guide is practical, since it presents no serious problem with respect to either die size or circuit complexity.

Multiple output logic circuits

Abstract: A circuit provides multiple output switching functions. Diodes couple groups of switching elements to form a single complex circuit. The diodes provide isolation between each group so that the logical function of each group may be output, as well as the logical function provided by the coaction of the groups. The present invention is particularly useful in circuits using complementary switching elements, e.g., Complementary Metal Oxide Semiconductor (CMOS) and Silicon on Sapphire (SOS) integrated logic circuits.

Radiation testing of an 8-bit CMOS microprocessor

Abstract: An 8-bit CMOS microprocessor has been tested in an ionizing radiation environment. Quiescent current was monitored during the irradiation and clock frequency was a test parameter. Irradiated in a static condition, failure was observed at a total dose of 3 x 10$sup 4$ rads (Si). (auth)

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

Abstract: The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.

Switching and delay device - delivers two output voltages, depending on input signal being below or above threshold

Abstract: The first output voltage corresponding to the lower input signal blocks a signal path through an electronic switch, and the second unblocks it. When an input voltage drops below the threshold, the second output signal remains present until a capacitor in an RC circuit charged to a voltage above the threshold is at least partly discharged. The device is an integrated CMOS circuit with at least two gates. Input voltage is applied to the input of a first gate serving as the threshold switch. The first gate output is connected through a diode to the input of the second gate which, together with the RC circuit, forms a delay line. The RC circuit is between the second gate input and frame, and its output is connected to the electronic switch control input.

Design automation of electronics in Sweden

Abstract: This paper describes the status of design automation of electronics in three different companies and a university in Sweden.Design automation of MOS circuits at Asea-Hafo (Ingmar Hoglund)Asea-Hafo is a company, which produces high reliability semiconductor devices as integrated circuits, discrete transistors, diodes and opto electronic components.During 1974 CMOS Large scale integrated circuits has become the main product. Asea-Hafo concentrates on custom designed circuits in volumes between 10.000 and 50.000 circuits per design and year.In order to be successful in the competition between producers of MOS circuits Asea-Hafo among other things has to offer a short time of delivery of prototypes and serial produced circuits.

Complementary DMOS process for LSI

Abstract: Through the application of diffused MOS (DMOS) transistors to the design of complementary MOS circuits, a CMOS process that is simpler and denser than that presently used has been designed and demonstrated. Test circuits using 1 ohm. cm n-type

Reliability of Complementary MOS Integrated Circuits

Abstract: This paper describes the results of tests of the stability and reliability of complementary MOS (CMOS) integrated circuits (IC). Operating life-tests at 125°C indicated excellent stability of electrical characteristics of both n-channel and p-channel transistors. Over three million device-hours of accelerated operating life-tests indicated a calculated failure rate, at a 60-percent s-confidence level, of 0.08%/1000 hours at 125°C, which corresponds to 0.01%/1000 hours at 55°C or 0.003%/1000 hours at 25°C. Field-usage reliability data on three satellites in orbit indicate a total failure rate of 0.003%/1000 hours (over thirty-four million operating hours with no failures). The observed failure rates are compared with other available data on IC reliability, and it is concluded that the reliability of CMOS ICs is equal to that of p-channel MOS circuits or of bipolar digital circuits of equal complexity, when each type is prepared by a well-controlled process, and operated at the same temperature. The operating temperature of CMOS IC chips in electronic systems is, however, generally lower since logic functions are accomplished at lower dissipation per gate.

An MOS Modeling Hierarchy including Radiation Effects

Abstract: A hierarchy of modeling procedures has been developed for MOS transistors, circuit blocks, and integrated circuits which include the effects of total dose radiation and photocurrent response. The models were developed for use with the SCEPTRE circuit analysis program, but the techniques are suitable for other modern computer aided analysis programs. The modeling hierarchy permits the designer or analyst to select the level of modeling complexity consistent with circuit size, parametric information, and accuracy requirements. Improvements have been made in the implementation of important second order effects in the transistor MOS model, in the definition of MOS building block models, and in the development of composite terminal models for MOS integrated circuits.