Showing papers on "Control reconfiguration published in 1994"

DPGA-coupled microprocessors: commodity ICs for the early 21st Century

Abstract: During the past decade, the microprocessor has become a key commodity component for building all kinds of computational systems. During this time frame, large reconfigurable logic arrays have exploited the same advances in IC fabrication technology to emerge as viable system building blocks. Looking at both the technology prospects and application requirements, there is compelling evidence that microprocessors with integrated reconfigurable logic arrays will be a primary building block for future computing systems. In this paper, we look at the role such components can play in building high-performance and economical systems, as well as the ripe technological outlook. We note how the tight integration of reconfigurable logic into the processor can overcome some of the major limitations of contemporary attached reconfigurable computer engines. We specifically consider the use of integrated dynamically programmable gate array (DPGA) structures for the configurable logic, and examine the advantages that rapid reconfiguration provides in this application. >

Design of reconfigurable control systems using eigenstructure assignments

Abstract: An eigenstructure assignment-based method for reconfigurable control systems designs is developed. When the dynamics of the process being controlled are changed due to operating condition variations, or system component failures, the proposed method is capable of reconfiguring the control system so that the eigenvalues and eigenvectors of the original closed-loop system are recovered to a maximum extent. If full state feedback is permissible, the method guarantees the stability of the reconfigured system. If only system output is accessible, the method will recover the subsequent dominant eigenvalues and eigenvectors of the original system, and the stability of the reconfigured system will be maintained if a sufficient condition derived herein is satisfied. This condition unveils some intrinsic relationships between the degree of process variations, stability margins of the original system and the stability of the reconfigured system with output feedbacks. The steady-state performance of the original syst...

Multivariable adaptive algorithms for reconfigurable flight control

Abstract: The application of multivariable adaptive control techniques to flight control reconfiguration is considered. The paper first discusses three adaptation mechanisms for model reference control. It is shown that simple algorithms can be obtained if full state feedback is assumed. The respective advantages and disadvantages of the three algorithms are discussed in general terms, considering their complexity and the assumptions that they require. Next, the application of the adaptive algorithms to reconfigurable flight control is investigated. The objective is to design automatically a flight control law in the presence of actuator failures or surface damage. Design considerations for the adaptive algorithms are discussed in this context. Simulations obtained using a full nonlinear simulation of a twin-engine jet aircraft are included to illustrate the results. >

Branch-exchange sequences for reconfiguration of lightwave networks

Abstract: Some of today's telecommunications networks have the ability to superimpose some form of logical connectivity, or virtual topology, on top of the underlying physical infrastructure. According to the degree of independence between the logical connectivity and the physical topology, the network can dynamically adapt its virtual topology to track changing traffic conditions, and cope with failure of network equipment. This is particularly true for lightwave networks, where a logical connection diagram is achieved by assignment of transmitting and receiving wavelengths to the network stations that tap into, and communicate over, an infrastructure of fiber glass. Use of tunable transmitters and/or receivers allow the logical connectivity to be optimized to prevailing traffic conditions. With rearrangeability having thus emerged as a powerful network attribute, this paper discusses the reconfiguration phase which is the transition between the current logical connection diagram and a target diagram. We consider here an approach where the network reaches some target connectivity graph through a sequence of intermediate connection diagrams, so that two successive diagrams differ by a single branch-exchange operation. This is an attempt at logically reconfiguring the network in a way that is minimally disruptive to the traffic. We propose and compare three polynomial-time algorithms that search for "short" sequences of branch-exchange operations, so as to minimize the overall reconfiguration time. For networks made of up to 40 stations, theoretical and simulation results show that, when a randomly selected diagram is to be changed to another randomly chosen diagram, the average number of branch-exchange operations required grows linearly with the size of the network. >

Advanced equipment control system

Abstract: The present invention relates to a control solution development environment coupled to a runtime environment constructed to insulate the control solution designer as well as the developed control applications from both the hardware and the operating system. This insulation frees the designer from having to deal with a tangle of control and operating system commands and considerations. The runtime environment manages the details of the process system resource and task allocation to implement the control strategies. Since the runtime environment insulates the developed control applications from changes in operating systems and hardware, applications developed to run in this environment are both reusable and portable. The runtime environment is scaleable, fault-tolerant, allows dynamic reconfiguration of the system, integration of diverse sensors and actuators and enables distributed control strategies. The runtime environment is built on C++ software language, is hostable on a variety of industry-standard computer operating systems, and readily accommodates legacy and third-party software tools.

Density enhancement of a neural network using FPGAs and run-time reconfiguration

Abstract: Run-time reconfiguration is a way of more fully exploiting the flexbility of reconfigurable FPGAs. The run-time reconfiguration artificial neural network (RRANN) uses ran-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the back-propagation algorithm into three sequential executed stages and configures the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single Xilinx XC3090 can implement by 500%. Performance is effected by reconfiguration overhead, but this overhead becomes insignificant in large networks. This overhead is made even more insignificant with improved configuration methods. Run-time reconfiguration is a flexible realization of the time/space trade-off. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured. >

Supervisory control system for networked multimedia workstations that provides reconfiguration of workstations by remotely updating the operating system

Abstract: A supervisory control system for a networked multimedia computing system permits a teacher or network administrator to quickly and easily update system software on selected destination workstations with the system software currently residing on the master workstation. In one mode of operation, only basic system software is updated, while user-defined preferences are unchanged. In a second mode of operation, both the system software and all user-controlled settings are replaced, to permit the remote workstations to be configured in a desired manner.

Intelligent fault diagnosis and control reconfiguration

Abstract: This paper gives an overview of fault diagnosis and control reconfiguration for complex systems such as those required in the aerospace industry. The presentation starts with a brief review of fault accommodation followed by four specific examples, viewed from the perspective of a control engineer. These examples are: 1) real-time fault diagnosis; 2) fault accommodation and control reconfiguration for an autonomous unmanned underwater vehicle; 3) fault detection, isolation, and reconfiguration for aircraft control surfaces; and 4) fault diagnosis relating to autonomous control of a spacecraft. >

"RISC" industrial robotics: recent results and open problems

Abstract: At the intersection of robotics, computational geometry, and manufacturing engineering, we have identified collection of research problems with near-term industrial applications. The common thread is robot systems with reduced intricacy in sensing and control (RISC), such as light beam sensors and parallel-jaw grippers. We conjecture that such systems, coupled with appropriate algorithms, are capable of recognizing and orienting a broad class of industrial parts. When compared with general-purpose robots, the resulting systems could be: (1) lower in cost, (2) more reliable, and (3) easier to reconfigure. The proposed hardware bears a close resemblance to existing "hard" automation; what is new is the application of computational methods for robust design and control of these systems, and more extensive use of simple sensors. By focusing on a small vocabulary of simple hardware, planning become computationally tractable and we can in some cases make guarantees about the existence of solutions. We borrowed the RISC acronym from computer architecture to acknowledge a common theme: identifying a minimal set of hardware primitives and matching these primitives with highly efficient software. In this paper, we review recent algorithms for locating, feeding, inserting and fixturing industrial parts. We discuss related work and propose a set of open problems for future research. >

Closed-loop control of systems over a communication network with queues

Abstract: Due to remote sensor, actuator and processor locations, many systems need to implement closed loop control through a communication network. Thus, they face the problem of random delays being introduced by the network. These delays may deteriorate the system performance and may even cause instability. The problems get more complicated when the possibility of queue formation at the transmitting side is considered for closed loop data transmission. The authors propose a state prediction/control scheme to control this type of system. The scheme utilizes knowledge of the amount of data in a queue to enhance prediction. Two automotive examples are used to illustrate the performance of the proposed scheme.

Single-chip self-configurable parallel processor

Abstract: A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58). Internal reconfiguration requires no separate reconfiguration time at all, and external reconfiguration can be accomplished in less than 10 μs.

RRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs

Abstract: Field programmable gate arrays (FPGAs) are an excellent technology for implementing neural networking hardware. This paper presents the run-time reconfiguration artificial neural network (RRANN). RRANN is a hardware implementation of the backpropagation algorithm that is extremely scalable and makes efficient use of FPGA resources. One key feature is RRANN's ability to exploit parallelism in all stages of the backpropagation algorithm including the stage where errors are propagated backward through the network. This architecture has been designed and implemented on Xilinx XC3090 FPGAs, and its performance has been measured. >

Optimal and robust design of integrated control and diagnostic modules

Abstract: The problem of designing an integrated control and diagnostic module is considered. The four degree of freedom controller is recast into a general framework wherein results from optimal and robust control theory can be easily implemented. For the case of an /spl Hscr//sub 2/ objective, it is shown that the optimal control-diagnostic module involves constructing an optimal controller, closing the loop with this controller, and then designing an optimal diagnostic module for the closed loop. When uncertain plants are involved, this two-step method does not lead to reasonable diagnostics, and the control and diagnostic modules must be synthesized simultaneously. An example shows how this design can be accomplished with available methods.

Artificial Neural Network Implementation on a Fine-Grained FPGA

Abstract: This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA) The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are time multiplexed onto the logic array This allows a larger ANN to be implemented on a single FPGA at the expense of slower overall system operation

A new network reconfiguration technique for service restoration in distribution networks

Abstract: Whenever a fault occurs in a particular section of a distribution network and on isolation of the fault, some of the loads get disconnected and are left unsupplied. Service should be restored to these affected load points as quickly as possible through a network reconfiguration procedure. A new and efficient technique is presented in this paper for this purpose. Network reduction and determination of the interested trees of the reduced network by a specially developed algorithm for finding the required restorative procedures, are the main contributions of this paper. >

Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements

Abstract: In an approach recently proposed for the yield enhancement of programmable gate arrays (PGA's), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step, this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. We first formulate the reconfiguration aspect of this approach as a problem of shifting pebbles on a graph. We present efficient reconfiguration algorithms for this pebble shift problem. Using these algorithms as heuristics, we develop a yield enhancement system not only for PGA's, but also for programmable Wafer Scare Integrated (WSI) processor arrays. We evaluate the heuristic algorithms using the measures of routability and total wire length of the reconfigured placement of the circuit. Based on this evaluation, we establish proper reconfiguration strategies. >

Reconfigurable learning control in large space structures

Abstract: The design of control algorithms for large space structures, possessing nonlinear dynamics which are often time-varying and likely ill-modeled, presents great challenges for all current methodologies. These limitations have led to the pursuit of autonomous control systems. In the present paper, the author proposes the use of a hybrid connectionist system as a learning controller with reconfiguration capability. The ability of connectionist systems to approximate arbitrary continuous functions provides an efficient means of vibration suppression and trajectory maneuvering for flexible structures. A fault-diagnosis network is applied for health monitoring to provide the neural controller with various failure scenarios. Associative memory is incorporated into an adaptive architecture to compensate slowly varying as well as catastrophic changes of structural parameters by providing a continuous solution space of acceptable controller configurations, which is created a priori. This paper addresses the theoretical foundation of the architecture and demonstrates its applicability via specific examples. >

Planning for change: a reconfiguration language for distributed systems

Abstract: In order to help programmers achieve greater leverage of emerging reconfiguration mechanisms, we are studying notations for users to express reconfiguration plans. These plans direct how a running distributed application would be changed, based upon recognition of events from either the application itself or its environment. Our work to date in this area is embodied in a simple system called Clipper. Based upon C++, Clipper provides a way for programmers to express plans, that are then used to automatically generate the run time mechanisms needed to validly reflect the programmer's rules for change in the application. This paper presents a description of our language in its current form, along with requirements that led up to it. >

RRANN: the run-time reconfiguration artificial neural network

Abstract: Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable field programmable gate arrays (FPGAs). The run-time reconfiguration artificial neural network (RRANN) uses runtime reconfiguration to increase the hardware density of FPGAs. This is done by dividing the backpropagation algorithm into three sequentially executed stages and configuring the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single FPGA can implement by 500%. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured. >

Control algorithms for fault-tolerant robots

Abstract: When a fault-tolerant robot fails, its fault responsive system detects and identifies the failure. During the recovery process, reconfiguration of the system isolates the fault, and a new system model and a suitable controller attempt to completely compensate for the faulty condition without interrupting the robot's operation. In this paper, the authors address the recovery process for fault-tolerant serial robots when they experience actuator failure. For this purpose, the authors consider three controllers based on PID feedback, sliding control, and parameter adaptation methods. It is shown that the sliding control implemented with a boundary layer reduces the system errors efficiently when the errors are large, and the controller behaves like an ordinary PID feedback as the errors get smaller. Additionally, when failures cause uncertainty in system parameters, inclusion of parameter identification capability in the controller design is suggested. Although the work is valid for a general robot, simulation results are presented on a four-axis robot. >

Defect tolerant SRAM based FPGAs

Abstract: We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present. The scheme is applicable to any SRAM based FPGA and keeps full software compatability with existing design tools. >

A diagnostic network for massively parallel processing systems

Abstract: Massively parallel processing systems consist of a large number of processing nodes to provide high performance primarily for data-intensive applications. In a system of such dimensions high availability cannot be achieved without relying on redundancy and reconfiguration. An important aspect of highly available design is rapid diagnosis and graceful degradation in the event of a failure. This paper presents a diagnostic network for locating faults in massively parallel processing systems comprised of identical processing nodes. >

Guarded repair of dependable systems

Abstract: Imperfect coverage and nonnegligible reconfiguration delay are known to have a deleterious effect on the dependability and the performance of a multiprocessor system. In particular, increasing the number of processor elements does not always increase dependability. An obvious reason for this is that the total failure rate increases, generally, linearly with the number of components in the system. It is also a well-known fact that the performance gain due to parallelism mostly turns out to be sublinear with the number of processors. It is therefore important to optimize the degree of parallelism in system design. A related issue is that by deferring repair, it is sometimes possible to improve system dependability. In this case decisions have to be made dynamically as to when to repair and when not to repair. Most of the current research deals with static optimization of the number of processors. No systematic approach for dynamic control of dependable systems has been proposed so far. Dynamic, i.e. transient, decision of whether or not to repair is the optimization problem considered in this paper. We propose extended Markov reward models (EMRM) to capture such questions. EMRM are a marriage between performability modeling techniques and Markov decision theory. A numerical solution procedure is developed to provide optimal solution trajectories for this problem. EMRM are a general framework for the dynamic optimization of reconfigurable, dependable systems. The optimization is applied on the basis of several performance and dependability measures. In particular, we explore availability, capacity-oriented availability, performance-oriented unavailability, and performability measures. Furthermore, off-line and on-line repair strategies are compared. We show that guarded repair can improve system performance and dependability significantly. The control strategies and reward functions differ a lot in each case. Each scenario turns out to be interest in its own right. A time-dependent optimality of dependable, parallel configurations can be determined from our results.

Decentralized control of machines with the use of inductive transmission of power and signal

Abstract: Industrial manufacturing systems, such as machine tools and robots, require frequent reconfiguration Conventional cable based systems introduce degradation of connector contacts at each reconfiguration adding noise and reducing reliability Furthermore, cable based systems are inadequate for some common tasks, such as endless rotational motion This paper describes a new approach to industrial manufacturing systems using inductive transmission of power and high speed data The proposed technology for motion controls makes possible, flexible systems built on contactless modular units High efficiency power transfer and high speed data transfer capabilities have been successfully incorporated in three modular units-rotatable, separable, and linear units-called the Integrated Power and Data Transmitting Units (IPDTU) This unique system structure allows: reliable operation in adverse environments polluted with oil and dirt; frequent reconfiguration without degradation of contacts; more freedom in configuring the machine; and decentralized controls >

The performability manager

Abstract: The authors describe the performability manager, a distributed system component that contributes to a more effective and efficient use of system components and prevents quality of service (QoS) degradation. The performability manager dynamically reconfigures distributed systems whenever needed, to recover from failures and to permit the system to evolve over time and include new functionality. Large systems require dynamic reconfiguration to support dynamic change without shutting down the complete system. A distributed system monitor is needed to verify QoS. Monitoring a distributed system is difficult because of synchronization problems and minor differences in clock speeds. The authors describe the functionality and the operation of the performability manager (both informally and formally). Throughout the paper they illustrate the approach by an example distributed application: an ANSAware-based number translation service (NTS), from the intelligent networks (IN) area. >

Application specific processor architecture comprising pre-designed reconfigurable application elements interconnected via a bus with high-level statements controlling configuration and data routing

Abstract: The architecture and design method of an application specific processor ("ASP") is disclosed. The ASP is designed by integrating selected pre-designed application elements contained in a library. These selected application elements can communicate with each other via a bus. Post-synthesis tailoring of the synthesized ASP is accomplished by using an instruction program which sequences the invocation of each application element and provides reconfiguration and data input/output routing commands thereto. A power management design is incorporated within the application elements allowing the majority of the application elements to be turned on only during periods of invocation.