Showing papers on "Degree of parallelism published in 1981"

A communicating sequential process language and implementation

Abstract: The design of a communicating sequential process language is presented, featuring a parallel command, communication by message passing and the use of the guarded command as a means of introducing and controlling non-determinism. The language described here incorporates a number of new proposals regarding communications between sequential processes. The principal proposal is that messages are to be selected for reception by a receiving process solely on the basis of their type and arrival order within type; in particular, the identity of the sending process does not influence message reception. This results in a greater degree of parallelism and non-determinism, which is useful to both the programmer and the language implementor. Also a hierarchichal composition regime is proposed, which gives communications significance to the organization of subprocess hierarchies; this promotes an independence of specification of program components through information hiding properties. The language implementation is described, and several aspects are of particular interest: the design of a process scheduler in a non-deterministic situation leads to some interesting optimizations, as does the design of a message handler in the case where the communicating processes can access the same memory. Finally, example programs are given to illustrate some of the novel features of the language.

VLSI perspective of real-time hidden-surface elimination

Abstract: VLSI (very large-scale integration) technology provides and demands new ways of solving large-scale computational problems. A pipelined version of a real-time hidden surface elimination algorithm is proposed. The approach is tuned to the requirements of the VLSI technology: it is simple and regular, employs only local communication, and attains a high degree of parallelism. The feasibility of the technique is demonstrated for a computer graphics system where objects are defined in terms of planar triangular surface elements. A case is made in terms of early 1980s technology. The use of VLSI will make high-power graphics available to the small user as well as the traditional flight simulator customer. This is achieved by enabling system expansion to take place through the addition of more identical chips. Consequently system cost is linear with respect to the number of chips used, a number determined by the maximum number of rendering elements needed by the specific user application.

System oriented extensions to dataflow

Abstract: This dissertation addresses the extension of traditional dataflow modeling to include specifications to allow additional control over the execution environment. Three major studies are presented: (1) a comparative analysis of several proposed and existing dataflow models and architectures, (2) the specification of several extensions for generalizing traditional abstract dataflow models and providing the opportunity to express greater parallelism, and (3) the design and implementation of an evolutionary test bed for realizing the simulation of dataflow programs and systems. The extensions to the abstract dataflow model include: (1) a generalized firing rule to eliminate unnecessary synchronization introduced by requiring all inputs to be available before enabling nodal execution, (2) a mechanism for obtaining a higher degree of parallelism through replication of nodes, (3) a concept of generalized termination detection and signaling useful in supporting replication and streaming, and (4) the description of methods for supporting shared data objects and interprocess communications in a multiple process dataflow environment. The dataflow simulator, DFSS, was developed in support of this work and is a highly generalized facility for realizing the execution, debugging, and metering of dataflow programs.

DEFASM: a microprogram meta-assembler with semantic capability

Abstract: A microprogram assembler which can assemble code for any user-defined target machine, i.e. a metamicroassembler, is described. Its most important feature is a definition phase where a description of the actual microinstruction set is given once for all, using a simple definition language. Within this definition phase, simple semantic controls may be introduced to facilitate the detection of errors that microprogram writers tend to make when the target machine has a high degree of parallelism, i.e. when long microinstructions are used.

Heuristic optimization of microcontrollers

Abstract: We describe a heuristic method for constructing and optimizing a microprogrammed controller. The input is a control flow graph. The output is a specification of a microcontroller including layout of the microword and the contents of the microprogram memory. The optimization performed uses a clustering technique to decide which control signals should appear together in a single microword. As more signals are clustered together# more parallelism becomes possible. We initially assame no parallelism and correspondingly small signal clusters. This corresponds to a highly encoded(vertical) microcontroller. Using a scheme of "attraction weights" we then merge clusters together until the desired degree of parallelism, or the maximum width of control word is reached, whichever comes first. Ihe controller in which all clusters are merged corresponds to a horizontal microcontroller. We describe a canonical control structure, the clustering algorithm, the computer implementation, and some results.

Models to Describe Those Features of Cellular Computer Nets Which Are Relevant to the Operating System

Abstract: Models to Describe Those Features of Cellular Computer Nets Which Are Relevant to the Operating System. A cellular computer net seems adequate to execute user problems which have a high computational complexity and which exhibit a high degree of parallelism. The cellular net is seen as a subsystem of a hierarchical modular computer system. A structure-model and a state-model will be presented. The flrst describes the topological features of a cellular net which are static, the second mainly models dynamic faults and the status of allocation. Finally three alternatives for realizing cellular nets are discussed.

Parallel evaluation of correlation time-of-flight experiments

Abstract: We examine three correlation time-of-flight (CTOF) techniques that are most promising for neutron, molecular and ion beam spectroscopy. The techniques use pseudorandom binary sequences as input modulations. In particular we study the degree of parallelism in the identification procedures which yield univariable or multivariable response functions. The time-complexity of the algorithms involved is discussed as a function of the number of parallel processors available. The indirect character of CTOF techniques and the experiment control and assessment make real-time evaluation essential. Therefore the design of parallel processor structures capable of performing parallel algorithms in real-time is presented for the three CTOF methods.

Efficient real-time interpolation for D/A conversion

Abstract: Four interpolation schemes using small sample sets are considered for real-time D/A conversion applications. Evaluation, for sampling rates near the Nyquist limit, is based on a mean-square-error criterion. Hardware suitability is considered with respect to the number of operations per interpolation and degree of parallelism.