Showing papers on "Delta-sigma modulation published in 2023"

A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique

Abstract: This paper presents a resolution-reconfigurable discrete-time dynamic zoom analog-to-digital converter (ADC) with a 20-kHz bandwidth. It employs a coarse 6-bit successive approximation register (SAR) ADC that dynamically updates the references for the post-stage single-bit second-order delta-sigma modulator to obtain a higher resolution with lower power. The sampling rate of the proposed ADC can be configured to be 1.6, 3.2, 6.4 and 10-MS/s such that four resolution modes, including 12, 14, 16 and 18-bit, can be provided accordingly. Note that pole locations of the noise transfer function (NTF) vary with different OSR’s, and noise-shaping effect, together with the power efficiency, can be degraded. To solve this issue, the pole-optimization technique is proposed in this paper. In this way can the pole locations be reconfigured according to the specific OSR. Additionally, the bandwidths of the operational amplifiers are also modulated in different oversampling ratio (OSR) scenarios to further improve the energy efficiency. Fabricated in a 0.18- $\mu \text{m}$ CMOS process, the prototype occupies 1.01 mm2. On condition of an OSR of 250, the proposed ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 102.8 dB, while dissipating 1.3 mW.

A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS

Abstract: Precise current measurements underpin emerging applications such as photoplethysmography (PPG), electrochemical sensing, and fast-scan cyclic voltammetry (FSCV) [1–6], where the signal is a low-swing current that rides on a large, slow-varying baseline. Therefore, readout systems need a dynamic-range (DR) > 120dB, bandwidth (BW) >1 kHz, noise floor $< 1\text{pA}_{\text{rms}}/\surd \text{Hz}$ , and power <1 mW (Fig. 32.3.1 left). To widen DR, prior front-ends employ a prediction DAC [1], threshold-filter-based feedback-loop [2], and a Reset-Then-Open (RTO) DAC [3]. However, they widen the DR by sacrificing BW or power (Fig. 32.3.1 right). For instance, [1] employing a prediction DAC requires a power-hungry digital backend, while [2] with a threshold-filter-based feedback-loop is BW-limited (~20Hz). In contrast, [3] achieves wide-DR and BW, but consumes> 1 mW power. This paper presents a continuous-tirne $\Delta\Sigma$ current-to-digital converter (IDC) that achieves wide-DR and BW at $\mu\mathrm{W}$ power. To this end, it employs: 1) a 2nd-order $\text{CT}-\Delta\Sigma$ structure employing a highly linear pseudo-differential VCO quantizer, 2) an energy-efficient tri-level resistive DAC, and 3) a digital-intensive truncation-noise-shaped baseline-servo (TNS-BS) loop that extends the DR at low power and area.

Optimized MASH-SR Divider Controller for Fractional-<i>N</i> Frequency Synthesizers

Abstract: The divider controller in a conventional phase-locked loop fractional- $N$ frequency synthesizer modulates the instantaneous division ratio of the feedback divider. The divider controller is typically a digital circuit that performs quantization of its input signal. Multi-stage noise shaping digital delta-sigma modulators (MASH DDSMs) and successive requantizer (SRs) are two representative divider controller architectures offering lower complexity and better spur performance, respectively. The MASH-SR, as a hybrid of these two classes of divider controllers, can achieve both lower hardware cost than the SR and better performance against spurs than a MASH DDSM. In this work, we present an optimized MASH-SR hybrid and compare the design with its conventional MASH DDSM and SR counterparts.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

Abstract: A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit (IC) has been implemented for a bridge sensor. The read-out IC has a capacitively coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta–sigma ( $\Delta \Sigma)$ analog-to-digital converter (ADC) with an output data rate (ODR) of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The $\Delta \Sigma $ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoIs) filter. Implemented in a 0.13- $\mu \text{m}$ CMOS process, the read-out circuit achieves an input impedance of 22 $\text{M}\Omega $ at a data rate of 800 SPS, a sensor offset compensation range of ±350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of $1.72 \mu \text{V}_{\text {RMS}}$ at a gain of 128. It draws an average current of $106.3 \mu \text{A}$ from a 3-V supply and $1.3 \mu \text{A}$ from a 1.5-V supply.

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC

Abstract: This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming $10~\mu \text{W}$ of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.

Optimization of Slew Mitigation Capacitor in Passive Charge Compensation based Delta-Sigma Modulator

Abstract: In this paper we propose a scheme of optimizing the size of charge compensation (CC) capacitor in a delta-sigma modulator (DSM) using a passive charge compensation (PCC) based switched capacitor integrator (SCI). The slewing behavior of a PCC based SCI is analyzed in both integration phase (IP) and sampling phase (SP) to optimize the size of CC capacitor. The effectiveness of the proposed scheme is demonstrated by implementing a 2-1 cascaded DSM using PCC based SCI with optimized value of CC capacitor in 0.18-μm CMOS technology. The DSM operates at a frequency of 5-MHz and achieves a peak SNDR of 103.1-dB in the audio bandwidth of 20-kHz. The power consumption of DSM is 220-μW at a supply voltage of 0.85-V and it consumes 1.3 mm of area. Post-layout simulations show an improvement of 10.8-dB in the SNDR of DSM by using the optimized value of CC capacitor in PCC based SCI.

10.6 A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer

Abstract: Many $\text{IoT}$ applications demand ADCs with high resolution, medium bandwidth, and good energy efficiency. Lately, the incremental ADC is drawing ^r ising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion $\Delta\Sigma$ modulator, the zoom architecture achieves high energy efficiency and high resolution simultaneously [1–2]. However, the conventional zoom ADC can only convert quasi-static signals, since the two stages operate sequentially, and its $\Delta\Sigma$ conversion operates at a slow speed. The dynami ^c zoom architecture performs coarse and fine conversions concurrently, thus being able to convert varying inputs [3–4]. Yet, limited by the low quantization level of the fine $\Delta\Sigma \mathrm{M}$ , it requires a large OSR for the targeted resolution (e.g., 282.25 in [3] and 87.5 in [4]), which restricts the input bandwidth to several tens of $\text{kHz}$ , Moreover, its loop filter relies on charge transfer, where each conversion requires dedicated sampling for its residue generation. As a result, in addition to the limited input bandwidth, the largely repeated sampling operation incurs extra power and design challenge for input drivers. The CT zoom architecture features easy driving while still requiring a large conversion cycle of 8192 in [5]. Recently, the emerging noise-shaping (NS) SAR ADC employs the efficient SAR for the multi-bit quantizer, significantly reducing conversion cycles [6–7]. However, without the initial coarse quantization, high loop filter orders are usually required for hig h -resolution applications, raising significant hardware cost and design complexity.

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

Abstract: Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology.

Delay Error Shaping in $\Delta\Sigma$ Modulators Using Time-Interleaved High Resolution Quantizers

Abstract: As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

Abstract: This brief presents a single-loop third-order discrete-time delta-sigma ( $ {\Delta } {\Sigma }$ ) analog-to-digital converter (ADC). The proposed $ {\Delta } {\Sigma }$ ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.

A 3.68 aF_rms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS

Abstract: This article describes a fourth-order continuous-time (CT) bandpass (BP)- $\Delta \Sigma $ capacitance-to-digital converter (CDC) for full-CMOS sensors having ultrahigh-resolution and high-energy efficiency. To improve the resolution of $\Delta \Sigma $ CDC, a CT instead of a discrete-time (DT) operation is employed to overcome a thermal noise limitation. Moreover, a BP- $\Delta \Sigma $ modulator is used to save power consumption compared to lowpass (LP) or highpass (HP)- $\Delta \Sigma $ Ms. In addition, a charge-domain digital-to-analog converter (DAC) at the input stage of the $\Delta \Sigma M$ is proposed for low thermal noise and simplicity. An inverter-based amplifier is used for low power consumption and gain boosting circuit is added to increase dc gain of the amplifier. Implemented in $0.18~\mu \text{m}$ CMOS, the proposed CDC achieves a ultrahigh-resolution of 3.68 aFrms and the highest Schreier figure-of-merit (FoMS) of 183 dB which is 3.3 dB improvement over the recent state-of-the-art CDCs.

Low Power Discrete Time Delta Sigma Modulator for Remote Healthcare Devices

Abstract: This chapter presents an ultra-low-power discrete time (DT) second order feedforward (FF) delta sigma (ΔΣ) modulator using an optimizer bulk-driven operational transconductance amplifier (OTA). The designed modulator was suitable for non-implantable biomedical devices in the 2.4GHz ISM band for IEEE 802.15.1/Bluetooth standard. The used OTA was optimized using the PSO algorithm for designing a 2nd order FF ΔΣ modulator. Using TSMC 0.18µm CMOS process, the designed OTA achieves a 40.1dB of DC gain and a 380MHz of GBW while consuming only 10µW under ±0.5V. The modulator has been implemented with an OSR of 50, a signal bandwidth of 0.5MHz, and a sampling frequency of 50MHz with an input signal magnitude of -6.37dBFS. It attains a peak SNR of 55.63dB and a resolution of 8.94bits with a total power consumption of 20µW under ±0.5V supply voltage.

Research of Continuous Delta-Sigma Analog-to-Digital Converter for Bio-Electricity Signal Acquisition

Abstract: In this paper, a continuous delta-sigma analog-to-digital converter with a low power, single-ring, third-order mixed integrator for bio-electricity signal acquisition is proposed. For the trade-off between low power consumption and high resolution, the Active-RC integrator is used in the first-order of the third-order feedforward modulator and the Gm-C integrator with improved linearity is adopted for the second and third order integrators. Because of the infinite resistance provided by the Gm-C integrator, the first-order integrator can replace the traditional second-order operational transconductance amplifier (OTA) with a single-stage OTA operating in the weak invert region to achieve low power consumption and ensure the output swing of the first-order integrator. The structure of cascade-of-integrators with feedforward (CIFF) can scale the output voltage values of three integrators and reduce the requirement of linearity of the Gm-C integrator, to reduce the design difficulty of the Gm-C integrator. In addition, the linearity of the second and third-order Gm-C integrator is improved by using the auxiliary difference pair OTA with source-level negative feedback. Therefore, the matching between the circuit structure and the model coefficients is improved significantly.

A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces

Abstract: Incremental analog-to-digital converters (IADCs), by adding a simultaneous reset in analog modulators and digital filters, are Nyquist-rate ADCs which use noise-shaping to convert a finite number of analog samples into a single digital word. They retain most advantages of the delta sigma ( $\Delta \Sigma )$ ADCs, and are much easier to be multiplexed with shorter latency and simpler digital filters. Integrated sensor fusion system-on-chips (SoCs) require a high-accuracy low-latency analog-to-digital converter (ADC) to interface a wide input range signal and multiplex among multiple sensor channels. To fulfill these demands at the same time, a multistage multistep incremental ADC is proposed. A third-order multistage IADC, implemented by cascading a second-order IADC (IADC2) and a first-order IADC (IADC1), performs the coarse quantization in the first step. When the coarse quantization is finished, the residue is also accumulated at the last integrator’s output and is ready for fine quantization. The circuit is reused and reconfigured as a second IADC in the second step. Prototyped in 180 nm technology and power supplied at 1.8 V, the proposed work can achieve 20 kHz signal bandwidth with 358.4 $\mu $ W power dissipation. The measured performance of the prototype is 91 dB dynamic range (DR), 89.1 dB signal-to-noise-and-distortion (SNDR), and 107.5 dB spurious-free DR (SFDR). The measured SNDR/DR achieves Schreier figure-of-merit (FoM) of 166.6/168.5 dB.

TID Radiation Effects on a 0.6 μm Sigma Delta ADC Radiation-Hardened-by-Design using ELTs

Abstract: This paper presents the Total Ionizing Dose radi-ation results for a radiation tolerant Sigma-Delta Analogto-Digital Converters for aerospace applications, in 0.6 $\boldsymbol{\mu} \mathbf{m}$ Silicon-On-Insulator Technology. The ADC topology circuit was de-signed from continuous-time sigma-delta modulator (CT-SDM) for High-Speed A/D Conversion. The digital filter is based on the Cascaded Integrator Comb what is a lowpass linear phase-line finite impulse response filters, well suited for anti-aliasing filtering. In order to mitigate the effects of ionizing radiation some features are approached, such as the adoption of the Radiation hardened by design Enclosed-LayoutTransistor-Based technique that increases radiation tolerance. Another technique used was SOl, which enables transistor isolation, thereby reducing parasitic capacitance. These two techniques are alternatives for Low-Power Low-Voltage circuits. During X-ray ionizing radiation testing, it was found that from a TID dose of order above 50 krad (Si) and 10KeV effective energy. The results obtained from the tests showed that the Integrated Circuit (IC) of the sigma delta ADC behaved as expected and can be used in environments for space applications.

Design of Interface Circuits and Lightweight PUF for TMR Sensors

Abstract: The micromagnetometers with high-resolution digital output are widely used in military and civilian fields. We proposed a novel high-precision interface circuit with an optimized chopper technique and switched-capacitor (SC) modulator for tunneling magnetoresistance (TMR) sensors. This work also proposes a novel method to create a lightweight physically unclonable function (PUF) by using existing TMR devices. The sigma-delta modulator converts the sensor signal into a robust digital output and maintains the signal-to-noise ratio (SNR) of the front-end circuit. We also take advantage of inherent variations of TMR sensors to generate PUF responses that are similarly unique and unclonable. The interface circuit is fabricated by a 0.35- $\mu \text{m}$ CMOS process from the Shanghai Huahong foundry. The active area of ASIC is only about $3\times2.7$ mm. The interface circuit can achieve an SFDR of 120 dB and an SNR of 98 dB at a sampling frequency of 200 kHz. The TMR magnetometers were tested in an environment of three-layer magnetic shielding. Our proposed PUF is also tested in terms of uniqueness and reliability.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

Abstract: This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

Design of Low Power High Speed 2nd Order Discrete Time Sigma-Delta Modulator Using Charge Shared Double Tail Dynamic Comparator

Abstract: In this paper, we study a switch capacitive second-order passive-active sigma-delta modulator with twin benefits of improved speed and lower power dissipation. The comparator block has been on prime focus to improve power and speed. Two design variants of integrators are utilized for improvement. As the filter is simply switch capacitive integrator, there will be high attenuation with lower power dissipation. The second stage integrator is followed by unity gain buffer which does compensation of gain errors and phase errors with respect to ideal integrator transfer function. A 2nd order discrete time sigma-delta modulator will yield exemplary results with using large oversampling ratio. This circuit contains double tail dynamic comparator based on charge sharing scheme to reduce power dissipation and improving speed for the modulator. For circuit level verification, the circuit is simulated using Cadence Virtuoso using GPDK 90 nm CMOS technology. The measurements depicts power dissipation of 1.44 µW, peak Signal to noise ratio & signal to noise and distortion ratio of 84.67 dB and 82.95 Db, respectively, dynamic range is 91.02 dB & ENOB is 13.48 bits using 1 V supply for a 500 Hz sinusoidal signal.

Improved Delta-Sigma Modulator for Direct Switch Control of a DC-DC Converter

Abstract: Digital Delta-Sigma modulators can be an interesting alternative to Pulse Width Modulation for generating switching signals of a power converter. Their noise-shaping behavior results in low output distortion for output frequencies well below the modulation frequency. To directly generate the switch control signals of a traditional DC-DC converter, a first-order modulator with a two-level quantizer is preferred as they are inherently stable for the entire output range. However, the noise attenuation of a first-order modulator is limited to 20dB per decade for frequencies below the modulation frequency. Additionally, they suffer from limit cycles due to the low modulator order and 2-level quantizer resolution. To overcome this problem, a fast feedback loop is proposed that acts on disturbances introduced by the quantizer and compensates low frequency noise. As a result, an improved Delta-Sigma modulator is obtained that remains stable for almost the entire output range but also provides improved noise attenuation like that of a second-order modulator. Moreover, the output noise signature is whitened resulting in less power being present at the limit cycle frequencies.

Dose dependence of the spectral characteristics of sigma-delta analog-to-digital converters

Abstract: This paper presents the results of the study of sigma-delta analog-to-digital converters` main spectral parameters` dependence on the total ionizing dose (TID). Within the framework of this study the main parameters of analog-to-digital converters (ADC) (dynamic, static and electrical) were controlled. The main dynamic characteristics of sigma-delta ADC are signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), signal-to-noise and distortion ratio (SINAD) and total harmonic distortion (THD). Those have been determined from the spectrum of digitized sine signal using the fast Fourier transform (FFT). Static parameters (integrated nonlinearity (INL), offset and gain errors) were determined using a straight line that linearizes the transfer function, according to the method which is described in the IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters. National Instruments modular measuring equipment was used for testing ADC`s parameters. Comparative data on the dose dependence of static and dynamic parameters of two sigma-delta ADC and one sigma-delta modulator are obtained. Based on the results, it was concluded that the most sensitive parameters of sigma-delta ADC to TID are its dynamic parameters. Therefore, when assessing the sigma-delta ADC`s radiation hardness, the spectral characteristics of absorbed dose should be kept under control.

Complex incremental ΣΔ ADC

Abstract: This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

Beam Shaping for Massive MIMO Systems With One-Bit Spatial $\Sigma -\Delta$ ADCs

Abstract: One-bit quantization opens up opportunities for massive MIMO implementation using cheap and power-efficient radio-frequency front-ends, but unfortunately brings severe amplitude distortion. The spatial $\Sigma -\Delta$ structure is one important manner that can recover the amplitude information from one-bit quantized signals. In this paper, we demonstrate that the upper bound of the spatial degree of quantization noise reduction (DQNR) is 3 for the considered spatial $\Sigma -\Delta$ structure. However, the upper bound is hard to be achieved via the zero forcing (ZF) or the maximum ratio combination (MRC) schemes, and the achieved spatial DQNR is even not greater than 1 in the worst case. Thus the distortion suppression is inefficient. To address this issue, we propose a random beam shaping (RBS) scheme and prove it can achieve the spatial DQNR of 3. Through the random beam shaping, the beams are smeared into the whole beamspace. Meanwhile, the random beam shaping results in the power leakage of the beams and it may limit the distortion suppression when considering the additive noise. To reduce the power leakage, we further propose an accurate beam shaping (ABS) scheme, in which the vector for the beam shaping is optimized through the alternative minimization algorithm and the beams are concentrated around the region with low power of quantization noise. The simulation results illustrate that the proposed beam shaping schemes can more efficiently exploit the large-scale antenna array to recover the amplitude information.

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time-Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

Abstract: A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the $\Delta $ - $\Sigma $ and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF). This article presents a calibration-free two-channel TI-NS-SAR with an aggressive second-order NTF for high resolution. Based on a one-time error feedback (FB) at midway, we propose a second-order error-feedforward (FF) to enhance the noise-shaping (NS) effect further meanwhile avoiding the excessive NTF peaking and dynamic range (DR) loss. A dynamic residue amplifier shared between two channels lowers the offset, which reduces the redundant bit to only one bit, thus improving the efficiency of SAR conversion. Fabricated in a 28 nm CMOS with 1 V supply, the prototype achieves 73.2 dB-signal-to-noise-and-distortion-ratio (SNDR) over 30 MHz-BW when operating at 330 MHz. It consumes 3.07 mW and exhibits a Schreier FoM (FoMs) of 173.1 dB.

A Calibration Scheme for a Sigma-Delta Modulator Using Passive Integrators

Abstract: This paper describes a calibration method for a 2-1 MASH $\Sigma\triangle$M using passive integrators. Due to process variations the RC product can vary, causing a degradation in circuit performance. Therefore, a circuit measuring the RC time constant and converting it into a digital coefficient, was designed. This coefficient is used to calibrate the reference voltage of the $\Sigma\triangle$M to decrease the variability of the feedback signal and to calibrate the digital cancellation logic (DCL), improving quantization noise cancellation. Electrical transient noise simulations results of the $\Sigma\triangle$M with calibration prove validity of the presented method showing performance improvement in worst corners.