Showing papers on "Depletion region published in 1977"

Emission probability of hot electrons from silicon into silicon dioxide

Abstract: An experimental method is described for directly measuring the probability of electron emission from the silicon substrate into the SiO2 layer after the electron has fallen through a certain potential drop in traversing the depletion layer and reached the Si‐SiO2 interface. The method is based on optically induced hot‐electron injection in polysilicon‐SiO2‐silicon field‐effect‐transistor structures of reentrant geometry. The emission probability was studied as a function of substrate doping profile, substrate voltage, gate voltage, and lattice temperature. It was found that the hot electrons could be emitted by tunneling as well as by surmounting the Schottky‐lowered barrier. Over‐the‐barrier emission dominates at large substrate voltages, where the emission probability is high, and tunnel emission becomes appreciable and may even dominate at small substrate voltages where the emission probability is low. A simple model was developed based on the assumption that only those hot electrons lucky enough to escape collision with optical phonons were emitted. Using this model, we found that the expression P=A exp(−d/λ) described very well the dependence of the emission probability on doping profile, substrate voltage, and gate voltage. Here A=2.9 is a constant, λ is the optical‐phonon‐electron collision mean free path, d is the distance from the Si‐SiO2 interface where the potential energy is equal to the ’’corrected’’ barrier of (3.1 eV−βEOX1/2 −αEOX2/3ox), βEOX1/2 is the Schottky lowering of the barrier, and αEOX2/3 is a ’’barrier‐lowering’’ term introduced to account for the probability of tunneling. The temperature dependence of the collision mean free path was found to follow the theoretical relationship λ=λo tanh(ER/2kbT), with λo=108 A and ER=0.63 eV. This model is useful for evaluating potential hot‐electron‐related instability problems in IGFET and similar structures.

Investigation of the double exponential in the current—Voltage characteristics of silicon solar cells

Abstract: The influence of minority carrier recombination in the depletion region of silicon solar cells on their current-voltage characteristics has been investigated. Starting with cells which exhibited a clear double-exponential dark characteristic of the form j = j_{01}[\exp (\frac{qV}{(A_{1}kT})-1] + j_{02}[\exp (\frac{qV}{A_{2}kT})-1] + \frac{V}{R_{sh}} with values A_{1} \approx 1 , A_{2} \approx 2 , and R sh large, depletion region recombination was studied by subjecting the cells to proton irradiation of 20- to 80-MeV energy at fluences of 1012to 1015cm-2, so as to introduce further recombination centers in the depletion region. A significant change of j 01 resulted rather than the expected change in j 02 which would be caused by the introduction of deeplying levels. It could be shown that this effect, included inthe Sah, Noyce, Shockley formulation of diode current resulting from recombination in the depletion region, Was caused by the introduction of shallow levels in the depletion region by the proton irradiation. The analysis required an accurate measurement of the I-V Characteristics over a range of temperatures and an evaluation of them with a least squares Curve fitting computer program in order to separate the effects. As a result of this study it is found that the saturation current j 01 is not necessarily attributable Only to diffusion current from outside the depletion region and that solely its temperature dependence can clarify its origin.

Junction termination extension (JTE), A new technique for increasing avalanche breakdown voltage and controlling surface electric fields in P-N junctions

Abstract: Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions using an ion implanted junction extension for precise control of the depletion region charge in the junction termination. Theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages better than 95% of the ideal and at lower leakage current than the corresponding unimplanted devices. For example, diodes with a normal breakdown voltage of 1050 volts with a .5ma leakage current become 1400 volt (1450 ideal) devices with a 5µa leakage current. Applications of the technique are feasible in MOS technology, as would be expected, but are even more attractive in power devices in which the dramatically reduced surface fields are just as important as the extremely high breakdown voltages since it means more flexibility in passivation techniques, two of which we have used to date. Our results have also shown that the implant can be at a variety of temperatures with a good degree of success, extra process flexibility being the goal of these tests.

Theoretical analysis of the quantum photoelectric yield in schottky diodes

Abstract: A detailed analytical calculation of the photoelectric quantum yield in Schottky diodes is presented. The transport of carriers in the surface space charge region is treated explicitly, taking account of photogeneration, diffusion and drift in the non-uniform electric field. Boundary conditions at the interface are expressed in terms of surface recombination velocity and emission velocity of excess carriers into the metal. It is shown that the metal-semiconductor interface strongly affects the collection efficiency of short wavelength generated electron-hole pairs. This effect basically originates in the emission flux of majority carriers into the metal. Current, charge carriers distributions and quantum yields are computed using the data of AuCdTe Schottky barriers.

(GaAl)As/GaAs heterojunction phototransistors with high current gain

Abstract: n‐Ga1−xAlxAs/p‐GaAs/n‐GaAs heterojunction transistors with high Al concentrations have been fabricated by the conventional liquid‐phase epitaxial method. Electrical measurements showed that the transistors have a common emitter current gain of up to 1600. The current gain varies with the emitter injection level because of the defect‐current component, which is the recombination current in the depletion region. It has been made clear, however, that the effect of the defect current was reduced in transistors grown at low temperature (∼750 °C). The variation of the electron diffusion length Ln with the device operating temperature has been calculated by using the current gain at each temperature. Furthermore, the phototransistor characteristics have been widely investigated.

Subband Structures of N-Channel Inversion Layers on III–V Compounds –A Possibility of the Gate Controlled Gunn Effect–

Abstract: Multi-subband structures of n-channel inversion layers on the surface of p-type III–V compounds are calculated by a variational method. Nonparabolicity is taken into account in the bulk dispersion relation of the \(\varGamma\)-valley. When the surface electron density is low, electrons occupy only the subbands in the \(\varGamma\)-valley, while when it exceeds certain critical value, most electrons occupy the ground subband in the second minimum valleys. From this behavior, the working condition of the Gunn effect in the system can be changed by applying the gate voltage in the MOS structure. The critical surface electron density depends on the charge density in the depletion layer and the surface orientation, but in case of GaAs, it is about 7×10 12 cm -2 for typical operating conditions.

Characterization of silicon-on-sapphire IGFET transistors

Abstract: Under dynamic operation conditions, the potential of the floating substrate in a silicon-on-sapphire (SOS) device is primarily controlled by the capacitive coupling of the substrate to other device terminals. However, a key parameter that plays a major role in defining that potential during switching is the avalanche multiplication current produced by the channel current carriers in the surface space charge region adjacent to the drain. A closed form expression is derived for the avalanche current, enabling the development of a nonlinear equivalent circuit model of the device. Comparison of measurements with device terminal characteristics, as well as the switching behavior of the device, shows good agreement.

Experimental studies of switching in metal semi-insulating n-p+ silicon devices

Abstract: The switching properties of silicon structures comprising a p + - n junction and a metal electrode separated from the n -section of the p + - n junction by a semi-insulating (leaky) layer are presented. Two basic types of structure were studied: devices with relatively light doped n -sections, and those with relatively heavily doped sections. The switching voltage of the first group was found to be proportional to the product of the doping density, N d and the square of the width of the n -section, and to be only very weakly temperature-dependent. The capacitance-voltage relationship of the device in the high-impedance mode was found to be of the form C −1 ∞ V 1 2 , and these measurements established that switching occurred just as the depletion region of the n -section under the gate electrode reached through to the p + - n junction. It was thus established that these devices were operating in the punch-through mode. In the second group of devices, the doping density of the n -section was increased by diffusing an n -well into the section. The switching properties were found to be quite different from the punch-through devices. The switching voltage was found to be independent of the width of the n -section and proportional to N d − 3 4 . Capacitance measurements also showed that the depletion region in the n -section under the oxide at switching, varied with the doping concentration, and was substantially less than the width of the n -layer. It was thus concluded that switching in these devices was of the avalanche-mode type.

Semiconductor memory devices

Abstract: A semiconductor memory (storage) device is provided using layered semiconductor structures which produce spatially separate electron and hole wells. The state of the device depends upon whether or not charge carriers (electrons and holes) are confined in these wells. Thus, the device has a first state exhibiting one conductance or capacitance when the wells do not have charge carriers in them, and a second state (different conductance or capacitance) when charge carriers are confined in the potential wells. The lifetime of the state in which carriers are confined in the wells depends upon the amount of time required for electron-hole recombination and is expected to be very long since the electrons and holes are spatially separated. A preferred embodiment utilizes a layered heterostructure formed in the space charge region of a p-n junction. Electrons and holes are generated in the potential wells using either electrical injection or incident light, while reading is accomplished by measuring conductance or capacitance. Erasure of the device state is achieved by a reverse electrical bias which removes the electrons and holes from confinement in the potential wells. Confinement of electrons and holes in three dimensions is also achieved.

Origin of n≃2 injection current in AlxGa1−xAs heterojunctions

Abstract: We show that the n≃2 current in AlxGa1−xAs heterojunctions is due to surface recombination. The rate of recombination at etched surfaces is evaluated in two photoluminescence experiments. Both of these experiments provide evidence that the rate of surface recombination is proportional to exp(eV/2kT) and has the correct magnitude to account for the measured I‐V curves. The n≃2 behavior is shown to be a necessary consequence of maintaining equality between surface and depletion layer charge.

Field effect transistor with reduced series resistance

Abstract: A field effect transistor having an additional highly doped source region contiguous to the source region and protruding into the channel having a shape approximately conforming to the shape of the depletion layer and almost contiguous with the depletion layer in a desired operative state, thereby reducing the series resistance from the source to the pinch-off point without increasing the capacitance between the source and the gate. The improvement is particularly effective for devices of a high power, high speed and high frequency use and is compatible with the integrated circuit techniques.

Transition region behavior in abrupt, forward-biased pn-junctions

Abstract: The transition region for abrupt p-n junctions, symmetric and asymmetric, is analyzed in terms of carrier densities at the neutral bulk-space charge region boundaries and the location of these boundaries with respect to the metallurgical junction. The non-equilibrium semiconductor problem is simplified by defining an effective intrinsic carrier concentration and an effective Fermi energy. The relation between the split in the quasi-Fermi levels and applied junction voltage is obtained. Also, density relationships are derived in terms of externally applied junction voltages. A low, high and very high injection formulation results. The transition region width is determined by solving Poisson's equation for a double region problem approximately. MOS concepts such as inversion and depletion are shown to apply to the forward biased junction.

Semiconductor controlled luminescent device

Abstract: A p type semiconductor gate layer is buried in an N type semiconductor cathode layer to encircle a channel through which the forward current of a luminescent PN junction passes. A reverse voltage is applied to the gate layer to spread a depletion layer in the channel to control the forward current and therefore the emission of light. The gate layer may be disposed on that surface of the cathode layer remote from the luminescent PN junction with a groove disposed the other surface of the cathode layer to narrow the channel.

Dependency of the highest harmonic oscillation frequency on junction diameter of IMPATT diodes

Abstract: The effect of series resistance and junction capacitance on the high-frequency limit of IMPATT diode operation is studied with a Read-type small-signal theory, and is confirmed experimentally. Oscillation frequencies from 30 to 400 GHz have been measured with Si p+-n-n+abrupt junction diodes with a depletion layer width of 0.2 µm. The highest oscillation frequency increases as the junction diameter is decreased, owing to reduced junction capacitance and increased bias-current density. The highest oscillation frequency observed is 423 GHz, which is obtained in the fifth harmonic mode with a diode of 16-µm junction diameter. Fundamental oscillation frequency is found to depend strongly on dc bias-current density, and to be close to the avalanche frequency of the small-signal theory.

A simple approach for accurately modeling the threshold voltage of short-channel mosts

Abstract: We present a theory which models short-channel effects in MOS transistors (MOST) Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (15 μm) to very large (100 μm) effective channel lengths The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (ie ion-implantation has not been used to adjust the threshold) Our approach can be applied directly to the modeling of the short-channel drain to source current This application of the theory will be presented in a later paper

Non-equilibrium response of MOS devices to a linear voltage ramp—I. Bulk discrete traps

Abstract: A study is presented of MOS devices containing discrete bulk traps, subjected to a triangular voltage waveform, such that the rate of change of voltage is sufficiently high to take the device into the non-equilibrium mode of operation. Consequently, the dynamics of the system response are related to the parameters of the traps involved in the generation and recombination processes occurring within the device. The technique is in contrast with Kuhn's method in which the device, and hence the various generation and recombination processes, are always in quasi-equilibrium. Analytical parametric equations relating the current, and hence the small-signal capacitance and the gate voltage to the width of the depletion region, are obtained. From these equations current and small-signal capacitance vs gate voltage plots are obtained as a function of sweep rate and temperature, for both forward and reverse voltage sweeps. These plots are rich in structure, and physical discussion relating to the salient features of these plots is presented. Suggestions are made of how various device parameters such as generation rate and life-time, trap density, and capture cross-section, can be extracted from the theory.

Channel depletion boundary modulation magnetic field sensor

Abstract: A high sensitivity, low noise, broad bandwidth channel conduction field sensor device is described. The conductive channel is configured to create an exceptionally narrow, undepleted conduction channel of approximately filamentary form. The filamentary conductive channel so formed is provided with a source at one end of the channel and two or more laterally spaced drains at the other end thereof. Electric or magnetic fields may be utilized to deflect a stream of charge carriers traversing the conductive channel from the source toward the drains utilizing the depletion width modulation effect of the fields upon the boundaries defining the conductive channel portion. Modulation of the depletion zone width and depth along the channel sides effectively moves the stream of carriers and the conductive channel area to overlap one drain more than another. This develops a differential drain current balance which can be utilized to provide an output signal. Width and length criteria for defining a filamentary channel structure are described for the ultimate desired configuration and size which are to be obtained. As noted, operation of the device is based upon modulation of the width and depth of the depletion zone boundaries defining the conductive channel. An increased signal output is obtained by reducing the width of the channel to eliminate excess carriers normally found in wide channel devices and, further, by making the depletion zones as large a portion of the total channel width as can be obtained.

Interdiffusion and Schottky‐barrier‐height variations in Au–W(Ti)/n‐GaAs contacts

Abstract: Au–W(Ti)/n‐GaAs diodes were constructed for the purpose of examining the thermal stability of the metal–GaAs interface and the integrity of the W(Ti) diffusion barrier. The evaluation procedure consisted of using measurements of the Schottky barrier height and other electrical parameters as a function of annealing temperatures. Barrier heights, Vb(Io), determined by measurement of the zero voltage current intercept, Io, were found to increase with annealing temperatures up to 600°C. Values determined by the measurement of forward current activation energies were in agreement with Vb(Io) up to 500°C. Above 500°C, however, this method was not applicable, due to the onset of excess forward current at low voltages. This current was accompanied by evidence of gold interdiffusion, compensation, and high electric field strength in the depletion layer. Direct identification of the excess current source, however, was not accomplished.

A mathematical study of space-charge layer capacitance for an abrupt p-n semiconductor junction

Abstract: Simple approximation equations are presented for the space-charge layer capacitance of an abrupt p-n semiconductor junction. By direct comparison with exact capacitance calculations, this approximation method is shown to yield a maximum error of about 3.5% throughout a wide range of impurity atom density and reverse biasing voltage. In addition, calculations are presented to show the magnitude of error associated with several approximation equations presently available in the technical literature.

Schottky Injection Currents in Insulators: The Effect of Space Charge on the Time Dependence

Abstract: When a particle current is injected into an insulator, and the charge is trapped in the insulator, the field at the injecting electrode decays with time t. Consequently, both the particle current and the total current density j also decay. If the trapping is complete, the time dependence is hyperbolic, i.e. j ? (t + ?)-1, where ? is a time constant. We show that this holds both when the traps are distributed in space, and also when the potential maximum of the Richardson-Schottky barrier lies within this space charge region. Therefore it is not possible to discriminate between the effect of spatially distributed traps and of an idealized thin sheet of traps. We suspect that this also holds even when the trapping is incomplete.

On the establishment of an inversion layer in p- and n-type silicon substrates under conditions of high oxide fields

Abstract: It has been observed that an inversion layer cannot form in a p‐type silicon substrate when the Fowler‐Nordheim tunneling current into the oxide exceeds the minority generation current in the depletion layer. On the other hand, for n‐type substrates, the formation of the inversion layer is unaffected by the oxide current.

Epitaxial deposition process for producing an electrostatic induction type thyristor

Abstract: A process of manufacturing a static induction thyristor comprising providing a semiconductor substrate of the first conductivity type which defines a first semiconductor layer and forming a second semiconductor layer thereon of a second conductivity type. The first and second semiconductor layers have relative impurity concentrations effective for forming therebetween charge depletion regions when no electrical signal is applied to the second semiconductor layer and which prevent injection of charge carriers through the second semiconductor layer when the thyristor is in a blocking state, and such that electrically forward biasing the second semiconductor layer effectuates a sufficient reduction of the depletion regions that a sufficient quantity of charge carriers may be injected through the second semiconductor layer that the thryistor switches to a conductive state. The second semiconductor layer defines the gate region of the thyristor.

Mos type semiconductor device

Abstract: PURPOSE:To reduce the generation of carriers due to an impact ionization, to impress the change of the potential of a section where one of carriers generated is integrated at a minimum even on the integration of one of carriers generated in the first conduction type semiconductor layer and to increase the conductance of a MOSFET by extending a depletion layer in a second conduction type second semiconductor layer and weakening the field strength of the depletion layer. CONSTITUTION:A low-concentration N impurity layer 8 extends a depletion layer in a high-concentration N impurity layer 3 for a drain and weakens field strength in the depletion layer, and reduces the generation of carriers causing the lowering of source-drain withstanding voltage. A high-concentration P impurity layer 9 prevents the lowering of built-in voltage between a high-concentration N impurity layer 2 for a source and a P-type silicon substrate 1 even when holes in carriers generated are integrated to the front surface of the high-concentration N impurity layer 2 for the source, and obviates the inflow of electrons to the P-type silicon substrate 1 from the high-concentration N impurity layer 2 for the source. Accordingly, the increase of withstanding voltage, that is, fining-of a MOSFET is realized, and reliability is improved.

Vertical field effect semiconductive device

Abstract: PURPOSE:To make a vertical field effect semiconductive device having an enough safety voltage between the gate layer and the soruce layer, by supressing the spread of depletion layer on teh surface side.

Tunnel MIS solar cells

Abstract: In a recent publication we have proposed an explanation for the operation of Schottky‐barrier solar cells with an interfacial oxide layer based on the concept that they are minority‐carrier nonequilibrium MIS tunnel diodes. Such devices represent a potentially low‐cost method for fabricating large‐scale solar‐energy‐conversion arrays both with single crystals and polycrystalline film semiconductors. These solar cells are identical to the conventional p–n junction device except for the location of the depletion region. Our calculations indicate that one would have to grow defect‐free ultra‐thin (10–15 A in the case of Al–SiO2–Si structure) interfacial oxide layers to get highest conversion efficiencies from these devices. Performance of tunnel MIS solar cells will be described with main emphasis on the role of surface states and oxide charges.

Thermal emission from damage near the interface of Schottky barriers and its influence on thermally stimulated and transient current experiments

Abstract: The presence of damage layers close to the interface of Schottky barriers causes local band distortion in this region. This band bending is shown, under certain conditions, to produce a current flow in the opposite sense to that usually expected during emission from trap levels in a Schottky barrier depletion layer. The influence of this anomalous current flow on thermally stimulated current and transient current measurements is discussed. It is shown that this can produce erroneous results from these techniques, and measurements on GaAs Schottky barriers are given as specific examples.

X-ray escape peak variations in diodes made from doubly travelling solvent grown p-type CdTe

Abstract: 2014 The dependence of the escape peak height on the applied diode voltage was measured at diodes made from doubly travelling solvent grown CdTe The crystal was In-doped with a concentration of 21 1016 cm-3 and p-type with a resistivity of 4 x 106 03A9cm The escape peak height saturates at higher voltages The theoretical dependence of the X-ray escape probability on space charge layer depth was derived A method for evaluating the experimental curve according to the thoeretical correlation was developped : it yields the actual space charge layer depth and the space charge density REVUE DE PHYSIQUE APPLIQUEE TOME 12, FEVRIER 1977, PAGE The X-ray escape peak is a well-known phenomenon in CdTe gamma detectors ; it is much more pronounced than, for instance, in silicon The reason is the marked increase in the X-ray fluorescence coefficient co with the atomic number Z of the absorbing element For CdTe whose average Z is 50, OJK amounts to about 085, for Si it is 004, for Ge and GaAs 054 (Fig 1) FIG 1 The K-shell X-ray fluorescence yield as a function of the atomic number Z (from Bambynek, [4]) The process responsible for the occurrence of the escape peak in the gamma spectra of a CdTe detector is described (Fig 2) in the following for a detector structure with a space charge layer : in each energy transfer from the gamma quantum to a K-shell electron, a K-X-ray quantum is formed simultaneous to the photoelectron As shown in the diagram at the right-hand side of figure 2 the absorption length curves of photoelectrons and photons are rather different The K-X-rays generated have larger absorption lengths than the electrons and hence will escape from the space charge layer to the outside or to the field-free bulk region with higher probability than the photoelectrons The result is the well-known gamma spectrum with the full energy photopeak and when going to lower energies the escape peak at (E1 - EK) and finally the K-X-ray line This X-ray peak is either due to X-ray fluorescence quanta coming from the bulk CdTe and absorbed in the space charge layer or due to events of electron escape from the space charge layer at simultaneous absorption of the X-ray quantum arising from the same y-quantum The relative peak heights in such spectra are changed when the space charge depth is modified by reverse voltage variations Figure 3 shows two spectra taken at the lowest (5 V) and the highest voltage (200 V) with an In-doped doubly travelling solvent grown CdTe crystal This material was grown with zone temperature of about 800 °C at a speed of 43 mm/d In was added to the Te-zone prior to the second growth in form of a Cd-05 0/00 In-alloy resulting in a 35 x 101’ cm-3 concentration of In in Te According to Zanio [8], who gives a segregation coefficient for 880 °C growth Article published online by EDP Sciences and available at http://dxdoiorg/101051/rphysap:01977001202029300

Damage Introduced by Second Breakdown in N -Channel MOS Devices

Abstract: Failures in an N-channel MOS device as a result of electrical overstress are discussed in terms of "second breakdown transition".1,2) In the second breakdown state, large power, as much as 500–5,000 mW, is dissipated in the drain depletion layer. The power dissipation leads either to aluminum migration from the gate electrode to the substrate through the gate oxide or to the degradation of transistor properties. Most of the aluminum migration occurs in a localized area of the substrate surface, where the depletion layer of the drain region extends widely. The second breakdown transition in an N-channel MOS device is attributable to minority carrier injection from the source region to the substrate and to an increase in the impact ionization current in the drain depletion layer. The critical drain voltage of the second breakdown transition depends on the source-substrate bias, the substrate resistivity, the channel length and the gate voltage.

Method for making and using a group IV-VI semiconductor

Abstract: A method for making and using a group IV-VI photovoltaic semiconductor diode such that its capacitance is reduced substantially with respect to its capacitance if made and used according to prior art techniques. The capacitance reduction may be obtained without detrimental effect to the detectivity and noise levels of the diode. In the currently preferred form of the method, a thin film of p conductivity type semiconductor material, PbTe, is applied to (epitaxially grown on) a cleaved BaF2 substrate. A layer of Pb is deposited on the semiconductor material to form a diode having an n+ conductivity type region in the semiconductor material and a depletion region. When the PbTe semiconductor material is applied to the BaF2 substrate, its thickness is limited such that the depletion region extends to the boundary formed between the PbTe and BaF2 materials, either when the diode is formed or, preferably, when a backbias voltage, less than the diode reverse breakdown voltage, is applied across the p-n junction. The diode is particularly suitable for use as an infrared detector typically operated at 80° K.