Showing papers on "Diffusion capacitance published in 1986"

Optical and transient capacitance study of EL2 in the absence and presence of other midgap levels

Abstract: A high-resolution optical study was carried out on GaAs crystals grown by horizontal Bridgman and liquid-encapsulated-Czochralski methods. An excellent correlation was found between the intensity of the 1.039-eV no-phonon line and the characteristic absorption of EL2, the major deep donor level in GaAs. A correlation was also found between the characteristic optical absorption of EL2 and its concentration as determined by junction capacitance measurements. The presence of EL0, another midgap level contained in heavily oxygen-doped crystals at concentration always less than those of EL2, had no effect on the optical spectra, but altered the capacitance measurements. Accordingly, an accurate calibration for the determination of EL2 by optical absorption was obtained from capacitance measurements on crystals containing only EL2; in this way the uncertainties introduced by other midgap levels were eliminated.

Method and apparatus for measuring the capacitance of complementary field-effect transistor devices

Abstract: A combination inverter chain and ring oscillator (200) is used to measure the capacitance of a field effect transistor device (12, 85, 202) by measuring the current associated with propagating a signal through the circuit at a certain signal frequency. Where the device (12) is a CMOS pair, the capacitance thus obtained is reduced by a constant factor to take crowbar current (52) into account. Once the capacitance for a basic or reference device (84) has been determined, the basic structure may be modified to derive incremental per-unit area capacitances for various components of the device structure.

General considerations for interpreting junction capacitance in complex systems

Abstract: Many attempts have been made to provide theoretical and experimental methods to achieve a simple interpretation of the measurement of the capacitance of a junction as a function of reverse bias voltage. In this paper we present a quite general but simple formulation that includes all of these previous cases and is useful for describing experimental results in complex systems both conceptually and quantitatively. The results are useful especially for materials containing a high density of deep imperfection levels.

A measurement-based charge sheet capacitance model of short-channel MOSFET's for SPICE

Abstract: Based on the surface potential formulation[1], a charge-sheet capacitance model for short-channel MOSFET's has been developed and implemented in SPICE. No iterations are needed to find the surface potential. The model equations are charge-based and includes the drift velocity saturation, the diffusion current, the effect of the bulk charge, the channel length modulation and the channel side fringing field capacitances. As a byproduct of the development of this capacitance model, an analytic charge-sheet current model has been obtained. The current, charges, their first derivatives(conductance and capacitance) and second derivatives are continuous over all the operating regions. An automatic direct-on-wafer off-chip capacitance measurement system with 14 aF rms resolution has been developed for performing the model parameter extraction.

Very high speed operation of planar InGaAs/InP photodiode detectors

Abstract: Planar, diffused, InGaAs/InP PIN detectors have been optimised for high-speed operation. To minimise the junction capacitance the p-n junction diameter was reduced to 25 μm, resulting in operating chip capacitance as low as 20 fF. The relationship between the bandwidth and quantum efficiency was investigated by varying the thickness of the n-InGaAs absorbing layer, from 8μm down to 0.4 μm. Using optical heterodyning techniques, a response bandwidth ( -3dB) in excess of 20 GHz was demonstrated. The quantum efficiency of the fastest devices is 38% at 1.3 μm wavelength.

A 3.3-ps Josephson or gate with Niobium junctions

Abstract: In this paper, we describe the design, fabrication, and evaluation of a Josephson logic gate with all-niobium junctions. Recently, we reported a 4.2-ps Modified Variable Threshold Logic (MVTL) OR gate. We redesigned the MVTL gate, in order to confirm the feasibility of its use as an ultra high speed gate. The minimum diameter of the Nb/AiO x /Nb junctions was reduced from 2.5 µm to 2.0 µm to decrease the junction capacitance. Resistance and inductance values were also optimized to attain high-speed operation. We evaluated an OR gate with a 5- stage gate chain by means of the Josephson sampling technique. The measured minimum gate delay was 3.3 ps/gate for a power consumption of 9.1 µW/gate.

Optimized retrograde N-well for 1-/spl mu/m CMOS technology

Abstract: Using experiment and simulation, transistors in a high-energy implanted N-well are designed for optimum device performance suitable for 1-/spl mu/m CMOS technology. The effect of process parameters on device performance is obtained. Superior body effect, junction capacitance, punchthrough voltage, and subthreshold slope are achieved for 1-/spl mu/m n- and p-channel transistors. With shallow P/P+ epitaxial material, this retrograde N-well approach also provides latch-up immunity for high-density CMOS.

Planar embedded GaInAs photodiode on semi-insulating InP substrate for monolithic integration

Abstract: A back-illuminated planar embedded photodiode designed for integration into a high-bit-rate PINFET 1.2?1.6 ?m optical receiver has been fabricated by nonmasked LPE growth on a profiled substrate. A p-n?-n+ structure provides low series resistance on both p- and n-sides. The electrical and optical performance is good, with a junction capacitance of 70 fF at ?10 V.

Transit time and charge storage measurements in heavily doped emitters

Abstract: We report results of a first direct measurement of the minority-carrier transit time in a transparent heavily doped emitter layer. The value was obtained by a high-frequency conductance method recently developed and used for low-doped Si. The transit time coupled with the steady-state current enables the determination of the quasi-static charge stored in the emitter and the quasi-static emitter capacitance. Using a transport model, we estimated, from the measured transit time, the value for the minority-carrier diffusion coefficient and mobility. The measurements were done using a heavily doped emitter of the Si p+-n-p bipolar transistor. The new result indicates that the position-averaged minority-carrier diffusion coefficients may be much smaller than the corresponding majority-carrier values for emitters having a concentration ranging from about 3 × 1019cm-3to 1020cm-3.

Circuit built-in light-receiving element

Abstract: PURPOSE:To accomplish a high-speed responding operation of the titled element by a method wherein the specific resistance of an epitaxial layer is set low on the side of substrate (the lower part) which gives an influence upon the storage time of minority carrier, and the specific resistance is set high on the surface side (the upper part) which inflicts an influence on the junction capacitance of a photo diode, thereby enabling to cut down both junction capacitance of the photo diode and and the storage time of the minority carrier. CONSTITUTION:Among the epitaxial layers 12 of a circuit (bipolar IC) built-in light-receiving element, the thickness of the upper epitaxial layer 12a is set at the value or thereabout which is obtained by adding the component of a depletion layer extended on the side of the epitaxial layer 12 of a photodiode to the depth of diffusion of a P diffusion layer 11. The junction capacitance of the photo diode part is determined by the upper epitaxial layer 12a having large specific resistance, and the storage time of minority carrier is determined by the lower part epitaxial layer 12b having small specific resistance. The storage time of carrier is reduced by the lower epitaxial layer 12b, and the junction capacitance of the photo diode part is also reduced by the upper epitaxial layer 12a.

A technique for modelling p-n junction depletion capacitance of multiple doping regions in integrated circuits

Abstract: The continuing advancements in integrated circuit technology have placed new burdons on the circuit design engineer, who must rely extensively upon computer simulation to correctly predict circuit behavior. One challenge is to develop better modelling techniques to more accurately deal with complex p-n junction structures often used in modern VLSI designs. This paper presents an easily implemented method for deriving parameters which accurately model the behavior of MOS VLSI structures containing complex p-n junction capacitance components. The methodology is applicable to both planar and laterally diffused junctions, whether formed by direct ion implantation or by diffusion from a finite or infinite source. The theories behind the equations used and results of the application of this new technique are discussed. A flow chart for a fitter program based on the new method is presented and described. The corresponding program written for the TI-59 scientific programmable calculator is available. Final model parameters are given and are shown to produce a numerical capacitance model which is accurate to within 2%.

Driving circuit for laser diode

Abstract: PURPOSE:To omit wasteful currents, to reduce supply capacitance and to improve electric/optical conversion efficiency by fitting a switch switching by clock pulses or signal pulses connected to a laser diode or the series connecting circuit of the laser diod and a CR parallel connecting circuit. CONSTITUTION:When signal pulses S transmitted from a modulator MOD rise, an N-P-N transistor TrQ1 is conducted, driving currents rise, and currents flowing through a laser diode LD rise. An P-N-P TrQ2 is interrupted by the rise of clock pulses CLK at the same time, a parallel circuit to the LD is opened, the inter-terminal voltage of the LD suddenly rises, and charging currents flow into the junction capacitance of the LD. The storage charges of the Q2 are discharged through the LD. Consequently, an optical output P from the LD suddenly rises. When signals from the MOD fall, the Q1 is interrupted, the Q2 is conducted, a parallel circuit is formed, and the optical output from the LD rapidly falls. The parallel circuit is opened during the driving of the LD, thus omitting wasteful currents.

Method and apparatus for estimating life of light emitting diode

Abstract: PURPOSE:To elevate the accuracy of screening with the estimation of the life, by non-destructively measuring the emission delay time, injection current and junction capacitance of a light emitting diode to be measured. CONSTITUTION:A square wave low current pulse is outputted from a current pulse application circuit 4 to be inputted into a light emitting diode 6 to be measured through a switching circuit 2 and light is emitted at a specified cycle to be received with a light receiving element 7. A measuring circuit 8 measures the delay time between the drive current inputted into the light emitting diode 6 being measured and a photocurrent received with an APD7 to be memorized into a computer 1. Then, the junction capacitance at non-bias of the light emitting diode 6 being measured is gauged with a semiconductor capacitance meter 3. It is found that the delay time is in proportion to the junction capacity with a strong correlation. The estimation of a correlation curve (l) by regression analysis or the like with the computer 1 reveal that deviation from the correlation curve (l) means variations in the defect density among elements. So to speak, samples on the correlation curve (l) indicate the average life among all of those measured and thus, those samples farther above the solid line (l) have the shorter life.

Heterojunction type transistor

Abstract: PURPOSE:To improve the high speed and high frequency characteristics of the titled transistor by a method wherein a high resistance ion implantation region is provided on the circumference of the base region of a high density base electrode lead out region, excluding the part adjoining to the base region, in such a manner that the ion implantation region is contacted to the base electrode lead out region. CONSTITUTION:A substrate S consisting of N type GaAs single crystal is provided. The first semiconductor layer 1, consisting of an N type GaAs semiconductor, the second semiconductor layer 2 of P type high carrier density, and the third semiconductor layer consisting of N type (AlGa)As compound semiconductor are grown on the substrate S successively by performing an epitaxial growing method. A base electrode lead out region 5 is formed on the semiconductor layer 3 surrounding the part where an emitter region is formed. A high resistance region 12 is formed on the region 5 including its circumferential region. As a result, the capacitors Cbc and Cbc located between a base and an emitter, and the base and a collector can be sufficiently reduced based on the prescribed junction capacitance.

Driving circuit for semiconductor light-emitting element

Abstract: PURPOSE:To drive a LED at high speed by connecting a parallel circuit of a resistor and a capacitor in series with a semiconductor light-emitting element and connecting a base in a transistor at a node between the light-emitting element and the parallel circuit, a collector to another terminal for the semiconductor light-emitting element and an emitter to another end of the parallel connecting circuit of the resistor and the capacitor. CONSTITUTION:Charges stored in a capacitor 22 are discharged through a resistor 21, a LED19 and a transistor 20. Currents flowing through the LED19 flow in the direction that junction capacitance and diffusion capacitance are discharged at that time. When currents flowing through the LED are viewed by a comparison with pulses applied to a transistor 23, charging currents, stationary currents and discharging currents flowing in the opposite direction can be acquired by the circuit constitution. Currents flowing through the LED are represented by Id.

Experimental study of noise temperature and conversion loss of SIS junction mixers

Abstract: Experiments on the performance of superconductor-insulator-superconductor (SIS) tunnel junctions as heterodyne mixers at 40 GHz are reported. The techniques developed for the fabrication of multi-junction SIS series arrays differ from, and are considerably simpler than, other methods described in the literature. Results are reported on mixer noise temperature, conversion loss, saturation, local oscillator power levels and mixer dynamic range. Factors affecting the mixer's conversion performance are identified and comparisons are made with other reported results. It is concluded that mixer performance in the present experiments is limited by imperfect impedance matching at the signal frequency, due to relatively large values of parasitic capacitance in the junctions. Future work is aimed at both reducing the junction capacitance and redesigning the mixer mount to give improved r.f. matching.

Protective circuit for input

Abstract: PURPOSE:To improve transient response characteristics by reducing the time constant of an input section by an input protective resistor and an internal capacitor. CONSTITUTION:A P channel MOS transistor and an N channel MOS transistor 5 constitute a complementary type inverter circuit, and a gate for these transistor 4 and transistor 5 is connected to the + side D of a power supply through a diode 2 while being connected to the - side S of the power supply through a diode 3. An input to an input terminal 1 is transmitted over a gate electrode for the transistor 4 and the transistor 5 through a resistor 1 connected in parallel and a diode 6, and outputted from an output section O connected to a drain common connecting section between the transistors 4 and 5. The time constant of a time constant circuit formed by the junction capacitance of diodes 2, 3 and the gate capacitance of the MOS transistors 4, 5 is reduced. Accordingly, transient response characteristics are improved, and propagation delay time is shortened.

Local charge influence on impurity diffusion in semiconductors

Abstract: The impurity diffusion in semiconductors has been simulated numerically by considering the local charge present in the semiconductor during the process. Numerical results demonstrate the validity limits of the diffusion model based on the well known charge neutrality approximation.

Optical reception circuit

Abstract: PURPOSE:To reduce transmission lossed based on impedance mismatching by inserting a matching circuit comprising passive elements of no loss between an photoelectric converting section and a preamplifier section to combine both. CONSTITUTION:A reactive component in addition to a resistive component exists in a photoelectric converting section because of the inductive component of wire and a junction capacitance of a photodetector and in a preamplifier section because of a floating capacitance of the circuit, inductive component of wiring and an input impedance of an amplifier. Reactance compensating circuits 6, 8 eliminate the reactive component. Further, an impedance converter 7 takes matching by stepping up or down resistive components with a difference value. Thus, the loss is reduced in the operating band and it is possible to supply a reception signal to a load efficiently.

Nonlinear properties of electron junctions in the presence of a space charge

Abstract: The role of a space charge in the formation of nonlinear characteristics of an electron junction, into which is introduced an accelerated electron flow, is considered. To describe the reactive properties of a quasistationary space charge one uses the concept of differential capacitance. Analysis of the current regimes and of the nature of transitions between them made it possible to establish the regions of continuous and jumpwise variation of the differential capacitance as function of electric parameters, as well as to explain the regime of electron reflection, in which the value of the differential capacitance exceeds the value of the interelectrode capacity by several times. An equation is obtained for the reflection regime, which, independently of the electrode configuration, makes it possible to determine the variation in the junction capacitance from the value of the quasistationary space charge. Due to the practical significance of obtaining data on the nonlinear reactivity of an electron junction, its noise characteristics are considered. A specific HF current fluctuation is detected, occurring in the presence of noise minima for certain flight angles.

Manufacture of cmos ic

Abstract: PURPOSE:To equalize the magnitude of threshold voltage approximately, and to reduce the substrate bias effect and junction capacitance of an N channel MOSFET by simultaneously doping an impurity to channel sections in a P channel MOSFET and the N channel MOSFET through gate oxide films through ion implantation. CONSTITUTION:Sections 7 as channel regions in a P channel MOSFET and an N channel MOSFET and sections 8 where contact holes are formed onto high-concentration P-type diffusion layers and high-concentration V-type diffusion layers are photo-etched, and thin gate oxide films consisting of SiO2 in approximately 600-1,000Angstrom are shaped through heating treatment in an oxidizing atmosphere. Boron ions are implanted simultaneously into the surface of a substrate through the thin gate oxide films in both MOSFETs, thus changing the flat band voltage VFB of the sections 7 as said channel regions in the positive direction. Al electrodes 9 are formed, thus completing the element.

Bi-polar semiconductor memory device

Abstract: PURPOSE:To enable high-speed write and readout with small holding current by making the load means of a high-resistant diffused region. CONSTITUTION:An n type semiconductor buried layer 2 is formed in the surface of a p type semiconductor substrate 1. Further, a p type diffused layer 3 for capacitance increase is formed at the position where a capacitor is to be formed, and p type diffused layers 4 for channel stop are formed slightly off the buried layer 2. Since the diffused layers 4 are thus formed, they become integral with a p type semiconductor region 9 formed in a later process, and the junction capacitance is formed between the diffused layers 4 and the buried layer 2. Therefore, a capacitor with a capacitance enough for overdrive can be formed with a small area. Besides, since the p type semiconductor regions 4 for channel stop re located only under isolation layers 6, a large resistance value can be obtained with a small area.