Showing papers on "Digital electronics published in 1970"

BIAS-3-A program for the nonlinear D.C. analysis of bipolar transistor circuits

Abstract: A computer program for both analog and digital circuits that formulates and solves nonlinear equations for d.c. node voltages and transistor operating points is described. Temperature variations and dependence can be effectively simulated.

Functional Partitioning and Simulation of Digital Circuits

Abstract: In this paper we present a method for obtaining a functional partitioning of the logic of a computer. It is shown that given a basic function to be performed, such as addition, the computer logic can be partitioned into four disjoint sets, namely the active information logic I, the semiactive flip-flops l, the activated control logic c, and the dormant logic D. Techniques involved in implementing the partitioning algorithm such as an event-directed simulator and three-value simulation are discussed. An application of this partitioning scheme as part of a large logic simulation system is described.

Data Modems with Integrated Digital Filters and Modulators

Abstract: The application of a binary transversal filter as transmitting filter and a digital circuit as modulator makes it possible to construct data transmitters consisting only of transistors and resistors. The modulation distortion, caused by the keying of a low-frequency square-wave carrier, can be compensated by a modification of the transfer function of the transmitting filter, provided the carder frequency is chosen to be a multiple of half the bit rate. This principle makes it possible to realize the whole data transmitter in one single integrated circuit. The binary transversal filter, provided with an analog-to-digital converter, can also be used to construct the data receiver for the greater part with digital circuitry.

Quality of designs from an automatic logic generator (ALERT)

Abstract: Automation of the design of computer logic has evoked wide-spread interest and activity. Nevertheless, detailed comparisons of automatically generated logic and manually prepared logic have not been made available.The ALERT program is a logic generator which accepts as input a summary description of a new computer in a high-level language, and from this it compiles logic designs to carry out the functions specified. This paper examines the quality of logic generated by the ALERT system.The specifications of several computers have been processed through the ALERT system. This report discusses the most comprehensive design processed, the central processor of the IBM 1800 computer.The 1800 had been designed by conventional manual techniques prior to this study, and its logic schematics were, therefore, available for comparison with the logic generated by ALERT.It was found that the automatically produced circuitry required 160% more components than used in the corresponding parts of the actual computer. Reasons for this discrepancy are considered, and methods are described which are expected to reduce the discrepancy between automatically generated designs and manual designs.The study indicates that automatic generation of computer logic and circuitry from high-level system descriptions offers a practical and viable alternative to traditional methods of logic design. Within the limits of the study, the automatically prepared design was found to be correct, functional, and manufacturable.

Digital circuit demodulator for frequency-shift data signals

Abstract: FSK data signals are applied to a digital phase-locked loop having a countdown feedback circuit producing a signal wave which leads or lags the phase of the data signal by an angle which is dependent on the frequency of the data signal. The countdown circuit also generates a second signal wave which lags the phase of the feedback wave by a fixed angle. The unique permutations of concurrent amplitudes of the three signals are processed by sets of gates to recover the baseband signal. Counters monitor the outputs of the gates to detect steady tone signals and loss of carrier.

Training device for teaching digital logic operations

Abstract: A training device for instructing students in digital logic, which includes a desk size panel upon which digital logic operations may be fabricated and visually displayed, a plurality of digital logic circuit devices having means for both mechanical and electrical attachment to the panel, circuit connection means for connecting the digital logic circuit devices to a source of bias voltage supply for energizing the digital logic devices, circuit connection means for providing selected interconnections between the digital logic devices displayed on the panel, and means for providing input digital values to the interconnected digital logic devices. Both magnetic and plug-type embodiments are disclosed as means for mechanically and electrically attaching the digital logic devices to the panel.

Check Schemes for Integrated Microprogrammed Control and Data Transfer Circuitry

Abstract: The choice of fault detection methods to be used in control and data transfer circuits is strongly dependent on system organization. This paper presents a unified parity check scheme for both.

Distributed logic memory cell for parallel cellular-logic processor

Abstract: In a parallel cellular logic processor including a program control unit and a plurality of logic memory cells, all data inputs, except intercell inputs, for any cell are channeled through common input coupling logic to a one-bit intracell bus. The coupling logic is enabled or disabled in accordance with predetermined combinations of states of program control signals and of a plurality of control flip-flop circuits within the cell. Those flip-flop circuits receive data signal inputs from the bus. The same bus also provides data inputs for a data flip-flop circuit and for a data store within the cell. Data input to the bus is provided by way of the coupling logic from a program-selected one of the data flip-flop circuit, the store, an external source, or from program. Additional logic allows communication among cells by way of selective interconnection of their respective intracell buses as determined by further program control signals.

An All-Solid-State Digital Control System for Appliances

Abstract: A completely solid-state control system for domestic appliances has recently been developed at the D&M Research Laboratories. While this system was developed specifically for dish-washers, it is readily applicable to all appliances that exhibit complex control problems. The heart of the system is a large-scale custom metal-oxide semiconductor integrated circuit measuring approximately 0.1 inch on a side. This digital circuit, which comprises nearly 600 circuit elements, performs all of the timing and logic functions of the control system. The logic circuit provides for seven different cycles and three distinct temperature modes. However, a greater number or complexity of cycles can readily be incorporated on the logic chip at little additional cost. The integrated circuit controls the electro-mechanical devices in the appliance (such as motors, heater, sole-noids, and lights) through a set of triacs (i.e., bidirectional thyristors). The logic chip and the triacs are mounted on a single printed-circuit board measuring less than 5 inches on a side. The board also accommodates a noninductive regulated dual-level power supply and a novel circuit for electronically contralling the motor-start windings. The all-solid-state approach to appliance control becomes increasingly attractive as new and more sophisticated features (such as motor-speed control, water-level sensing, dryness sensing, etc.) are added to appliances and as the demand for greater reliability increases throughout the appliance industry. It now appears that the solid-state control system described will be economically competitive with comparable electromechanical systems in 1 to 2 years.

A system of computer aids for designing logic circuit tests

Abstract: A system of computer programs which aid in generating and validating logic circuit tests is described. Easy to use and available on a time-share computer, the system includes: 1) a preprocessor that translates a logic topology from a simple input language to binary (machine readable) form and determines indistinguishable fault sets, 2) an automatic test sequence generator for combinational circuits, and 3) a fault simulator for asynchronous sequential circuits. The faults considered are those causing any single wire branch to be fixed at logic 0 or fixed at logic 1. Wires which fan-out are simulated with independent faults on each fan-out branch as well as with faults common to all the fan-outs. Gates are simulated with unit delay and are allowed three possible logic values—0, 1 and “don't know”. “Don't know” is the starting value on every gate, representing the uncertainty of internal states when power is applied to a circuit. “Don't know” is also used to settle critical races and oscillations.

Modelling of transistors for fast integrated logic circuits

Abstract: A large-signal equivalent circuit is described based on a simplified analysis of the operation of a planar transistor. The extra stored charge in saturation and the d.c. characteristics are related to the geometry and impurity profile, and the results are used to define the value of the circuit elements.

Simulation of digital control systems on an analog computer with digital logic

Abstract: This paper describes a procedure for simulation of digital control systems on an analog computer with digital logic. The digital elements are only those normally provided in the digital panel now available as an optional accessory from most analog computer manufacturers. When used in conjunction with the conventional analog amplifiers and integrators connected as track-hold devices, it is possible to simulate complete systems which include not only the straightforward single-rate system but also those having two or more sampling rates or subsystems, and those having delayed or skip sampling characteristics. The digital logic connections for some simple but typical problems are given and are suggestive of those required for more sophisticated applications.A couple of oscilloscope photographs are included which show the informative presentation which can be obtained with this simulation technique.

Feasibility of using digital filters to interconnect p.c.m. and f.d.m. transmission systems

Abstract: A time-division multiplex (t.d.m.) and a frequency-division multiple (f.d.m.) system may be interconnected by means of gates and lowpass filters. The use of digital filters (d.f.s) for this purpose appears attractive when the t.d.m. system uses pulse-code modulation (p.c.m.), because digital-analogue and analogue-digital conversion are unnecessary at the interface between the d.f. and the p.c.m. system. The problems involved in applying d.f.s in this application are discussed. It is concluded that the interconnection of p.c.m. systems with f.d.m. systems using quite low carrier frequencies requires the development of digital circuits operating at several hundred megahertz.

An All-Digital Multichannel Narrow-Band FSK Data Receiver

Abstract: The advent of large-scale integration has suggested new approaches to signal processing problems. In the data transmission field, for example, a complete modem can be built entirely of digital circuits. Not only is this approach technically feasible, but it is economically attractive, if the inherent speed of the digital devices is utilized by time-sharing the hardware among a large number of channels. This paper describes, an entirely digital multichannel narrow-band frequency-shift-keying data receiver. Input signals from each channel are converted to digital form and processed sequentially by a time-shared arithmetic umt composed of recursive digital filters. A prototype has been built and tested. If offers performance comparable to existing analog equivalents, while allowing extensive size and cost potential reductions.

Acceleration of simulation time by hierarchical modelling

Abstract: The use of hierarchical data structures during the run time of simulation results in excellent performance values regarding model size and loading time without any loss of accuracy of the results. This paper describes the algorithms and techniques exploited by a hierarchical simulator and gives benchmark examples with regard to memory size and loading time for circuits of different size. Although this technique has been developed for the simulation of digital circuits, it is applicable to a broader spectrum of problems of discret simulation.

Principles of d.c. Transistorized ‘Nor’ Gates Design

Abstract: The main difficulties for designing transistor switching circuits, as transistorized ‘Nor’ gates, are connected with process of optimization several conflicting demands, the combined effect of which cannot always be considered during calculations directly In this paper the analysis of ‘Nor’ logic gates is formulated on the basis of graphic-analytic method4,5, permitting to take into consideration the total influence of circuitry parameters, variations due to temperature, loading and technology tolerances, etc, in order to obtain the reliable switching mode of operations It also allows to take into account dynamic and economic requirements for the further optimization, and from this point of view it can be very useful for many transistorized digital circuits including the integrated switching circuits for mass production

Digital control for primary radar systems

Abstract: An investigation into the use of digital logic techniques for simple pulsemodulated radar systems resulted in their application to provide the necessary controlling and timing waveforms for a display. The paper describes a conventional analogue display and its digital counterpart and compares both systems. Results for the performance of a logic system are given.

Transitional Delay Fault Test Generation Using AGenetic Algorithm

Abstract: With the continuous technological advancements in digital electronic circuit technology devices are becoming even more complex, it is essential that a high level of operational reliability is maintained which is why there is always a requirement for new and improved test methodologies. A fault condition in a digital circuit may be the result of a manufacturing problem causing physical imperfection in the device, this imperfection may be open circuit or short circuit connections, or a flaw that changes other characteristics of the device. The propagation of a gate may be affected introducing a delay defect into the circuit, often creating timing problems, which have always proved difficult to detect. This paper presents a new approach to the generation of test patterns that detect gross delay defects in combinational VLSI circuits. In O'Dare and Arslan [1] the authors presented a technique that implemented a genetic algorithm (GA) for the generation of test patterns to detect single stuck-at-faults in combinational VLSI circuits. In order to generate a test for delay faults it is necessary to create a transition in logical state at the fault site within the circuit, the only way to achieve this is by generating pairs of test patterns . The first test pattern initialises the state of all nodes within the circuit, the second test pattern is then used to force the required transition at the designated test node. The problem of test generation for delay faults is considerably more complex than that of test pattern generation for single stuck-at-faults presented in O'Dare and Arslan [1], with an increase in search space size from 2 n to 2 2n for an n input circuit. The problem is further augmented by the necessity of applying the two test patterns in a strict ordered sequence to create the required transition. The authors have therefore developed a new genetic test technique to overcome the problem, using chromosomes-pairs to represent the test patterns. The GAs primary component is a dynamically evolving Global Record Table (GRT), which is used to guide the search towards optimal test pairs in an otherwise complex solution space, producing a compact and efficient set of test pattern-pairs as the GA evolves. The experimental results presented in this paper are compared with other research results for well known combinational benchmark circuits.

Mathematical ``Lower Bounds'' and the Logic Circuit Designer

Abstract: The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder.

Comment on "A Transform for Logic Networks"

Abstract: The above-mentioned paper by K. S. Menger1 presents a restatement of logic functions in terms of the "macroelements" of Galois field (GF) arithmetic. Against the current background of LSI technology, this high- level hardware is going to be a welcome development.

Functional stability conditions for logic devices of K- valued logic

Abstract: For any input signal of logic elements (LE) which realize logical functions of K -valued logic to be converted into any output signal, it has been shown to be sufficient that the LE have 2(K- 1) different input-output characteristics without equal values of the output signal at neighboring discrete values of input signals. Sufficient conditions for stable operation of both long closed and short logical chains of elements with characteristics under consideration are formulated.