Showing papers on "Digital electronics published in 1973"

Segmented associative logic circuits

Abstract: Disclosed are logic circuits, comprising an array of logic elements interconnected in segmented groups of arrangement and number such that together they can generate signals representative of any required number of Boolean functions in response to binary signals applied to the logic elements in the different groups. Segmentation of associative logic permits the implementation of multiple output Boolean logic functions and sequential logic functions with optimum use of a given array area. The segmentation structure of associative logic circuits can be fixed or it may be programmed to form a variety of patterns or groups, such programming being possible either at the time of manufacture or by electrical or mechanical means subsequent thereto.

Bisitable digital circuitry

Abstract: Bistable digital circuits including cross coupled gates having complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input. Complementary unbalanced transfer characteristics of the threshold circuits provide widely separated high and threshold voltages approaching respective high and low supply potentials. The coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over in response to a change in logical level at the signal input.

Scanning apparatus for a matrix display panel

Abstract: A scanning apparatus for a matrix display panel having a plurality of picture elements at the intersections of X- and Y-line conductors. The scanning apparatus has an X-line driving circuit, Y-line driving circuit, a video signal generator, a timing signal generator, a width control signal generator, a second switching circuit and an analog-to-digital converter. The Y-line driving circuit has a plurality of sets of first memory circuits, a set of second memory circuits, a set of first switching circuits, and a set of brightness control circuits. The scanning apparatus is capable of reproducing moving images having many steps of gray scale from coded video signals having relatively few bits by digital circuits and is also capable of finely controlling the brightness by the efficient use of a horizontal sweep retrace period of the video signals with simplified circuits.

Computer-aided prediction of delays in LSI logic systems

Abstract: A computer program is described which was developed for LSI (large scale integrated) systems to resolve the uncertainties in transient delays prior to building the physical logic systems This computer program represents a departure from the conventional logic simulation programs where unit delays are assumed for individual logic elements The program takes into account all physical circuit variables at the mask composite stage in the design cycle Transient delays are computed and inserted into the logic simulation program

Integrated circuits in digital electronics

Abstract: Perspective Number Systems Switching Functions Combinational Logic Logic Gates Latches and Flip-Flops Sequential Circuits Arithmetic Circuits Coding, Code Conversion, and Error Detection and Correction Digital-to-Analog and Analog-to-Digital Converters LSI and VLSI Practical Considerations Index

Emitter function logic-logic family for LSI

Abstract: A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.

Practical considerations for analog operation of bucket-brigade circuits

Abstract: The bucket-brigade circuit offers a means of implementing a clock-controlled analog delay line in monolithic form. Operating in the sampled-data domain, it combines some of the advantages of both analog and digital circuits and appears to have a strong application potential in analog signal processing systems. In this paper, the analog operation of bucket-brigade circuits is described with respect to such practical operating considerations as bandwidth, dynamic range, linearity, power dissipation, baseband, signal recovery, a clock waveform noise. Experimental results from p-channel MOSFET and n-channel JFET brigades are presented.

Comparison of MOSFET logic circuits

Abstract: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.

Digital-summation threshold-logic gates: a new circuit element

Abstract: Threshold-logic gates are memoryless, multiple-binary-input single-binary-output circuits that operate by an arithmetic summation process to determine the 0 or 1 gate output state The availability of such gates would be of great advantage to digitial system design A new approach to the circuit realisation of such gates is presented here, ie to use digital-summation techniques within the gate circuitry, as distinct from the analogue-summation techniques previously employed The adoption of digital summation removes the former circuit-tolerance problems, and allows gates with great potential usefulness to be readily designed

Logic test probe and indicator circuit

Abstract: A test circuit for detecting low, high and open voltage levels, and dynamically changing voltage levels in a digital circuit includes a display panel and a probe provided with a plurality of indicators for signalling each of the possible level conditions sensed by the probe. The circuit also includes a current detecting circuit for providing an unambiguous indication when an open level is present. A pair of indicators provide information of the presence of dynamically changing levels while low and high level indicators provide information by way of duty cycles of the shape of the dynamic wave-form. An indicator is also provided for giving a sustained indication when an unexpected level change takes place and includes means for automatically resetting itself.

EFL logic family for LSI

Abstract: A highly-efficient LSI logic family combining the advantages of multi-emitter structures with the performance of ECL logic will be discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5 pJ performance.

Self-teaching machine for binary logic

Abstract: A self-teaching machine for binary logic wherein means are provided for programming the machine''s logic circuits to match a drawing of a logic system. Typically, the machine has a number of universal logic gates and an interconnecting network. Both the gates and their interconnecting network are programmable providing combinations to represent any one of several million logic drawings. The machine has the capability of being programmed to match the selected logic drawing by either the student or a preprinted matrix in one corner of the drawing. The student, after programming the machine with the desired logic drawing, then enters various logic situations via a column of situation selector switches. The machine displays, in relation to the selected drawing, the step-by-step logic flow through the network as a result of logic situations introduced. This machine is to assist maintenance technicians in becoming familiar with logic flow diagrams of complex mechanical electrical or electronic systems, and also to aid in trouble shooting and checking of particular systems.

Adaptive logic circuits for digital stochastic computers

Abstract: A theoretical and experimental investigation of adaptive logic elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics.

Analysis of architectural strategies for a large message-switching network: A case study

Abstract: State-of-the-art design of communication networks is characterized by the ubiquitous appearance of computer technology. All significant message-switching systems designed in the last ten years have used stored program processor controlled switching. Sophisticated terminals are also using small computers, and are otherwise dominated by the use of digital electronics. The telecommunications technological environment is characterized by rapidly changing cost-benefit relationships among system components, due primarily to the cost decline of digital logic.

Digital interface module

Abstract: An interface module making use of photo-optical coupling techniques both in the logical control circuitry and in the load waveform responsive circuitry to optimize the degree of isolation between digital circuits and an industrial environment with its associated high voltage and noise

Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic

Abstract: Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions The logic sharing permits more economical realizations than can be obtained using classical parity and triple-modular redundancy schemes for obtaining logic circuits with the corresponding property

Trends in semiconductor digital circuits

Abstract: The ways in which digital circuit design techniques have developed over the last 25 years are described. The interaction between circuit design and devices is discussed in the light of the range of compatibility of digital circuits and the systems which became possible with semiconductors which were not so with thermionic valve circuits.

Apparatus for detecting and counting coincidence of incoming logic signals

Abstract: Apparatus for trouble shooting digital circuits in which the repetition rate of coincidence between compared logic signals is not sufficient for the operation of an oscilloscope. A comparator circuit for the apparatus produces signals representing the existence of coincidence of compared incoming signals. A light emitting diode connected to the comparator circuit is operated when all the compared incoming signals are coincident at least for a prescribed duration. In addition, a counter circuit is connected to the comparator circuit. Light emitting diodes for the counter circuit are operated for indicating the count of the compared signals that are coincident for at least a prescribed time duration.

Design and application of a modified universal logic module

Abstract: The basic concept of an n-variable universal logic module (ULM-n) as developed by Yau and Tang is extended so that the input control functions are simple two-bit binary codes and not determined by one of the n variables. Although the resulting design is not a minimum pin configuration, it has the advantage that the control variables are 0 and 1. Basic ULM-2 and ULM-3 are developed and a method of using them to implement higher variable ULM's is also considered.

Simple MOSFET modeling for digital applications

Abstract: The charge-control concept provides a common base for the modeling of both the MOSFET and the bipolar transistor in digital applications. The dominating characteristics of common MOSFET digital circuits are contained in simple device models.

Fractional Frequency Synthesizer

Abstract: A simple technique is presented for using standard IC logic elements to synthesize frequencies. In particular, certain fractional multiples of a primary frequency may be synthesized for which no convenient techniques are available at digital logic levels. By utilizing the harmonic content of repetitive digital waveforns, sum and difference frequencies may be extracted from the output of the digital logic network. In effect, the new technique provides a type of digital mixing to accomplish frequency synthesis (or conversion) which is compatible with modern digital circuits. The circuit complements available techniques for division by an integer.

Binary frequency divider circuit

Abstract: A binary frequency divider circuit suitable for cascade operation is provided. A plurality of complementary MOS transistors are interconnected to provide a pair of complementary inverters and also to provide a pair of complementary combinational logic gates which function similarly to AND/OR combinational logic gates for the particular case wherein complementary logic input signals are provided.

Multi-phase pulse counter

Abstract: A multi-phase counter incorporates an n-stage n-stable trigger circuit, where n 6, 7, 8, . . . . . . . . , the stable states of this circuit being represented as output signals in a binary code, and n logic gates. The output of each stage of the trigger circuit is connected to the inputs of other s stages, where 3 < OR = s < OR = n -3. The output of each logic gate is connected to the input of the respective stage of the trigger circuit, the first inputs of the logic gates being the inputs of the counter, and the second input of each k -th logic gate, where k 1, 2, 3, . . . . . , n, is connected to the output of the (k + a )-th one of the stages, where the sum (k + a ) is taken by modulus n. In case both the logic gates and the stages of the trigger circuit are in the form of NOR logic elements, then a -d, where d is the smallest interval between the stages of the trigger circuit, that are in a binary 1 state. In case the stages of the trigger circuit are NOR logic elements, and the logic gates are AND logic elements, then a d.v-1, where v is the number of the stages in a binary 1 state.

Multiple Faults in Combinational Logic.

Abstract: : The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author)

Design and Application of Static Logic Directors

Abstract: A digital computer program written by Westinghouse engineers aids the design of new static logic systems for metal mills. The computer program accepts logic equations specifying the functions to be performed. The program generates circuit drawings of logic circuitry plus paper tape for controlling an automatic wiring machine. The automatic wiring machine wires the back panel receptacles for plug-in cards which contain the integrated-circuit AND/NAND logic elements. The design engineer determines functional requirements to be performed by the logic circuits. He expresses these requirements in convenient logic statement form and adds comments on circuit functioning. Logic and comment statements are keypunched for input to the computer. The computer analyzes the equations, converts the functions to AND/ NAND logic circuits and generates the punched-paper tape required by the automatic wiring machine. In addition, the computer generates the circuit diagrams showing the actual AND/NAND circuits with complete (JIC) cross references and comments on circuit functioning. During computer processing diagnostic messages are generated to aid in finding design errors. Only one type of logic board is used in the new static logic system to perform all logic functions. This reduces maintenance to mere board replacement and greatly reduces spare board inventory. Triac outputs are featured in addition to normal contact closure outputs. Traic is a static ac switch which can operate pilot-operated solenoid valves, contactors, indicating lights, and other common ac loads. The logic system combines the advantages of fully wired integrated-circuit logic with the convenience and accuracy of computer aided design.