Showing papers on "Digital electronics published in 1983"

Analysis and Design of Digital Integrated Circuits

Abstract: The third edition of Hodges and Jackson's Analysis and Design of Digital Integrated Circuits has been thoroughly revised and updated by a new co-author, Resve Saleh of the University of British Columbia The new edition combines the approachability and concise nature of the Hodges and Jackson classic with a complete overhaul to bring the book into the 21st century The new edition has replaced the emphasis on Bipolar with an emphasis on CMOS The book focuses on the latest CMOS technologies and uses standard deep submicron models throughout the book The material on memory has been expanded and updated As well the book now includes more on SPICE simulation and new problems that reflect recent technologies The emphasis of the book is on design, but it does not neglect analysis and has as a goal to provide enough information so that a student can carry out analysis as well as be able to design a circuit This book provides an excellent and balanced introduction to digital circuit design for both students and professionals Table of contents 1 Deep Submicron Digital IC Design 2 MOS Transistors 3 Fabrication, Layout and Simulation 4 MOS Inverter Circuits 5 Static MOS Gate Circuits 6 High-Speed CMOS Logic Design 7 Transfer Gate and Dynamic Logic Design 8 Semiconductor Memory Design 9 Additional Topics in Memory Design 10 Interconnect Design 11 Power Grid and Clock Design Appendix A A Brief Introduction to Spice Appendix B Bipolar Transistors and Circuits

NORA: a racefree dynamic CMOS technique for pipelined logic structures

Abstract: Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.

Reasoning about Digital Circuits

Abstract: : Predicate logic is a powerful and general descriptive formalism with a long history of development. However, since the logic's underlying semantics have no notion of time, statements such as I increases by 2 and The bit signal X rises from 0 to 1 can not be directly expressed. The author presents a formalism called interval temporal logic (ITL) that augments standard predicate logic with time-dependent operators. ITL is like discrete linear-time temporal logic but includes time intervals. The behavior of programs and hardware devices can often be decomposed into successively smaller intervals of activity. State transitions can be characterized by properties relating the initial and final values of variables over intervals. Furthermore, these time periods provide a convenient framework for introducing quantitative timing details. After giving some motivation for reasoning about hardware, he presents the propositional and first-order syntax and semantics of ITL. Demonstrated is ITL's utility for uniformly describing the structure and dynamics of a wide variety of timing-dependent digital circuits. Devices discussed include delay elements, adders, latches, flip-flops, counters, random-access memories, a clocked multiplication circuit and the Am2901 bit slice. ITL also provides a means for expressing properties of such specifications. Also examine are such concepts as device equivalence and internal states. Propositional ITL is shown to be undecidable although useful subsets are of relatively reasonable computational complexity. (Author)

Optical logic array processor using shadowgrams

Abstract: On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performing a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an incoherent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LED’s. Experimental results demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, we construct an optical logic array processor that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.

Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

Abstract: Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method for computer simulation is discussed.

Test Generation for MOS Circuits Using D-Algorithm

Abstract: An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both, the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

On Fault Detection in CMOS Logic Networks

Abstract: This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

GaAs digital dynamic ICs for applications up to 10 Ghz

Abstract: To evaluate the potentiality of GaAs MESFETs as transmitting gates, dynamic TT~ flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

Test-generation system for digital circuits

Abstract: In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it. At each point in this outline waveform at which the system needs to insert input signals, a test generator (18) is called by the waveform system (14) to derive a test vector based on information concerning the layout of the circuit, its possible defects, and its current state, the current state having been communicated to the data base (12) by the fault simulator (16), which determines the states that result from application of a waveform received from the waveform system (14). Even for non-scan-type circuits under test, the test generator derives only one test vector at a time, without searching through sequences of test vectors to find which sequences of test vectors might cause propagation of faults to the output ports of the circuit under test. It nonetheless efficiently derives test waveforms because it chooses among the fault effects of all faulty versions of the circuit concurrently for those effects that are likely candidates for propagation.

Programmable logic machine (A programmable cell array)

Abstract: The PLM is a single mask, programmable cell array with complete interconnect. It is 100% wireable and 100% testable with built-in LSSD, it achieves subnanosecond cell delay and 400-gate complexity with less than 1 W of power, and it is fabricated through a low-density process resulting in low cost and a four-day turnaround. This paper describes why the PLM was developed, its operational characteristics, and how it differs from conventional gate arrays.

Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay

Abstract: An axiomatic method for proving correctness properties about digital circuit implementations under the influence of asynchronous inputs is presented. This method, termed hardware correctness, is used to prove properties about a target digital circuit that is implemented in terms of constituent digital circuits. The proof consists of deducing theorems about properties of the target circuit from known properties of the constituent circuits. Three types of properties are considered, and they are expressed as axioms in first order predicate calculus. The axioms describe ideal behavior of the four most commonly studied asynchronous circuits, the inertial delay, the synchronizer, the time-bounded arbiter, and the latch. These axioms are derived from the less precise behavioral descriptions used by other investigators.

Dynamic CMOS logic circuits for implementing multiple AND-functions

Abstract: A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.

A Testability Measure.

Abstract: This thesis presents the current status of an algorithm which is used to calculate how testable a digital circuit is. The algorithm, or testability measure, is easier than calculating the entire test set. The algorithm calculates controllability and observability figures for each and every node in a given combinational or sequential circuit. These figures are approximations to the actual amount of time, and fraction of total input combinations which are needed to control and observe a given circuit node. Algorithm results can be compared to benchmark figures to determine their accuracy. Testability measure results are shown to be exact for fanout-free combinational circuits and feedback-free shift register circuits which are made using D flip-flops. Poor results are found to occur among the observability figures for stem fanout nodes, which showed up most noticably in multiple level parity trees. Chapter 1 TM Fundamentals 1.0 Introduction In this thesis we present a testability measure, abbreviated TM. The testability measure is an algorithm which works from a digital circuit at the gate and flip-flop level to produce a metric for each lead, or node in the given circuit. Testability measure results can be used to determine how testable the given circuit is. A small result, or figure, indicates that a node is difficult to test, while conversely, easily tested nodes have large figures. This chapter contains the background information that is necessary to be able to use the TM. The following section defines the applicability of the testability measure. The algorithm's objectives are discussed in the third section, Section 1.2. In the next section we define the terms that are used in this thesis. The last section contains an overview of the algorithm. A flow chart is included to add clarity to the discussion. The remaining chapters contain details of the TM calculations and the performance of the algorithm. Chapter 2 presents details of the algorithm calculations. In Chapter 3 we show how to calculate exact testability 2 figures and thus judge their accuracy. The TM's major strong and weak points are discussed in Chapter 4. The last chapter, Chapter 5, contains our concluding remarks on the algorithm and our ideas concerning future research. 1.1 Scope of the TM Algorithm TM calculations are performed on digital circuits. The permitted class of circuits includes combinational circuits and clocked sequential logic networks. The algorithm has been formulated to operate only on circuits with a single output, so that multiple outputs must be treated as an array of single outputs. Redundant networks (circuits which contain excessive logic) and asynchronous circuits are not included in the permitted class of circuits. The permitted combinational logic gates include And, Or, Nand, Nor gates and inverters. Exclusive Or gates must be broken down into a more basic form. D flip-flops and JK flip-flops are the permitted sequential logic elements. For SR flip-flops our algorithms are incomplete. 1.2 Algorithm Objectives The objective of this thesis is to formulate a testability measure that is indicative of testing difficulty. The algorithm must show which portions of a given circuit are hard to test, and which are easy to test. It also must be easier to compute than finding the entire test set. If this were not true, then there would be no advantage in using the TM. And finally, we should be able to compare the testability measure's results to a rigorous measure's results. Thus we want to create a measure which is easy to calculate and has results that are meaningful. A primary feature of our TM is that the results have meaning. They are approximations to exact results in purely combinational networks. In sequential circuits they are approximations to benchmark calculations. The benchmark results, while not exact, do indicate how testable a circuit is. 1.3 Definition of Terms The TM requires that all combinational logic be. level organized. Level organized circuits are set up in the following manner. All primary inputs (PI) will be placed at the left-hand side of the circuit. The first level, the left-most set of gates, have as inputs only Pi's and complemented Pi's. The next level should have as inputs the outputs of the first-level gates, complements of the first level outputs and only complemented or uncomplemented Pi's. A gate, G,, cannot be on the same level with a gate, G„, if the output of G„ is used as an input to G. . Gates can have as inputs onlygate outputs of the previous level(s) and possibly Pi's. Thus a gate at level i must have at least one input from a gate output at level i-1 and can have other inputs which are either Pi's or outputs of gates in level 1, 2,...,i-2. Each possible primary input combination is called N a vector. If there are N Pi's, then there are 2 distinct vectors. The term vector is also associated with sequential circuits. A state vector in a sequential circuit is the set of bits that make up the coding of a M state. A circuit with M flip-flops has 2 different state vectors. The TM generates two figures for each node in a circuit. One of these is the controllability figure, a concept first developed by Goldstein (see Reference (2) ) . Each node has two controllability figures, the onecontrollability and the zero-controllability. The onecontrollability describes the ease, or difficulty, of setting a node to a one. The one-controllability of node x is denoted by C . The zero-controllability of node x, denoted C , describes the difficulty of setting node x to a zero. Control of a lead to a one (zero) is dependent on the fraction of the total number of vectors which set the lead to a one (zero) and on the amount of time that must pass before the node is actually set. To describe these factors the one (zero)-controllability is split into the fractional one (zero)-controllability and the one (zero) time frame number respectively. The time frame number, abbreviated TFN, denotes the number of clock periods, or time frames, which are needed to control a node to a one (zero). The TFN is taken from Kovijanic[4]. In a purely combinational network, for example, the one (zero)-TFN is equal to zero for all nodes because the circuit is unclocked (gate delays are ignored). In Eg. (1-1) we write the one (zero)-controllability of node x as a two-tuple C^ = {A,B} (1-1) where A is the fractional one (zero)-controllability and B is the one (zero)-TFN. The fractional one-and zerocontrollabilities are restricted to the range [0,1]; thus in Eq. (1-1) we have 0 £ A 1 1. (1-2) We must ensure that the fractional controllabilities never exceed these bounds. Any results which are out of bounds are forced back into the permitted range by using Eq. (1-3). If A > 1, then A = 1.0 (1-3) If A 1 -»• F = 1.0 (1-6) F F=0.0 1.4 Overview of the TM Figure 1-1 is a flow chart of the TM algorithm. It highlights the procedure and order of the TM calculations; details are contained in the next chapter. The controllability calculations are performed first and the network is processed level-by-level, proceeding from inputs to outputs. This is another idea which was first formulated by Goldstein in Reference [2]. For sequential circuits with feedback loops we iterate through the levels until the fractional controllability figures converge. Observability calculations are performed second, proceeding from output to input.* We do not iterate the OBS calculations. The remainder of this section is devoted to explaining selected portions of Fig. 1-1. * see Goldstein, Reference [2]

Logic Partitioning for Minimizing Gate Arrays

Abstract: This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.

Concurrent fault simulation of MOS digital circuits

Abstract: The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of faults. We show how this technique can be applied to metal-oxide-semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck-open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the peformance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques.

Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

Abstract: BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques

Abstract: This paper describes a method for the automatic synthesis of multiple-valued combinational logic circuits using automatic theorem proving techniques. Logic design of multiple-valued circuits is considerably more complex than binary design because of the associated combinatorial explosion. Two general approaches which can be taken in axiomatizing the environment of combinational logic design in multiple-valued logic have been investigated. These axiomatizations, formulated in the language of first order logic, are used to state the problem of combinational logic design as a theorem proving problem. This formulation together with a representation of the function being designed can be used as input to an automatic theorem proving program. The circuit design can then be obtained from the proof generated by the theorem prover.

Semiconductor integrated circuit

Abstract: PURPOSE:To obtain a semiconductor IC containing both analog and digital circuits with which the power consumption is reduced, and the constituting IC is achieved by supplying the power only to the analog circuit. CONSTITUTION:A power supply ON signal is fed to an interface (INF)21 from a digital control circuit 11, and the output of the gate G1 turns off a transistor TRTv. Then the current mirror circuits of TRT1 and T2 flow a current I1 equal to that of a constant current source 20 to a TRT5. Furthermore a current I1 is supplied to the INF21 by the current mirror circuits of TRT5 and T6 as well as TRT3 and T4, and the INF21 is turned on. When the INF21 is turned off, the INF21 is made inactive by a logic signal via a gate G2 and then a TRT7 is turned on by a power supply OFF signal input. Then the supply of current is stopped to the TRT5 and T6, and then the supply of current is cut to the INF21.

Digital circuit for determining the envelope frequency of PCM encoded call progress tones in a telephone system

Abstract: A digital tone detector circuit characterizes the received PCM encoded signals as one of a plurality of call progress tones, voice signals or silence. The PCM signal is linearized and normalized to a predetermined level in a digital automatic gain control circuit which also provides a signal corresponding to the level of the input signal. A first circuit is responsive to the linear signal for providing a count of the zero level traversals incurred by the linear signal. An envelope detector circuit is also responsive to the linear signal for providing a signal representing the envelope frequency thereof. The composite results corresponding to the signal level, the zero-level traversal count, and the envelope frequency are translated in an evaluation logic circuit to provide an output signal representing the identity of the input PCM signal. A microprocessor is responsive to a plurality of the output signals from the evaluation logic circuit for determining the cadence of the received PCM signals.

A versatile CMOS rate multiplier/variable divider

Abstract: A versatile integrated circuit that delivers an optimally spaced output signal is presented. The paper includes a comparison of the commonly used rate-multiplication scheme and the accumulator rate-multiplier principle. It is shown that this principle always delivers the best possible digital approximation of a regular signal, but it is inherently slower. The design considerations for speed improvement are described, together with a scheme that leads to the special feature of a programmable denominator. In this case, the circuit can be used as, for example, a binary rate multiplier, BCD rate multiplier, and variable divider, etc. Cascading possibilities are shown, and some application areas are given. The circuit is ideally suited for use as a microprocessor compatible peripheral circuit in digital control systems.

Emitter coupled logic circuit controlled by a set input signal

Abstract: An emitter coupled logic circuit includes a differential transistor pair and a set transistor, which are all emitter coupled. The logic level of the high voltage side of a set input signal to be applied, as a control input signal, to the set transistor is higher than the logic level of the high voltage side of the logic input signal pair to be applied, as control input signals, to the differential transistor pair. Simultaneously, the logic level of the low voltage side of the set input signal is lower than the logic level of the low voltage side of the logic input signal pair.

Addressing and control of high-speed logic circuits with picosecond light pulses.

Abstract: We demonstrate complete logic-level switching in high-speed GaAs field-effect transistor circuits addressed by picosecond light pulses, and logic-function control thereby. Besides their applicability to high-speed data processing in gigahertz-rate communication links, such experiments show potential for contactless diagnostic procedures for test circuits and for picosecond-resolution measurements of on-chip response times of logic gates by means of optical sampling techniques.

Smarter radiation monitors for safeguards and security

Abstract: Radiation monitors for nuclear safeguards and security depend on internal control circuits to determine when diversion of special nuclear materials is taking place. Early monitors depended on analog circuits for this purpose, subsequently, digital logic controllers made better monitoring methods possible. Now, versatile microprocessor systems permit new, more efficient, and more useful monitoring methods. One such method is simple stepwise monitoring, which has variable alarm levels to expedite monitoring where extended monitoring periods are required. Another method, sequential probability ratio logic, tests data as it accumulates against two hypothesis - background, or background plus a transient diversion signal - and terminates monitoring as soon as a decision can be made that meets false-alarm and detection confidence requirements. A third method, quantitative monitoring for personnel, calculates count ratios of high- to low-energy gamma-ray regions to predict whether the material detected is a small quantity of bare material or a larger quantity of shielded material. In addition, microprocessor system subprograms can assist in detector calibration and trouble-shooting. Examples of subprograms are a variance analysis technique to set bias levels in plastic scintillators and a state-of-health routine for detecting malfunctions in digital circuit components.

Architectures For A Sequential Optical Logic Processor

Abstract: A general technique is described for implementing sequential logic circuits optically The system consists of a nonlinear transducer which provides a two-dimensional array of gates and one or more computer generated holograms (CGHs) to interconnect the gates The limitations on the number of gates which can be implemented in an optical system is affected by the interconnection method We describe three interconnection methods and their respective limitations One method, which is a hybrid of space-variant and space-invariant CGH elements, provides high gate densities and high gate-utilization rates© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering Downloading of the abstract is permitted for personal use only

Logic Circuit Synthesis Using Prolog

Abstract: This paper briefly reviews the current use of CAD in logic design, and then describes an expert system used to synthesize logic circuits. Specialized knowledge dealing with standard TTL ICs is written in Prolog and AGE, and the results are compared.

Automatic and hierarchical verification of asynchronous circuits using temporal logic

Abstract: Establishing the correctness of complicated asynchronous circuit is in general quite difficult because of the high degree of nondeterminism that is inherent in such devices. Nevertheless, it is also very important in view of the cost involved in design and testing of circuits. We show how to give specifications for circuits in a branching time temporal logic and how to mechanically verify them using a simple and efficient model checker. We also show how to tackle a large and complex circuit by verifying it hierarchically. f.This research was partially supported by NSF Grant Number MCS-8216706.

Computer-aided synthesis of pla-based systems

Abstract: VLSI (Very Large Scale Integration) circuit design requires the use of computer aids in conjunction with a structured and hierarchical methodology to be economically feasible. Programmable Logic Arrays (PLAs) are regular structures widely used in the design of complex digital circuits, such as microprocessors. PLA-based systems can implement combinational and sequential functions and are amenable to automated synthesis. Optimal automated design of PLA-based systems is addressed here. Design of PLAs involves four basic steps: functional, logic, topological and physical design. In particular, new techniques for logic and topological design of PLA-based systems are introduced. Folding and partitioning are two topological design techniques that involve the reorganization of the array to reduce the silicon area occupied and improve the switching-time performance. Folding allows to implement a PLA in a smaller area, by rearranging the positions of the active devices and interconnections. Optimal PLA compaction is studied in connection with the problem of interconnecting the array to other circuit building-blocks. A new technique, multiple constrained folding, allows to achieve a minimal PLA area implementation with constrained positions of electrical inputs and outputs. Several new folding algorithms are described. Experimental results, obtained by computer program PLEASURE, are reported. Partitioning exploits the use of redundant columns and/or rows to transform a PLA into an array having the same functionality and a conveniently partitionable structure. Partitioned PLAs are implemented as block-folded arrays or as the parallel connection of PLA sub-units. An algorithm based on a graph representation of the PLA partitioning problem is presented. Experimental results, obtained by computer program SMILE, are reported. Logic design of PLA-based implementations of sequential functions, represented by Finite State Machines (FSMs), is then addressed. In particular, the optimal state assignment problem is studied in connection with logic minimization of the combinational component of the FSM. A binary encoding of the states (assignment) is optimal when the unfolded/unpartitioned PLA area is minimal. Due to the computational complexity of the problem, a heuristic technique for state assignment is presented. First the class of present-state assignments that minimize the PLA rows is determined. Then a minimal-length assignment (leading to a minimal-column PLA) is selected. Experimental results, obtained by computer program KISS, are reported.

Time response of small capacitance tunnel junctions and the simulation of fast logic circuits

Abstract: A simulation method of small time constant Josephson tunnel junctions is developped It is based on a first order series expansion of the time dependent Josephson current given by the microscopic BCS theory The method is well adapted to the switching dynamic of logic gates when the RSJC model lacks of accuracy, has a comparable efficiency both in computer time and memory space The scaling down of resistively coupled logic gates is presented among the illustrations

Real Time Event Selection and Flash Analog-to-Digital Converters

Abstract: In high-energy particle experiments, high-speed analog logic is employed to select events on a real-time basis. Flash analog-to-digital converters replace the high-speed analog logic with digital logic. The digital logic gives great flexibility to the scheme for real-time event selection. This paper proposes the use of flash A/D converters for the logic used to obtain the total sum of the energy deposited in individual counters in a shower detector.