Showing papers on "Division (mathematics) published in 1982"

Fraction bus for use in a numeric data processor

Abstract: A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words of BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

Cell growth and division

Abstract: This section explains what problems growth causes for cells. 1. What are two reasons why cells divide rather than continue to grow indefinitely? a. b. 2. Is the following sentence true or false? As a cell increases in size, it usually makes extra copies of its DNA. 3. Circle the letter of what determines the rate at which food and oxygen in a cell are used up and waste products produced.

No division implies chaos

Abstract: Let / be a closed interval in /?' and/: / -» / be continuous. Let x0 G / and ft \\ r • -^ n */+!=/(*/) forOO. We say there is no division iox (xx, x2,. ■ ■ ,x„) \\i there is no a G / such that Xj < a for ally even and Xj < a for ally odd. The main result of this paper proves the simple statement: no division implies chaos. Also given here are some converse theorems, detailed estimates of the existing periods, and examples which show that, under our conditions, one cannot do any better.

A Theory for Protocol Validation

Abstract: This paper introduces a simple algebra for the validation of communication protocols in message passing systems. The behavior of each process participating in a communication is first modeled in a finite state machine. The symbol sequences that can be accepted by these machines are then expressed in "protocol expressions," which are defined as regular expressions extended with two new operators: division and multiplication. The interactions of the machines can be analyzed by combining protocol expressions via multiplication and algebraically manipulating the terms.

A recursive sweep-plane algorithm, determining all cells of a finite division of R d

Abstract: “Sweep-plane” algorithms seem to become more and more important for the solution of certain geometrical problems. We present an algorithm of this kind that enumerates the cells of all dimensions into whichR d is partitioned by a finite set of hyperplanesF 0 . A plane sweeping through space (remaining parallel to itself) finds new cells each time it includes an intersection of someF 0 (normally a point). An analysis of the intersection-properties allows the construction of an algorithm recursive with respect to the dimension of space. Full generality has been one of our main objectives.

Cyclic division algebras

Abstract: A general example of cyclic division algebra is given, based on a construction of Brauer, yielding examples of division algebras of arbitrary prime exponent without proper central subalgebras, and also noncrossed products of arbitrary exponent.

Mathematical teaching cards

Abstract: A series of mathematical teaching cards consisting of a plurality of decks each having a level of difficulty identification, a plurality of sets of mathematical statements having the same answer, and a deck identification number is disclosed and described. The teaching cards may be used for multiplication, division, subtraction, and addition or any combination thereof.

Memory with permanent array division capability.

Abstract: A memory (10) can be divided to provide a reduced number of accessible memory elements. By selectively causing an individual address to always assume of predetermined logic state, the number of accessible memory elements is reduced by one half. The selection as to which half is accessible is achieved by applying to an array divider circuit (22) the individual address signal data logic state which corresponds to the predetermined then applying to the array divider circuit (22) an array divider signal. The array divider circuit (22) subsequently provides the individual address signal at the predetermined logic state effectively reducing the number of accessible memory elements by one half.

Splash guard ring for pipe flanges

Abstract: A splash guard ring insures the safe exist of liquid underline pressure from pipeline without splashing and without the dangerous projection of the stream of liquid. The features of the splash guard ring provide for the division of the area enclosed by the ring itself and the flanges of adjoining pipe members in the pipeline. The divided areas are interconnected such that liquid flowing from the pipeline is diverted into smaller streams partially opposing and/or crossing each other.

Apparatus for speeding up digital division in radix-2n machine

Abstract: A division A/B where A and B are represented in a radix D can be accomplished by evaluating a power series. It is very important not only for the power series to converge but also to converge quickly in practical application. Thus, the convergence rate of the power series must be small in order to obtain a reasonably good approximation of the quotient by evaluating the first few terms. The acceleration method that guarantees to give a small convergence rate, 1/(2D-3 ), of the power series (see the section of the related application) was proposed with at most three successive applications of acceleration constants. This invention reduces the convergence rate, 1/(2D-3), to a smaller convergence rate, 1/(2mD-3), in the worst case where m=1,2,2 2 ,2 3 ,2 4 , . . . and the three successive applications of acceleration constants to at most the two successive applications of the constants. These two reductions promise to yield faster division in digital computer.

Digital time division multiplex system for transmission and switching tasks

Abstract: The subject matter of the invention is a digital time division multiplex system with a bit clock frequency of 139.264 MHz for transmission and switching tasks. A single frame of the time division multiplex system comprises 68 columns and 32 lines which contain 2176 time slots, each with 40 bits. The time slot no. 1 (column 0, line 0) contains a sync word for frame synchronisation.

Method and apparatus for demodulating time-discrete frequency-modulated signals

Abstract: Method for demodulating time-discrete frequency-modulated signals The method includes combining sequential equidistant samples of a signal to be demodulated for deducing the instantaneous frequency of the signal to be demodulated The improvement includes dividing a first vector sum of samples forming a dividend by a second vector sum of samples forming a divisor Each sample is a complex number represented by a vector The vector sum of the dividend has a phase that is offset from the vector sum of the divisor by a phase angle equal to n times pi, wherein n is any integer The division of the vector sums is advantageously performed by a ROM in which all the division results have been stored and which can be accessed by the divisor and the dividend for quickly obtaining the division result Delay lines and summing circuits are used for combining the samples into the dividend and the divisor

Heuristic for the line division problem in computer justified text

Abstract: References I. Baudet, G.M. On the branching factor of the alpha-beta pruning algorithm. Artificial Intelligence 10, 2 (April 1978), 173-199. 2. Fuller, S.H., Gaschnig, J.G., and Gillogly, J.J. An analysis of the alpha-beta pruning algorithm. Department of Computer Science Report, Carnegie-Mellon University, (1973). 3. Knuth, D.E., and Moore, R.N. An analysis of alpha-beta pruning. Artificial Intelligence 6 (1975), 293-326. 4. Kuczma, M. Functional Equations in a Single Variable. Polish Scientific Publishers, Warszawa, (1968), p. 141. 5. Pearl, J. Asymptotic properties of minimax trees and gamesearching procedures. Artificial Intelligence 14, 2 (Sept. 1980), 113-138, 6. Pearl, J. A space-efficient on-line method of computing quantile estimates J. of Algorithms 2, 2 (June 1981) 24-28. 7. Roizen, I. On the average number of terminal nodes examined by alpha-beta. UCLA-ENG-CSL-8108, Cognitive Systems Laboratory, University of California, Los Angeles, (1981). 8. Slagle, J.R., and Dixon, J.K. Experiments with some programs that search game trees. JACM 16, 2 (April 1969) 189-207. 9. Stockman, G. A minimax algorithm better than alpha-beta? Artificial Intelligence 12, 2 (Aug. 1979), 179-196. 10. Tarsi, M. Optimal searching of some game trees. UCLA-ENGCSL-8108, Cognitive Systems Laboratory, University of California, Los Angeles, (1981). (To appear in JA CM.) Programming Techniques And Data Structures Ronald L. Rivest* Editor

Telecommunication path substitution arrangement

Abstract: A time division switching system having distributed control processors is disclosed. The switching system includes time-slot interchange units having associated subscriber sets and conference circuits and a time-shared space division network for interconnecting the time-slot interchange units. Each of the time-slot interchange units and the time-shared space division network are controlled by separate control processors. In response to called subscriber set identifying information from a calling subscriber set, the control processor associated with the time-shared space division network completes standard communication paths through the time-shared space division network to connect the time-slot interchange units associated with the calling and called subscriber set. Standard communication paths are replaced with conference paths which include a conference circuit, by establishing the conference path, transmitting information on both the standard and conference paths, and selectively releasing the standard path when continuity can be assured on the conference path.

Liquid crystal driving apparatus

Abstract: A liquid crystal driving apparatus comprises a plural number of first signal lines arranged on the front surface of a liquid crystal panel, a plural number of second signal lines arranged on the back surface of the liquid crystal panel in the direction intersecting the first signal lines at right angles, third signal lines arranged between the first signal lines, fourth signal lines arranged between the second signal lines, and a time division driving signal generator and a selection driving signal generator. The time division driving signal generator supplies time division driving signals to the first and fourth signal lines. In synchronism with the time division driving signals generated by the time division driving signal generator, the selection driving signal generator supplies selection driving signals to the second and third signal lines.

Transmission having a constant torque ratio output at a variable speed ratio output

Abstract: The transmission has a power division transmission which is adapted to provide a variable speed division with a constant torque division. The power division transmission has three branches comprising a motor input shaft and two branched transmissions. Each branched transmission is associated with a separate output shaft. At least one further power division or differential transmission is associated with the branched transmissions and the input shaft and has a rotatable transmission part. This latter part is connected to a speed control means such that the degree of slip between the branched transmission output shafts can be varied and/or controlled.

Algorithmic skill vs. conceptual understanding

Abstract: With the help of Pascual-Leone's Theory of Constructive Operators, this study investigated the hypothesis that understanding of the long division algorithm requires a high cognitive level, or greater m-capacity, than does understanding of the fundamental concepts of division. Formal and preformal sixth grade students were tested on performance and understanding of a given division algorithm and division concepts.

Incremental length or angle measuring device

Abstract: In addition to the measuring division (T) and to the reference marks (R1...Rn), this incremental length or angle measuring device further has, in accordance with Figure 2, at least one further grid division (T') whose division period (TP') differs from the division period (TP) of the measuring division (T). This difference is determined in each case upon the occurrence of a reference mark (R1...Rn) and is a detecting feature for the position of the respective reference mark (R1...Rn) with reference to a specific zero point.

Multiplaying and dividing circuits

Abstract: PURPOSE:To execute an operation of multiplication and division, which is low in power consumption and high in speed, by constituting a unit circuit of a C-MOS gate, constituting a division carrying circuit of an E/D type MOS gate, and reducing the number of elements and a chip area. CONSTITUTION:Binary numbers P0, P1-P7 of 8 bits are multiplied by binary numbers B0, B1-B7 of same 8 bits, binary numbers S0, S1-S15 of 16 bits, being said multiplied value are derived, or binary numbers A0, A1-A14 of 15 bits are divided by binary numbers B0, B1-B7 of 8 bits, and the quotient shown by binary numbers Q0, Q1-Q7 of 8 bits, being said divided result, and the remainder shown by binary numbers S0, S1-S15 of 16 bits are derived. These operations are selectively designated by a control signal. In this way, when a unit circuit is constituted of a CMOS gate, and a division carrying circuit is constituted of an E/D type MOS gate, a chip area is reduced, and the processing of multiplication and division, which is low in power consuption and high in speed is executed.

Multiplying circuit of complex number

Abstract: PURPOSE:To reduce the number of multiplying circuits, by arranging in time-division within the unit computing time for both the real and imaginary number parts of a multiplicand. CONSTITUTION:The real number part (a) and the imaginary number part (b) of the multiplicant of the complex number supplied the input terminals 1 and 2 are arrayed in time division and within the unit arithmetic time (s) through a time dividing circuit 20 and with a timing T1. The output of the circuit 20 is supplied to the 1st and 2nd multiplying circuits 7 and 8 as a multiplicand respectively. While the real number part (c) and the imaginary number part (d) of the multiplier of the complex number supplied through input terminals 3 and 4 are supplied to the circuits 7 and 8 respectively. A multiplication is carried out between the parts (c) and (d) of the multiplicand and multiplier arrayed in time division through the circuits 7 and 8 to obtain products (e) and (f). These products (e) and (f) are delayed through delaying circuits 21 and 22 and by 1/2 unit computing time interval to deliver products e' and f'. A subtraction is carried out between e' and (f) through a subtracting circuit 11, and an addition is carried out through an adding circuit between (e) and f' to obtain a difference (g) and sum (h). Both (g) and (h) are latched by latching circuits 13 and 14 to obtain both the real and imaginary number parts of the product of a complex number.