Showing papers on "Effective number of bits published in 2001"

Baseband processors and methods and systems for decoding a received signal having a transmitter or channel induced coupling between bits

Abstract: Received signals are decoded based on a coupling between bits of the received signals introduced by the channel over which the signal is transmitted or by the transmitter which transmitted the signals. For example, in a higher-order modulation scheme, such as 8-PSK, individual bits grouped in a given symbol are generally coupled rather than fully independent. Accordingly, decoding information on a first one of the bits processed through a forward error correction decoder may be used to adjust the soft information from a demodulator for one or more of the other bits contained in the same symbol for use in processing those bits through the forward error correction decoder. Particularly where interleaving is utilized, a first bit may be processed through the decoder before the soft information on another of the bits is needed, thereby allowing an intermediate decision soft value for the first bit to be used in generating the input value to the decoder for the subsequent bit. Alternatively, a multi-pass process may be utilized which may allow all of the bits to be decoded utilizing soft information from the first decoding pass to affect the input to the decoder during the second pass for coupled bits such as those transmitted in a common symbol.

Decoding system and method for digital communications

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Method for allocating bits and power in multi-carrier communication system

Abstract: A method of transmitting a data bit stream on a multi-carrier transmission system is provided. The steps include estimating a signal to noise ratio for each carrier for a known transmit power for each carrier, allocating a quantity of bits for each carrier within limits imposed by a target bit error rate and the estimated signal to noise ratio, computing a total excess power available for a current allocation of bits, computing additional power that would be required by each carrier to carry additional bits, and allocating the total excess power based on the computation of additional power required by each carrier to carry additional bits. The computation of additional power needed may be performed by computing the additional gain necessary to carry additional bits or by computing the additional excess power necessary to carry additional bits.

Rate control apparatus and method for real-time video communication

Abstract: A rate control apparatus for real-time video communication includes: an initialization unit for setting an initial value required for rate control according to a transmission speed and the number of input frames; a target bit calculation unit for obtaining the target number of encoding bits, maximum allowable number of bits, and minimum allowable number of bits in consideration of a buffer state and a transmission speed; a rate control and encoder unit for executing rate control and encoding using the maximum allowable number of bits and the minimum allowable number of bits; a stuffing control unit for comparing the size of a bit stream from the rate control and encoding unit with the target number of encoding bits from the target bit calculation unit for thereby outputting stuffing bits; a buffering unit for storing a combination of the bit stream from the rate control encoding unit and the stuffing bits from the stuffing control unit for thereby outputting them to the target bit calculation unit; a frame skip unit for outputting a frame skip signal according to the buffer occupied state signal from the buffering unit; and a control logic unit for controlling an encoding process of each of the above elements and determining whether or not the next input frame is encoded according to the frame skip signal from the frame skip unit.

Partial redundancy encoding of speech

Abstract: A method and apparatus for partial redundancy encoding of a speech data packet is disclosed. The bits in the speech data packet (10) are sorted in a predetermined error sensitivity characteristic, order, level or degree of importance. Only those bits in the packet (10) which are considered to be most error sensitive are protected by redundant transmission. A partial set of redundant bits of the previously transmitted packets (10) are included with the data bit for current packet (10). The redundant bits are used at the receiver side to reconstruct damaged packets. By using only the most sensitive bits for redundancy, the additional required bandwith may be limited.

A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply

Abstract: A 100 MHz ADC for low-power applications uses a 0.18 μm digital CMOS process. The design achieves 9.4 ENOB for a 50 MHz input at full sampling rate, and consumes a total of 180 mW with 2.5 mm/sup 2/ core in a single 1.8 V power supply.

Convolution decoding terminated by an error detection block code with distributed parity bits

Abstract: An improved encoding technique improves the error detection provided in conventional communication systems. Traditional encoding systems for communication systems often utilize channel-coding in the form of block-coding and convolutional encoding. Block-coding typically utilizes parity bits for error detection. These parity bits are typically placed as a block at the end of the data frame. The present invention provides an improved encoder and decoder which utilize parity bits placed within the data and spread within the data bits for higher reliability.

Method and system for turbo encoding in adsl

Abstract: In a coding system for asymmetric digital subscriber line (ADSL) communications, a method of encoding a sequence of information bits is provided comprising the steps of dividing the information bits (110) into encoding bits (130) and parallel bits (120); encoding the encoding bits to produce encoded bits (160); mapping the encoded bits and the parallel bits into first and second pulse amplitude modulation (PAM) signals; and generating a quadrature amplitude modulation (QAM) signal (170) from these first and second PAM signals. This method overcomes the decoder complexity that would otherwise be required due to the large QAM constellations involved for ADSL communications.

High-resolution ADC operation up to 19.6 GHz clock frequency

Abstract: We have designed, fabricated and tested the second-generation (2G) design of a high-resolution, dynamically programmable analog-to-digital converter (ADC) for radar and communications applications. The ADC chip uses the phase modulation–demodulation architecture and on-chip digital filtering. The 2G ADC design has been substantially enhanced. Both ADC front-end modulator and demodulator, as well as decimation digital filter, have been redesigned for operation at 20 GHz. Test results of this 6000 Josephson junction 2G ADC chip at clock frequencies up to 19.6 GHz are described. These test results were compared to the results of ADC functional simulation using MATLAB.

Carrier-dependent dithering for analog-to-digital conversion

Abstract: An analog-to-digital converter (100) (ADC) includes a dither signal generator (107) configured to add an analog dither signal (114) to the analog input signal (102) of the ADC prior to digitization (i.e., quantization). The amplitude of the either signal is selected based upon the power levels of one or more carriers present in the bandwidth for which the ADC is designed to operate. Addition of the dither signal to the input signal in the analog domain reduces quantization noise such as conversion spurs that result from non-linearities in the ADC transfer function.

Frame synchronization method and system

Abstract: A method and system for frame synchronization in a digital data transmission. A synchronization word is selected that is suitable for good correlation in a receiver detector. Either traffic bits or control bits are interleaved within the synchronization word in a predetermined pattern that is fixed for consecutive frames. The position of the sync word is varied from frame-to-frame. Also, the interleaved bits that are either traffic or control bits varies substantially between consecutive frames.

InP-HBT optoelectronic integrated circuits for photonic analog-to-digital conversion

Abstract: A monolithically integrated optical receiver and a 4-bit flash analog-to-digital converter, all in InP HBT technology, have been implemented. The optical receiver converts an incoming optical pulse train into an electronic signal and is functional up to 10 Gsps. The electronic input 4-bit flash ADC achieves 3.8 effective bits at low input frequency and 2.1 effective bits at Nyquist input frequency when sampled at 10 Gsps. A 4-bit version has 2.8 effective bits at low-input frequency and 2.4 effective bits at Nyquist-input frequency when sampled at 10 Gsps. The 4-bit ADC operates up to 18 Gsps where it has 1.7 effective bits at Nyquist-input frequency.

Variable dynamic range analog-to-digital converter

Abstract: Provided is an analog-to-digital converter that includes a first analog-to-digital conversion (ADC) stage connected to input a first analog signal and a second ADC stage connected to input a second analog signal produced by the first ADC stage. A tone detector enables the second ADC stage from a disabled state when a first condition indicating the presence of a high-level interference tone is satisfied and disables the second ADC stage from an enabled state when a second condition indicating the absence of a high-level interference tone is satisfied.

Ramp testing of ADC transition levels using finite resolution ramps

Abstract: A common strategy for testing ADCs involves applying a ramp waveform to the converter, collecting a histogram of the converter response, and computing the transition levels. High resolution converters require high resolution sources with tight linearity to implement the test. A method is described which excites the ADC with an imperfect ramp whose resolution is comparable to the ADC noise. The transfer characteristics are extrapolated from the resultant response. The method recovers the threshold value with the same number of samples that are required by the classic ramp histogram.

Soft bit computation for a reduced state equalizer

Abstract: Method and apparatus for soft bit computation with a reduced state equalizer. The method assures that the number of states in the equalizer is reduced to obtain acceptable complexity, while also ensuring that soft bit computation is performed for substantially all bits. The method involves computing a first set of soft bits from bits transmitted in a received signal, using a reduced-state trellis with finite non-zero delay, calculating hard decisions in response to the received signal, and also ensuring that substantially all soft bits are computed by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits. Furthermore, the hard decisions are used to compute the second set.

Square-and-multiply exponent processor

Abstract: Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.

Forward power control determination in spread spectrum communications systems

Abstract: A spread spectrum communications system where power control mitigates received signal fluctuations. An implementation is described for forward power control wherein received data is checked for errors. Where an error is detected energy levels of the power control bits and traffic bits are determined. The energy level of the power control bits is compared against a first predetermined threshold wherein if the energy level of the power control bits is less than the first predetermined threshold an increased in forward power is requested. Otherwise, the energy level of the traffic bits are compared against a second predetermined threshold wherein if the energy level of the traffic bits is less than the second predetermined threshold a decrease in forward power is requested. Otherwise an increase is requested.

An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique

Abstract: An 8-bit 10-MS/s folding and interpolating analog-to-digital converter (ADC) using the continuous-time auto-zero technique is presented. Compared with the conventional architecture, it can improve the nonlinear errors and enhance the signal-to-noise-and-distortion ratio (SNDR). Both architectures have been fabricated on the same die of a 0.35-/spl mu/m DPDM CMOS process and measured under the same conditions with a 2.7-V supply voltage and 10-MHz sampling rate. The continuous-time auto-zero architecture shows an ENOB of 7.7 bits while the conventional one shows 5.8 bits.

Receiver deskewing of multiple source synchronous bits from a parallel bus

Abstract: A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.

High frequency range four bit prefetch output data path

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

A photonic wideband analog-to-digital converter

Abstract: This paper provides a comprehensive understanding of a novel photonic high-speed analog-to-digital converter (ADC) approach and its anticipated performance. Compelling analytic models, experimental data, and simulation results show that the system will achieve the goal of developing an ADC with a resolution on the order of 12 bits and with conversion speeds in excess of 10 GS/s.

Method and apparatus for adaptively coding a data signal

Abstract: A method and apparatus for transmitting an input data signal over an information channel. The input data signal comprises a sequence of data blocks. A puncture coded signal is generated for each data block in the sequence of data blocks. The total number of bits in the puncture coded signal is equal to the number of bits in a particular data block plus additional error correcting bits used to perform error correction at a receiver. The number of error correcting bits is adaptively adjusted for each data block in response to a channel quality measure for the information channel.

Transmission method and system with unequal error protection

Abstract: A method for prioritizing protection in the symbol mapping of selected information includes the steps of supplying information bits and overhead bits. Interleaving the information bits and overhead bits to supply a plurality of interleaved data blocks. And selectively mapping the plurality of interleaved data blocks into a modulation symbol.

A low-power variable resolution analog-to-digital converter

Abstract: A method to reduce the power dissipation of analog-to-digital converters (ADCs) in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this paper, we present an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is, a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Our ADC is implemented in a 0.35 /spl mu/m CMOS-technology with a-single-ended 3.3 V power supply. This ADC implementation has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average, of 10 percent less power when the resolution-is decreased by two bits.

Method of converting bits of optical disk, demodulating method and apparatus

Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits. The first and second output bits are used for designating an address of a demodulating reference table.

Method and system for powering down an analog-to-digital converter into a sleep mode

Abstract: A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.

Low weight data encoding for minimal power delivery impact

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Signal clipping circuit for switched capacitor sigma delta analog to digital converters

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

8-psk transmission filtering using reduced look-up tables

Abstract: A method for generating a premodulation-filtered modulation waveform having a real part and an imaginary part for transmitting octal symbols uses a reduced lookup table (208). Succesive octal symbols, each comprising three information bits (B1, B2, B3), are input to a logic unit (202). The logic unit forms a first derived bit by combining the first and third information bits and a second derived bit by combining the second and third information bits. The first and second information bits, along with the first and second derived bits, are delayed in respective L-bit shift registers (204). The bit sequences in the L-bit shift registers are used to determine a corresponding filtered waveform segment for each bit sequence (208). The waveform segments corresponding to the delayed first information bits and the delayed first derived bits are combined to obtain a segment of said imaginary waveform part (214b). The waveform segments corresponding to the delayed second information bits and delayed second derived bits are combined to obtain a segment of said real waveform part (214a).

Wireless communications with efficient channel coding

Abstract: A data encoding algorithm can be used (120) to generate overhead bits from original data bits, and the original data bits and overhead bits can be transmitted in respectively separate transmissions (121, 123), if the overhead bits are needed. At the receiver, the original data bits can be determined (125) from the received overhead bits, or the received data bits and the received overhead bits can be combined and decoded together (126) to produce the original data bits.