Showing papers on "Electronic circuit simulation published in 1988"

SPICE: A Guide to Circuit Simulation and Analysis Using PSpice

Abstract: From the Publisher: Revision of best-selling guide to the PSpice circuit simulator by an authoritative author. Provides a "tutorial approach" to using PSpice through graduated examples. Comprehensive coverage of the newest capabilities of this program. Explains the use of "Monte Carlo methods" in PSpice for statistically computing estimates of how circuits will behave with variations in component values. Explains the use of sensitivity calculations and "worst case analysis" in PSpice for discovering the maximum range of circuit performance and the causes of extreme operations. Two-Port Network Analysis, explains derivation and use of two-port parameters, including s-parameters.

Circuit aging simulator (CAS)

Abstract: A circuit aging simulator (CAS) has been developed as part of the BSIM (Berkeley Short-channel Igfet Model) family to predict the effects of hot-electron degradation on MOS circuit behavior Using the SPICE2 of SPICE 3 circuit simulator in a UNIX environment, CAS simulates circuit behavior at a user-specified future time using fresh and DC prestressed BSIM parameter process files CAS is configured in a pre- and postprocessor configuration, so that no modifications to the SPICE code are necessary Iterative simulation to take into account ongoing degradation can also be done through an accompanying UNIX shell scrip program >

A knowledge-based approach to analog IC design

Abstract: A design methodology of expert-system-assisted analog IC design is presented. The expert system provides advice on how to improve the design and the circuit simulator gives quantitative evaluation of the resultant circuit performance. The whole cycle repeats until the desired design goal has been achieved. To explore this design methodology, an expert system has been developed to assist the design of a CMOS operational amplifier. The implementation of the expert system and the associated experimental results are presented. >

Circuit simulation on shared-memory multiprocessors

Abstract: Reports the parallelization on a shared-memory vector multiprocessor of the computationally intensive components of a circuit simulator-matrix assembly (including device model evaluation) and the unstructured sparse linear system solution. A theoretical model is used to predict the performance of the lock-synchronized parallel matrix assembly, and the results are compared to experimental measurements. Alternate approaches to efficient sparse matrix solution are contrasted, highlighting the impact of the matrix representation/access strategy on achievable performance, and medium-grained approach with superior performance is introduced. The techniques developed have been incorporated into a prototype parallel implementation of the production circuit simulator ADVICE on the Alliant FX/8 multiprocessor. >

An accurate and efficient gate level delay calculator for MOS circuits

Abstract: This paper describes an accurate and efficient gate level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. Meanwhile, the high efficient delay characterization is accomplished through a fast timing simulation technique instead of using a circuit simulation or a timing simulation technique, a theorem to reduce a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process.The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The results show that the multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented in this paper.

CODECS: a fixed mixed-level device and circuit simulator

Abstract: Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits >

System for calculating and displaying user-defined output parameters describing behavior of subcircuits of a simulated circuit

Abstract: An improved circuit simulator interface permits a user to define one or more output parameters describing behavior of hierarchically-defined subcircuits of a circuit. The user defines each output parameter by a hierarchial expression including one or more primitive output parameters generated by a simulator when simulating the circuit or other user-defined output parameters describing behavior of subcircuits of the circuit. Once the circuit simulator has simulated the circuit and has generated the primitive output parameter values, the simulator interface responds to a user request to display the value of a selected user-defined output parameter by decomposing the hierarchical parameter expression defining the selected output parameter to an expression combining only primitive parameter values. The simulator interface then evaluates the decomposed expression using primitive parameter values generated by the simulator and displays the result.

Network representations of LIGBT structures for CAD of power integrated circuits

Abstract: To enable computer-aided design (CAD) of power integrated circuits, physical models for lateral high-voltage/power (HV/P) devices, in particular lateral insulated-gate bipolar transistor (LIGBT) structures, are developed and implemented in SPICE. The models are charge-based, and, via regional partitioning, account for the unique features of HV/P devices unaccounted for in conventional equivalent-circuit models. The implementation of the models in the circuit simulator is flexible and allows these features (e.g. multidimensional carrier flow, conductivity modulation, latchup, transcapacitance) to be simulated without having to sacrifice much physics through excessive empiricism. Device measurement of specially designed test structures, supplemented with two-dimensional numerical device simulations, support the modeling methodology and the model parameter extraction. >

XPSim: a MOS VLSI simulator

Abstract: XPSim (formerly known as SuperCrystal), a multirate, event-driven circuit simulator suitable for large MOS VLSI circuits, is described. XPSim incorporates both static and dynamic partitioning of the circuit. Each partitioned subcircuit is numerically solved with a new integration method-the exponential function method. The voltage waveforms produced by this method are piecewise exponentials. Currently, XPSim supports up to a third-order explicit method. Preliminary tests indicate that XPSim exhibits a significant speedup over SPICE while retaining similar accuracy and is able to handle large circuits. >

A mixed-mode analog-digital simulation methodology for full custom designs

Abstract: The authors present a solution to the problem of mixed-mode analog/digital simulation for full custom designs. By efficiently incorporating two specialized simulators-a circuit simulator and a switch-level simulator-in a single computing environment with a common user interface, they have succeeded in simulating full-custom circuits with tightly coupled feedback between the analog and digital portions. The proposed methodology can be applied to a mixed-mode simulation of a purely digital or purely analog circuit in which one portion requires a much higher order of accuracy than the other. >

Challenges in computer-based analysis/simulation and design of power electronic circuits

Abstract: Challenges in the area of analysis/simulation tools for power electronics are outlined, along with a proposal for a hierarchy of tools. It is noted that circuit nonlinearities, wide variations in circuit time constants leading to mathematically stiff circuit description equations, the necessity of being able to obtain the switching instant with high accuracy, and the sensitivity of circuit performance to small parasitics make the task of providing comprehensive simulation very difficult. It is also noted that the design process must be tailored by recognizing that power electronic circuits are different from digital circuits, and hence need a different process. Some essential elements of such a design process are described, and known problems that need to be solved before one can design power electronics circuits completely using computer-based tools are identified. Some of the problems to be addressed in the near future are described. >

Accurate modeling and simulation of parallel interconnection in high-speed integrated circuits

Abstract: The evaluation of the time-domain performance of interconnection lines is becoming increasingly more important in the analysis and design of high-speed integrated circuits. An accurate computer model for n coupled microstrip lines is developed for circuit simulation. Modal analysis is applied to decouple the n coupled line system into n independent lines and the characteristic solution of the lossy transmission line equation is modeled into a simple time-varying equivalent circuit. This model has been implemented into a circuit simulator, called iSMILE, that significantly reduces the model development time. Simulation results on propagation delay times and crosstalks are presented for the case of high-speed GaAs HEMT (high-electron-mobility transistor) integrated circuits. >

Automated parameter extraction and modeling of the MOSFET below threshold

Abstract: A subthreshold model for use in circuit simulation software is described. The model includes representation of nonuniform substrate impurity concentrations and short-channel and narrow-channel effects, while being simple in form. It has been developed in concert with an automated parameter-extraction methodology. The model adds only one parameter to the existing strong inversion model with which it is fully integrated. The accuracy and computational efficiency are suitable for circuit simulation. The results of an extraction carried out on nMOS transistors with channel widths from 70 to 0.9 mu m and channel lengths from 35 to 1.25 mu m over a wide range of bias conditions are described. >

Simulation and modeling for soft recovery of p-i-n rectifiers

Abstract: Soft recovery of fast-switching p-i-n rectifiers is studied using experimental data and a novel coupled device and circuit simulator An analytical model for determining lifetimes is presented and verified by numerical simulations The softness factor is difficult to model analytically; hence simulations are necessary Coupled device and circuit simulations also allow a determination of the magnitude of the inductive voltage spike that appears across the rectifier during an unclamped reverse recovery >

Latency exploitation in circuit simulation by sparse matrix techniques

Abstract: The most important operations for a circuit simulator are component model linearization, updating the network matrix, performing large unsymmetric decomposition on this matrix, and solving the network variables by forward and backward substitution. Methods are presented to keep all these operations localized to the part of the network that is active at the current time point, thus obtaining a considerable reduction in computational effort. The methods depend upon the sparse matrix structure itself, yielding a very effective fine-grained latency use, contrary to methods based on the large blocks specified by the circuit hierarchy. Results obtained from an implementation of the algorithms in a piecewise linear circuit simulator with an implicit multirate integration scheme are presented. >

Simple models for SPICE assist power electronics circuit simulation on PCs

Abstract: The authors show how built-in dependent sources in a circuit analysis program (PSPICE) can be used to model voltage and current source inverter circuits under large-signal operating conditions, including simple feedback. The simplified models proposed reduce the run time and the amount of memory required, allowing the simulation of topologies with increased circuit complexity and long computation intervals. It is shown how user-defined programs can be incorporated to obtain steady-state conditions, schematic capture capability, and input/output data manipulation, while operating under SPICE in a user-friendly environment suited for personal computers. >

SEMINET: further advances in integrated device/circuit simulation for power electronics

Abstract: SEMINET, a power circuit simulator with an integral device simulator, is reviewed, and enhancements are described. Development and simulation of a dynamic insulated-gate-transistor (IGT) model using SEMINET is discussed, and insights into IGT behavior during turn-off are presented. Simulation of an IGT-based half-bridge circuit is described, and the large-signal transient behavior and interaction of the IGT and flyback diode are examined. >

Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor

Abstract: Circuit simulation is a widely used but computationally demanding tool for VLSI design. In this paper, the considerations in achieving performance improvement through parallelization on a shared-memory multiprocessor are addressed. The two main components that comprise the computational bulk of circuit simulation, namely, matrix assembly and sparse matrix solution, raise very different issues in their parallelization. Parallelizing matrix assembly involves using a sequence of lock-synchronized parallel loops. A theoretical prediction of the performance of such loops is developed and this prediction is then compared to actual performance on a variety of circuits. Two approaches to parallel sparse matrix solution are contrasted: 1) an efficient implementation of an earlier proposed fine-grained model that captures parallelism at the elemental-operation level, and 2) a newly proposed medium-grained scheme that represents the computation at the row-operation level. A performance-evaluation framework is developed to interpret measured speedup in terms of various relevant factors. While the fine-grained approach achieves somewhat better load-balancing and also slightly lower scheduling overheads due to judicious task-clustering, the medium-grained approach is shown to be consistently superior for large circuit matrices due to lower operand access costs and better vectorization potential. The techniques developed have been incorporated into a prototype parallel implementation of the production circuit simulator ADVICE on the Alliant FX/8 multiprocessor.

Power MOS FET Models for ``Switching'' Circuits

Abstract: A compact model of the Power VDMOS Transistor compatible with the circuit simulator `` SPICE2'' is described in this article. This model is applied to the simulation of switching circuit with resistive and inductive loads; comparisons with experimental results are presented.

Device and circuit simulation interface for an integrated VLSI design environment

Abstract: MOSGEN, a program that provides efficient interface between the device simulator, PISCES and the circuit simulator SPICE, is described. Algorithms to generate parameters for SPICE built-in MOS transistor models have been developed and incorporated into MOSGEN. Only six PISCES simulation results are required to generate a complete set of SPICE parameters. This interface program, together with SUPREM, PISCES, and SPICE, form an integrated simulation environment for VLSI design. Such an integrated simulation environment facilitates the designers to examine just how a microscopic fabrication variable, such as implantation dose, affects final device and circuit performance as well as product yield. >

PC software for electronic circuit design in printed circuit form

Abstract: The advent of inexpensive, powerful, reliable and easily accessible microcomputers is changing the design of both electronic circuits and electronic systems. It is now well recognised that CAD tools can be used to speed up circuit design in the engineering process. This paper provides an overview of commercially available personal computer based circuit analysis and design packages, and reports progress made in the development of a design package called AJITA, used for rapidly producing electronic circuit designs, in printed circuit form, from direct specification in terms of functional building blocks.

Models for circuit simulators to analyze crosstalk and radiation into wires

Abstract: A procedure is presented for analyzing digital pulse distortion, unintentional electromagnetic coupling (crosstalk), and the pickup of an incident electromagnetic field by transmission lines, using suitable models for commercial circuit simulators such as ASTAP, SPICE, and SABER. Transmission-line effects and field-to-cable coupling are represented in the circuit simulator by voltage sources for AC and transient analysis. AC computations can be done with distributed parameters, instead of lumped parameters, producing good accuracy and saving time. This type of analysis is very useful in the case of a periodic signal and linear loads. A description of these models and a comparison with experimental results are given. >

Thermal modelling using ASTEC3 software

Abstract: This paper describes the application of ASTEC3, a general purpose analogue electronic circuit simulation package, to the analysis of thermal properties of given structures. The modelling of each system is considered for both conduction and convection mechanisms, radiation being assumed to play a very minor role in heat dissipation from most electrical circuits. A procedure is given for the modelling of one-, two- and three-dimensional thermal problems which is then used for the simulation of relatively simple examples. The results obtained with ASTEC3 are compared with results determined by using more traditional and independent techniques.

SUGAR: an event driven circuit simulator

Abstract: The SUGAR algorithm is presented which outperforms conventional circuit simulation techniques on large circuits by fully exploiting latency. The event-driven technology does not have the convergence problems associated with SPICE-like algorithms. Examples were presented that show the accuracy of the results by comparison with SPICE, and show the improvement in CPU usage for simple MOS circuits containing a high degree of latency. >

Design Methodologies for Nonlinear Circuit Simulation and Optimization

Abstract: This paper illustrates the methodology for designing a nonlinear circuit using state-of-the-art CAD tools applied to several examples of FET circuits The parameters needed for characterization of the (nonlinear) FET are extracted using RoMPE, a parameter extraction program based on gradient optimizers which have been enhanced by adjoint sensitivity calculations to provide exact gradients Measured DC and small-signal S-parameter data are simultaneously fitted to a modified Materka FET model Simultaneous fitting of the data to both DC and AC parameters is essential to preserve the implicit dependence of the small-signal model parameters upon the bias Microwave Harmonica, a harmonic-balance based nonlinear circuit simulator, is then used with the model parameters to design a single-gate FET mixer circuit The use of an optimizer to improve the conversion gain and spectral purity of the mixer, and its use in the design of oscillator circuits is also demonstrated

A circuit simulator based on the waveform-relaxation method using selective overlapped partition and classified latencies

Abstract: Several techniques for improving simulation costs in the waveform relaxation method are discussed. In the circuit partitioner field, selective overlapped partition and duplication depth ideas are proposed. For the circuit simulation part, several modifications to the conventional simulator are demonstrated and classified latencies proposed. Experimental simulations are compared with results obtained from SPICE2. The results indicate conclusively that, if the circuit size is over one thousand, SUPER-SPICE is more cost-effective than SPICE2. >

A systematic approach to simulate power electronic circuits on digital computers

Abstract: It is shown that switching devices can be modeled as variable inductors which are controlled by independent off-on controllers. As the topology of the circuit changes due to closing and opening of the switches, it is shown that only one set of linear state-space equations is needed to characterize a power electronic circuit mathematically. Therefore, a system of converters with a large number of randomly variable-switched topologies can be simulated methodically. Based on this approach, the digital simulation of a resonant inverter is presented. >

Convergence properties of relaxation methods in the DC analysis of large MOS circuits

Abstract: A novel approach, formulated as a special case of transient analysis is proposed for the DC analysis problem. This makes it possible to rely on a common background in both instances. Simulation results for the DC analysis of MOS circuits are compared with those obtained by the standard circuit simulator SPICE. >