Showing papers on "FET amplifier published in 2005"

Optimum operation of asymmetrical-cells-based linear Doherty power Amplifiers-uneven power drive and power matching

Abstract: We developed a Doherty amplifier with uneven input drive and optimized individual matching for the carrier and peaking cells. In the proposed amplifier, higher input power is delivered to the peaking cell rather than the carrier cell for optimized linear power operation, especially for appropriate load modulation. Both cells are matched differently to further optimize the performance. We analyzed the efficiency of the proposed amplifier as a function of the input drive ratio for the two cells. To interpret the linearity related to the load modulation and harmonic cancellation mechanisms, we simulated the third-order intermodulation amplitude and phase of each cell of the proposed amplifier. For verification, we implemented the asymmetric power amplifier with uneven drive and optimized power matching using Motorola's MRF281SR1 LDMOSFET with a 4-W peak envelope power. For a 2.14-GHz forward-link wireless code-division multiple-access signal, the measured drain efficiency of the amplifier is 40%, and the measured average output power is 33 dBm at an adjacent channel leakage ratio (ACLR) of -35 dBc, while those of the comparable class-AB amplifier are 21% and 30.6 dBm at the same ACLR level, respectively.

A highly efficient Doherty feedforward linear power amplifier for W-CDMA base-station applications

Abstract: This paper presents a RF high-power Doherty amplifier for improving the efficiency of a 30-W feedforward linear amplifier used in wide-band code-division multiple-access (W-CDMA) base-station applications. A high-power Doherty amplifier using a single push-pull LDMOS field-effect transistor is proposed as the main amplifier of a feedforward linear amplifier. The peaking amplifier's compensation line and gate bias effects are analyzed at the 6-dB backoff point. From the experimental results of a forward-link one-carrier W-CDMA, a 2.2% power-added efficiency improvement at an adjacent channel leakage power ratio linearity of -60 dBc is achieved in comparison to a conventional feedforward class-AB amplifier.

Power stealing for a thermostat using a TRIAC with FET control

Abstract: An electronic thermostat circuit has improved power stealing for controlling an AC control device. The circuit comprises a source of AC control power coupled to an electronic switch means having an electronic switch means control input. The electronic switch means controls the AC control device. The diode bridge controls the electronic switch means by a DC control signal applied to the diode bridge means DC connection. The amplifier means has an amplifier input for controlling the state of the amplifier and an amplifier output for generating the DC control signal. An isolated gate FET means is electrically coupled to the amplifier input for controlling the state of the amplifier. The isolated gate FET means is powered by the current derived from the source of AC control power by power stealing. The digital signal controls the state of the AC control.

Linearity optimization of a high power Doherty amplifier based on post-distortion compensation

Abstract: The linearity of a 30-W high-power Doherty amplifier is optimized using post-distortion compensation. A balanced high-power Doherty amplifier using two push-pull laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) is linearized by optimum adjustment of the peaking compensation line, shunt capacitors, and gate biases. The measured results of an optimized Doherty amplifier for a four-carrier wideband code division multiple access (W-CDMA) signal, achieved -43 dBc adjacent channel leakage ratio (ACLR) at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2dB and 6.5dB in comparison to the Doherty amplifier before optimization and a ClassAB amplifier, respectively.

Low noise and high gain low noise amplifier

Abstract: A high-gain and low-noise low noise amplifier (LNA) includes a differential amplifier, a pre-amplifier and an impedance matching network. The differential amplifier includes a first input end and a second input end coupled to a grounded impedance. The pre-amplifier includes an input end and an output end. The impedance matching network is coupled between the first input end of the differential amplifier and the output end of the pre-amplifier for matching an input impedance of the differential amplifier with an output impedance of the pre-amplifier. The present invention provides a LNA structure with low noise, high gain and easy design.

Power amplifier utilizing quadrature hybrid for power dividing, combining and impedance matching

Abstract: A power amplifier includes a quadrature hybrid and input impedance matching network. The power amplifier also includes at least one amplifier that includes an output electrode, and a quadrature hybrid and output impedance matching network. The quadrature hybrid and input impedance matching network exhibits a low pass frequency response.

A handset power amplifier with high efficiency at a low level using load-modulation technique

Abstract: A new monolithic-microwave integrated-circuit power amplifier for cellular handsets has been implemented using the load-modulation concept of the Doherty amplifier, which has a high efficiency at a low power level. In order to get a compact module, the /spl lambda//4 transmission line for the load modulation is replaced by a passive high-pass /spl pi/-network, and the load-modulation circuit is also modified to function as a power-matching circuit of the main amplifier. The amplifier has two modes of operation, low- and high-power modes, controlled by a control voltage. At the high power mode, both the main and auxiliary amplifiers are operational and, at the low power mode, only the main amplifier generates output power enhancing the efficiency. For the code-division multiple-access environment, the amplifier at the low-power mode provides power-added efficiency (PAE) of 39.8% and an adjacent channel power ratio (ACPR) less than 49.8 dBc at 23.1 dBm, and the high-power mode PAE of 37.9% and ACPR of 46.4 dBc at 28 dBm. The efficiency is improved by approximately 18.8% at P/sub out/=23 dBm by the load-modulation technique. For the advanced mobile phone system-mode operation, the amplifier delivers 26.1 dBm with PAE of 53% and 30.8 dBm with 48.7% at the low and high modes, respectively.

A proportional to absolute temperature voltage circuit

Abstract: A voltage circuit including a first amplifier having first and second inputs and having an output driving a current mirror circuit is provided. Outputs from the current mirror circuit drive first and second transistors which are coupled to the first and second input of the amplifier respectively. The base of the first transistor is coupled to the second input of the amplifier and the collector of the 10 first transistor is coupled to the first input of the amplifier such that the amplifier keeps the base and collector of the first transistor at the same potential. The first and second transistors are adapted to operate at different current densities such that a difference in base emitter voltages between the first and second transistors may be generated across a resistive load coupled to the second 15 transistor, the difference in base emitter voltages being a PTAT voltage.

Transmitting apparatus and radio communication apparatus

Abstract: A transmitting apparatus 100 operates a high-frequency power amplifier 105 as a nonlinear amplifier in a first mode, and operates high-frequency power amplifier 105 as a linear amplifier in a second mode. When high-frequency power amplifier 105 is operated as a nonlinear amplifier, the input level of high-frequency power amplifier 105 is varied by a variable gain amplifier 107 in accordance with the average output power of a transmit signal. Transmitting apparatus 100 is also provided with a compensation table 121 for reducing error in high-frequency power amplifier 105 mode switching operations.

Level detector for optical receivers

Abstract: An apparatus and method for detecting an output power level of an optical receiver, in order to hold output signal levels constant over changing input optical levels. A photodetector detects an optical signal, and a current from the photodetector is applied an amplifier. The amplifier may be either a differential trans-impedance amplifier, or a dual trans-impedance amplifier coupled to a differential output amplifier. An output of the amplifier is applied to a signal detector, wherein an output signal of the signal detector is an indication of an output power level of the optical receiver.

Power amplifier with stabilising network

Abstract: A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies.

Power amplifier module for wireless communication devices

Abstract: A power amplifier module for amplifying radio frequency signals includes a radio frequency power amplifier including one or more semiconductor transistors, adapted to receive an input radio frequency signal and power control signals, and to output an amplified radio frequency signal. The power amplifier module is integrated with input and output impedance matching networks and a power sensor that is adapted to receive the amplified radio frequency signal and to output a signal indicating the power output level of the power amplifier module. The power amplifier module also includes control logic in accordance to at least one of the qualities and the power level of the amplified radio frequency signal.

Gain boosting for tuned differential LC circuits

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Small-sized on-chip CMOS power amplifier having improved efficiency

Abstract: A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

Amplifier circuit for capacitive transducers

Abstract: An amplifier circuit for capacitive transducers, such as miniature electret or condenser microphones, wherein the amplifier circuit comprises bias control means adapted to improve settling of the amplifier circuit. Another aspect of the invention relates to a miniature condenser microphone and a monolithic integrated circuit comprising an amplifier circuit according to the present invention. The present invention provides amplifier circuits of improved performance by resolving traditionally conflicting requirements of maintaining a large input resistance of the amplifier circuit to optimize its noise performance and provide fast settling of the amplifier circuit.

A subharmonic self-oscillating mixer using substrate integrated waveguide cavity for millimeter-wave application

Abstract: A low-cost, compact, subharmonic self-oscillating mixer integrated with antenna is presented and demonstrated at 30GHz. This novel configuration makes use of substrate integrated waveguide (SIW) cavity as a resonator in the feedback loop to stabilize the fundamental oscillating frequency. This allows the possibility of building a complete planar receiver, with improved phase noise, as an integrated front-end for millimeter wave systems such as radar and wireless sensor network. It is also an attractive structure for MMIC design. A convenient method free from FET amplifier design is proposed in the work for this kind of self-oscillating mixer, which can also be applied in SIW oscillator design. The circuit, implemented as a down-converter, exhibits an average conversion loss of 8.6dB, and an IF phase noise of -86dBc/Hz at 100-kHz offset. The effects of DC variation on the oscillating frequency and the output P/sub 1dB/ gain compression are measured and demonstrated.

Dual-band GaAs FET power amplifier with two-frequency matching circuits

Abstract: A dual-band GaAs FET power amplifier with the two-frequency lumped-element matching circuits is designed using the low-pass Chebyshev-form impedance transformer design method An 800/1500MHz 1Watt-class GaAs FET amplifier is fabricated and the experimental results show the saturated output powers of 309dBm and 282dBm with the power added-efficiencies of 516% and 519% at 800MHz and 1500MHz, respectively The fabricated circuit size is 24mm by 28mm The presented design approach enables a simple dual-band power amplifier with superior performance and small size

Power amplifier for amplifying high-frequency (H.F.) signals

Abstract: An H.F. power amplifier is disclosed having a plurality of branches (10, 11, 12) switched in parallel. Each branch comprises a plurality of amplifier elements (T1,…, T4) switched in series. Resistors (R2,…, R5) enable the voltage (UlDS) applied to the amplifier elements (T1,…, T4) to be set at a fraction of a supply voltage (Ud) applied to the branches (10, 11, 12). Capacitors (C2,…, C4) are used to adjust the source impedance of the amplifier elements (T2,…, T4). In order to prevent the gate-drain voltage (UlGD) from exceeding the breakdown voltage of an amplifier element (T1,…, T4) and damaging the amplifier element (T1,…, T4), a limiting path (7) is connected according to the invention between the gate terminal (G) and the drain terminal (D) of the amplifier element (T1,…, T4), the limiting path (7) being switchable between a conducting state and a blocking state depending on the gate-drain voltage (UlGD).

Metamorphic 94 GHz power amplifier MMICs

Abstract: In this paper, we present the development of two 94 GHz power amplifier MMICs for use in high-resolution synthetic aperture radar (SAR) systems. The amplifier circuits have been realized using a 0.1 /spl mu/m InAlAs/InGaAs based depletion type metamorphic high electron mobility transistor (MHEMT) technology in combination with coplanar circuit topology and dual-gate transistors, thus leading to an excellent power and gain performance at millimeter-wave frequencies. The realized two-stage driver amplifier (MPA) MMIC exhibited a small-signal gain of 16 dB and a saturated output power of 20.5 dBm at 94 GHz with a total gate width of 0.72 mm in the output stage. The two-stage high power amplifier (HPA) circuit achieved a linear gain of 10 dB and a saturated output power of 23.3 dBm with a total output periphery of 1.44 mm.

Impedance matching techiques for multi-band or wideband RF amplifiers and associated amplifier designs

Abstract: Multi-band or wideband impedance matching in RF amplifiers is disclosed, using variable negative feedback. The feedback is provided by variable impedance connected between the input and output terminals of an inverting amplifier, which may be single-ended, or differential. The variable impedance is used in conjunction with a fixed input impedance matching network to tune the variable impedance to different frequencies. The variable impedance feedback can also be used for gain control, and has the added benefit of stabilizing the amplifier. Both multi-band and wideband amplification can be optimized through the use of the disclosed circuitry and techniques. Use of an output impedance matching network in conjunction with the RF amplifier is optional.

Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit

Abstract: An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage through a first impedance circuit. A p-type transistor of the circuit has a source coupled to the source of the n-type transistor, a gate coupled to a second bias voltage, and a drain coupled to a second supply voltage through a second impedance circuit. A first differential input is coupled to the gate of the n-type transistor through a first capacitor and to the gate of the p-type transistor through a second capacitor. A second differential input is coupled to the sources of the n-type and the p-type transistors. A third capacitor has a first end coupled to the drain of the n-type transistor, and a fourth capacitor has a first end coupled to the drain of the p-type transistor and a second end coupled to a second end of the third capacitor. An output of the amplifier circuit is provided at the second ends of the third and the fourth capacitors. The n-type transistor and the first impedance circuit serve as a common-source amplifier for a signal at the first differential input and as a common-gate amplifier for the signal at the second differential input. Similarly, the p-type transistor and the second impedance circuit serve as a common-source amplifier for the signal at the first differential input and as a common-gate amplifier for the signal at the second differential input.

Simple two-electrode biosignal amplifier.

Abstract: A simple, cost effective circuit for a two-electrode non-differential biopoten- tial amplifier is proposed. It uses a "virtual ground" transimpedance amplifier and a par- allel RC network for input common mode current equalisation, while the signal input impedance preserves its high value. With this innovative interface circuit, a simple non-inverting amplifier fully emulates high CMRR differential. The amplifier equivalent CMRR (typical range from 70-100 dB) is equal to the open loop gain of the operational amplifier used in the transimpedance interface stage. The circuit has very simple struc- ture and utilises a small number of popular components. The amplifier is intended for use in various two-electrode applications, such as Holter-type monitors, defibrillators, ECG monitors, biotelemetry devices etc.

C-band Single-Chip GaN-FET Power Amplifiers with 60-W Output Power

Abstract: A C-band high power amplifier was successfully developed with a single-chip GaN-based FET. At 4.0GHz, the fabricated 24-mm wide FET delivers 62 W and 156W under CW and pulsed operating conditions, respectively with a universal test fixture. The internal matching circuit was designed to be set up in a half-size package as compared to that for GaAs-based comparable-power-level amplifiers. The developed GaN-FET amplifier with 24-mm gate periphery delivers a 61W output power with 10.2dB linear gain and 42% power-added efficiency under CW operating conditions. To the best of our knowledge, this is the highest CW output power achieved from a single-chip FET power amplifier at C-band.

370 W output power GaN-FET amplifier for W-CDMA cellular base stations

Abstract: A single-ended amplifier using small packaged GaN-FETs exhibits a record 2.14 GHz W-CDMA output power. The amplifier, composed of paralleled 48 mm gate periphery FET die, delivers a peak saturated output power of 371 W with a linear gain of 11.2 dB at a drain voltage of 45 V under 2.14 GHz 3GPP W-CDMA signal input. The output power density (output power/package size) of 1.1 W/mm2 is twice as high as that of the existing over 300 W GaAs-FET amplifiers. A low 5 MHz offset ACLR of −36 dBc with a drain efficiency of 24% is also obtained at 8 dB power back off from the saturated output power.

High frequency power amplifier module

Abstract: For use in an amplifier configuration including a high-power amplifier and a low-power amplifier which are always interconnected in terms of high frequencies and between which switching is made using no switches, a highly stable high-frequency power amplifier module with high isolation between the amplifiers is provided. To reduce wrapping around from a low-power amplifier section in an activated state to a high-power amplifier section in a deactivated state or from the high-power amplifier section in an activated state to the low-power amplifier section in a deactivated state, an input matching circuit having high isolation characteristics is included in an input matching circuit portion which does not have much to do with amplifier efficiency. Switching of each of the amplifier sections between an activated state and a deactivated state is effected by control using bias input terminals.

Integrated booster amplifier

Abstract: An amplifier is provided. The amplifier comprises an H-bridge with two halves. A capacitor and two inductors are coupled to the H-bridge. Each inductor, a half of the H-bridge, and the capacitor are configured as a boost converter.

Creating High Voltage FETs with Low Voltage Process

Abstract: An integrated circuit (IC) includes a high voltage first-conductivity type field effect transistor (HV-first-conductivity FET) and a high voltage second-type field effect transistor (HV-second-conductivity FET). The HV first-conductivity FET has a second-conductivity-well and a field oxide formed over the second-conductivity-well to define an active area. A first-conductivity-well is formed in at least a portion of the active area, wherein the first-conductivity-well is formed to have the capability to operate as a first-conductivity-drift portion of the HV-first-conductivity FET. The HV second-conductivity FET has a first-conductivity-well and a field oxide formed over the first-conductivity-well to define an active area. A channel stop region I s formed in at least a portion of the active area, wherein the channel stop region is formed to have the capability to operate as second-conductivity-drift portions of the HV-second-conductivity FET.

A 50 W LDMOS current mode 1800 MHz class-D power amplifier

Abstract: This paper presents a 50W current mode class-D power amplifier for the 1800 MHz frequency band using commercial LDMOS-FET. The amplifier is based on a switching mode push-pull structure which utilizes a shunt harmonic termination circuit and a 180q balun output transformer. The output termination topology is applied for minimizing power losses due to the existing parasitic capacitance of the LDMOS- FET power devices. From the measured results, a drain efficiency of 63 % at 47 dBm output power was achieved.

A low-noise and wide-band ac boosting current-to-voltage amplifier for scanning tunneling microscopy

Abstract: A compact, fast, and low-noise current-to-voltage amplifier is built for scanning tunneling microscopy. The amplifier consists of two amplification stages. The first stage performs low-noise transimpedance amplification by using a high performance FET operational amplifier together with a high-ohm feedback resistor of 1GΩ and a parallel trimming capacitor. The ac boosting amplifier in the second stage recovers the higher frequency above the 3dB cutoff of the first stage to extend the maximum bandwidth up to 100kHz. This two-stage current-to-voltage amplifier shows a low current noise below sub-pA rms when tuned to have the bandwidth of around 1kHz. It also guarantees stable frequency response in the presence of 1000pF input capacitance.

Low noise AC coupled amplifier with low band-pass corner and low power

Abstract: A low noise AC coupled amplifier having transistors sharing bias currents, and having a low band-pass corner frequency and consuming low power. The amplifier may be used in a magneto-resistive (MR) preamplifier to amplify a response from a MR sensor. Bipolar and MOS transistors are used in the front end, utilizing the advantages of each transistor type to achieve low noise as well as low band-pass corner. The amplifier has a modified structure achieving lower power by using a PNP transistor instead of an NPN transistor.