Showing papers on "Firmware published in 1998"

Data transaction assembly server

Abstract: A form driven operating system which permits dynamic reconfiguration of any host processor into a virtual machine supporting any of a number of operating system independent applications. A data transaction assembly server (TAS 18) downloads menus and forms unique to each application requiring data to be input for processing. The data transactions and forms are exchanged between the TAS (18) and a remote processor in real-time so that virtually any operating system independent software application may be implemented in which a form driven operating system may be used to facilitate input, data input into the form may be processed, returned as a data stream, and displayed to the user. The TAS requires a flash PROM (95) for storing the TAS control firmware, a RAM (96) for storing the data streams making up the forms and menus, and a small RAM (97) which operates as an input/output transaction buffer for storing the data streams of the template and the user replies to the prompts during assembly of a data transaction. The transaction entry device (12) including the TAS (18) may be integrated with a telephone and accessed via conventional data input devices.

Method for BIOS authentication prior to BIOS execution

Abstract: A cryptographic device is implemented in communication with a host processor to prevent the host processor from performing a standard boot-up procedure until a basic input output system (BIOS) code is authenticated. This is accomplished by a cryptographic device which is addressed by the host processor during execution of a first instruction following a power-up reset. The cryptographic device includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a memory to contain firmware and a root certification key. The second IC device includes logic circuitry to execute a software code to authenticate the BIOS code before permitting execution of the BIOS code by the host processor.

Disk drive having data-guarding firmware

Abstract: A disk drive includes a disk defining a multiplicity of sectors. A method of operating the disk drive includes a step of providing a firmware-controlled state machine which can be in any of a plurality of states including an off-line in-progress state. While the state machine is in the off-line in progress state, the drive performs a firmware-controlled scan of the multiplicity of sectors. While performing the firmware-controlled scan, the drive identifies and repairs a marginal sector.

Authorization firmware for conducting transactions with an electronic transaction system and methods therefor

Abstract: A computer configured to authenticate a user to an electronic transaction system is disclosed. The computer includes a central processing unit and electronic authorization firmware disposed within the computer and in electronic communication with the central processing unit. The electronic authorization firmware includes a non-volatile memory circuit configured to store at least one of a user private key and user identification data and a firmware identification data. The electronic authorization firmware further includes decryption logic circuitry disposed between the non-volatile memory circuit and the electronic transaction system. The decryption logic circuitry is configured to prevent unauthorized access to at least one of the user private key and the user identification data in the non-volatile memory circuit. The electronic authorization firmware also includes encryption logic circuit coupled to the electronic transaction system and configured to transmit digital data encrypted using the user private key for transmission to the electronic transaction system. The digital data authenticates the user to the electronic transaction system, wherein the non-volatile memory is inaccessible by the central processing unit without traversing the decryption logic circuitry.

Firmware upgrade method for wireless communications device, and method for supporting firmware upgrade by base station

Abstract: A method for upgrading firmware (F/W) of a wireless communications device is capable of updating F/W at all times through a simple process by transferring, directly and wirelessly, new firmware required for the wireless communications device from a base station. In the F/W upgrade method, a user's identification of the wireless communications device and information required for F/W upgrade are transferred to the corresponding base station, and the current mode of the wireless communications device is converted into an F/W upgrade mode according to whether or not the corresponding base station allows the upgrade, which is determined based on the transferred information. Then, F/W of the wireless communications device is wirelessly upgraded by the corresponding base station.

System and method for applying initialization power to SCSI devices

Abstract: A computer is provided having a SCSI subsystem and multiple SCSI devices connected to that subsystem. Those devices involve electromechanical motors which require a greater amount of current during times needed to spin-up the motor-driven devices to a steady-state velocity than current needed to maintain that velocity. Each SCSI device includes an inquiry page indicating attributes of that device and whether that device supports fast spin-up. If a device supports fast spin-up, firmware within the computer is activated during ROM POST operations forwards a command to begin a spin-up operation on one SCSI device before the prior device has completed its spin-up operation. In this manner devices which support fast spin-up can concurrently spin-up to their constant velocity value so as to minimize the initialization process of the computer system subsequent to reset or boot-up of the system. Any devices which do not support fast spin-up, as indicated in their inquiry page, can thereafter be spun-up in sequence one after the other to complete the boot-up process for the entire computer system employing numerous SCSI disk drives or tape back-up units.

Method of communication between firmware written for different instruction set architectures

Abstract: A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or more legacy routines through a first dispatcher. The native firmware nodule includes a prologue routine. The prolog routine locates the data structure associated with the legacy firmware module and initializes it to provide a link between the first and second firmware modules.

Method of updating firmware without affecting initialization information

Abstract: A firmware controlled device saves status and configuration information in a separate portion of memory that is not affected by a firmware update. In addition, information that may change during a firmware update, and may need to remain constant, is saved in the separate portion of memory that is not affected by a firmware update. In a first example embodiment, a reset process for the firmware controlled device is divided into two portions. In a first portion of the device reset process, the contents of the separate portion of memory are updated, either from firmware or by interaction with other devices. In a second portion of the device reset process, all other reset functions are performed. The first portion of the reset process is performed only during a power-on reset, or in response to an overall system reset. In particular, the first portion of the device reset process is not performed after a firmware update. In the second example embodiment, data that needs to remain constant are copied to the separate portion of memory as part of a firmware update process. Then, as part of a reset process, the device checks to see if a firmware update has occurred. If a firmware update has occurred, the data in the separate portion of memory are copied to the appropriate destinations, and the data in the separate portion of memory are cleared. As a result, for either example embodiment, the contents of the separate portion of memory are not disturbed during or after a firmware update, and a system reboot is not necessary after a device firmware update.

Advanced boot sequence for an +86 computer system that maintains expansion card device compatibility

Abstract: An ×86 based computer system that implements a firmware based boot process without an ×86 BIOS that supports expansion devices coupled to the computer system, wherein the expansion devices include their own respective BIOS extensions. The computer system includes an ×86 processor coupled to a volatile memory and a non-volatile memory via a bus. The non-volatile memory includes firmware which when executed by the processor cause the computer system to implement the boot process. The firmware initializes device drivers for the computer system and initializes an application programming interface for the device drivers. The firmware then initializes a compatibility component for interfacing with the device drivers, wherein the compatibility component is operable for translating accesses by a first software application to an ×86 BIOS into corresponding accesses to the device drivers. This enables the first software application to execute on the computer system by using the compatibility component while a second software application is able to execute on the computer system by accessing the application programming interface directly. The firmware then runs an expansion device BIOS extension from an expansion device coupled to the computer system to initialize a memory area in volatile memory. The memory area is configured by the BIOS extension to interface with the expansion device, such that the expansion device is made available to the first application and the second application.

Method for updating firmware of a computer peripheral device

Abstract: An optical disc drive includes a system controller in the form of a microcontroller and a FLASH memory which holds program code for the micro controller. The FLASH memory is formed in two areas, the first being a protected area in which the code cannot be changed and the second being an unprotected area in which the micro controller can write updated program code. The updated code is received from a host computer over an interface ( 28 ). The code in the protected area and in the micro controller ROM is sufficient to enable the basic functions of requesting and receiving program code from the host computer and writing the received program code into the unprotected area of the FLASH memory to be performed. This enables recovery of the drive if the code in the unprotected area becomes corrupted, for example if a power supply failure occurs during transfer of the code.

Arrangements having firmware support for different processor types

Abstract: A system, a method of operating the system and a system firmware. The system includes a processor and a system firmware including a plurality of customized firmware parts, with each firmware part performing system firmware functions required for and customized to only a subset of a plurality of types of processors which are operational when connected to the system, and a processor identification device, coupled to the system, which identifies which subset of the plurality of types of processors is connected to the system and in response to the identification of the type of connected processor, causes a customized firmware part corresponding to the identified types of processor to be executed by the processor.

Disk array device for ensuring stable operation when a constituent disk device is replaced

Abstract: When it is determined in a disk replacement determining section that a disk has been replaced during system operation, a reference disk device is selected by a reference disk selecting section from disk devices other than a disk device having been replaced. The firmware (firmware storing area) of the reference disk device is copied into the replaced disk device.

Non-tethered apnea screening device

Abstract: The present invention provides a method and a device for evaluating a fully ambulatory subject for sleep apnea. In a preferred embodiment, this method is seen to comprise the steps of (1) locating on the subject's upper lip an airflow sensor that is connected with a miniature, recording unit which has: (a) signal conditioning and filtering circuitry to yield required levels of airflow sensor signal fidelity, (b) a programmable controller having an analog to digital converter, an integrated recorder, a data display means, and firmware that analyzes the airflow sensor signal, (c) a mini jack connected to the recorder that connects with a smart cable to control data flow between the recorder and an external computer (2) using this unit to sample at prescribed time intervals the sensor data which effectively quantifies the temporal variation of the subject's inspiration and expiration airflow, (3) time stamping and storing this sampled data in the integrated recorder, (4) using the firmware to identify, count and cause the display of the number of apnea events identified as occurring per a specified period of time, and (5) using an external computer with application software to analyze and display the data for further evaluation of sleep apnea events.

Apparatus and method for enhancing data transfer rates using transfer control blocks

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues

Abstract: This paper describes StarT-Voyager, a machine designed as an experimental platform for research in cluster system communication. The heart of StarT-Voyager is a network interface unit (NIU) that connects the memory bus of a PowerPC-based SMP to the MIT Arctic network. The NIU is highly flexible, with its set of functions easily modified by firmware or by programmable hardware, making it possible to compare different communication interfaces and implementation strategies on a common platform. Its flexibility comes from a fast embedded processor and large, fast FPGAs that surround a high-speed protected communication core. Its efficiency comes from a set of primitive operations that are implemented in hardware and are designed to reduce the firmware overhead. Our initial configuration of StarT-Voyager implements four forms of message passing along with S-COMA and NUMA shared memory support. With experimentation on the machine, it can be reconfigured to introduce new mechanisms improving usability and performance.

Command queueing engine

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Method for using two copies of open firmware for self debug capability

Abstract: A first copy of Open Firmware is loaded into system memory to supply a debug function and a second copy of the same firmware is then loaded to provide functional code which is to be debugged. The first copy of Open Firmware in system memory is designated as the resident debugging function. Kernel code, within the first copy, sets up an executing environment for the debugger, such as system exception handlers and debug console enablement. Normal Open Firmware configuration variables are retrieved from Non-Volatile Random Access Memory (“NVRAM”) by the first copy and transmitted to the loader. The second copy of Open Firmware is loaded into system memory to a location specified by the configuration variables. The second copy firmware image is designated as a normal Open Firmware operation in the system. The second copy initially takes over all system exception handlers except instruction breakpoint exception, program interrupt exception and trace exception. The instruction breakpoint exception is utilized to invoke the first copy, or resident debugger, from the normal Open Firmware (second copy) image during code debugging. The two copy debugging configuration is utilized in conjunction with an online machine language assembler and disassembler.

Means and method for configuring a data processing pipeline

Abstract: A configurable data processing pipeline for processing data, such as print data, provides configuration flexibility, thereby allowing the data processing operations to be optimized for the data, while achieving improved data processing speed. In the preferred embodiment, the configurable data processing pipeline is implemented in an ASIC. The configurable data processing pipeline includes compression/decompression modules, a page strip manager, a color space conversion module, a merge module and a halftone module. A method for controlling the pipeline accepts raster image data after it has been processed by image rendering firmware and prepares the raster image data for transfer to the pipeline. Page rendering firmware performs this function. Next, pipeline control firmware takes control and thereafter operates the pipeline ASIC, independently of the page rendering firmware.

One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access block

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be sent. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Method and system for programming firmware over a computer network

Abstract: A method and apparatus for programming a programmable hardware device of a local computer system that is connected to a network, uses a programming file that is resident on a remote system which is also connected to the same network. A method for facilitating such programming includes providing a Java-language program that is capable of accessing a programming file having data, providing a Java Native Interface (JNI) implementation that is capable of facilitating a sending of data from the programming file to the programmable hardware device, and providing a Java Native Interface that facilitates communication between the Java-language program and the JNI implementation. Another method for such programming by a user includes accessing a programming file having data and located on a computer system that is remote from the local system and connected to the local system through a network, using a Java program. The method also includes retrieving the data from the programming file and sending the retrieved data to the programmable hardware device, such that the retrieving and sending are facilitated by using a particular Java Native Interface (JNI) and a particular JNI implementation.

Firewall security protection of parallel processing in a global computer networking environment

Abstract: This invention generally relates to one or more computer networks having personal computers or network servers with master (30) and slave microprocessors (40) and a firewall (50) between them. The microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large number of computers connected, like the Internet, wherein more that one separate parallel processing operation involving more that one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network. Still more particularly, this invention relates to business enabling the shared use of network microprocessor for parallel and other processing.

Performance monitoring in a Myrinet-connected SHRIMP cluster

Abstract: Performance monitoring is a crucial aspect of parallel programming. Extracting the best possible performance from the system is the main goal of parallel programming, and monitoring tools are often essential to achieving that goal. A common tradeoff arises in determining at which system level to monitor performance information and present results. High-level monitoring approaches can often gather data directly tied to the software programming model, but may abstract away crucial low-level hardware details. Lowlevel monitoring approaches can gather fairly complete performance information about the underlying system, but often at the expense of portability and flexibility. In this paper we discuss a compromise approach between the portability and flexibility of high-level monitoring and the detailed data awareness of low-level monitoring. We present a firmware-based performance monitor we designed for a Myrinet-connected Shrimp cluster. This monitor combines the portability and flexibility typically found in software-based monitors, with detailed, low-level information traditionally available only to hardware monitors. As with hardware approaches, ours results in little monitoring perturbation. Since it includes a software-based global clock, the monitor can track inter-node latencies accurately. Our tool is flexible and can monitor applications with a wide range of communication abstractions, though we focus here on its usage on shared virtual memory applications. The portability and flexibility of this firmware-based monitoring strategy make it a very promising approach for gathering low-level statistics about parallel program performance.

Method of overfill probe identification and control

Abstract: A fail-safe fluid transfer control apparatus has full redundancy in the response to various inputs such as overfill probe signals, ground detection signals, and the like. Independent microprocessor controllers independently evaluate the inputs and each output control signals to close a respective relay when the inputs indicate that fluid transfer may commence. The relays are arranged in series such that both must be closed for a fluid transfer to commence. The control signals from each controller include a static signal and an alternating signal, both of which must be properly output to close its respective relay. Each controller monitors the state of each relay, and discontinues its control signals if either relay appears to be malfunctioning. Each controller runs an different, independently written firmware program to process the detected inputs to prevent a common firmware error. An optical bypass key replaces conventional mechanical keys and transmits an optically encoded signal to the controller for establishing a bypass condition. A preheating circuit is also provided for providing a dynamic voltage supply to standard thermistor probes which may be encountered.

Method and apparatus for microcode downloading

Abstract: A method and implementing system are provided in which the download program is designed to execute either from a command line in a main menu or from a diagnostics or service menu 201 as a service aid. The drive program 203 loads an executable file 205 which first reads from a drive specific data ("DSDATA") file 207. This allows the executable file 205 to configure itself to correctly perform micro-code download on a specific and designated drive device. The executable file program then proceeds to download the data contained in the drive binary firmware file 208 to a designated drive write buffer 209. The program then prompts the operator for final confirmation that the drive should be updated. Once the operator confirms the download, the executable file program issues the command to load the firmware into the drive.

Method for read only memory shadowing

Abstract: A method that employs a ROM shadowing circuit to transfer ROM data to the RAM in order to implement the ROM shadowing process required during the initialization of a PC. When the ROM shadowing circuit detects a system reset signal, the ROM shadowing circuit holds the CPU in a reset state while the ROM shadowing circuit copies the ROM data to the RAM. When the data copy is completed, the ROM shadowing circuit releases the CPU, which then begins fetching and executing instructions that comprise firmware initialization routines from the RAM.

Checkpoint logging without checkpoint display device availability

Abstract: A processor register is reserved by early firmware code to be employed for checkpoint logging or for storing diagnostic information at the time of failure before a checkpoint display device, usually contained within an I/O subsystem, is initialized. Early firmware codes are usually written in assembly language and the firmware of the present invention dedicates a processor register for logging checkpoint information. If a machine fails before any checkpoint, or point of failure, is displayed by a checkpoint display device, a dedicated processor register has logged any checkpoint or diagnostic information. The error information relating to the failure is obtained from the dedicated register through JTAG (Joint Task Action Group) scanning utilizing a processor debugging tool.

IP Switching: Protocols and Architectures

Abstract: From the Publisher: What kind of switch can actually deliver the reduced latency, improved QoS (quality of service), and greater bandwidth demanded by services such as videoconferencing, multicasting, and virtual reality? Which switches meet the needs of your network? And, perhaps most importantly, which will keep up with technology that's always on the move? This book, covering both the firmware and software of IP switching, and written by one of the field's foremost experts, has all the answers. It provides the best overview of the entire arena, giving you everything from a nuts-and-bolts explanation of switching technology to a detailed, all-inclusive analysis of vendor offerings. Network designers, network managers, Internet service providers, and anyone dealing with the technical aspects of fast data flow, all need IP Switching: Protocols and Architectures.

Method and apparatus for preventing unauthorized access to computer-stored information

Abstract: A method and apparatus of a computer based security system to prevent unauthorized access to computer-stored information comprising several components. These comprise of an intrusion detection mechanism, a ROM-based firmware program, an internal battery sized to provide several minutes of operation of the computer system and all its internal devices, and a mechanism to reset the central processing unit of the computer and switch to battery power responsive to the intrusion detection mechanism.

Program rewriting device, network system and storage medium

Abstract: PROBLEM TO BE SOLVED: To easily rewrite programs for devices connected to a network. SOLUTION: All devices connected to a network and having the same machine sort as that of a device concerned are retrieved (S11 to S15), and whether the firmware of each of the devices is older than that of the device itself or not is judged (S23). When the firmware is older (S23: YES), the order firmware of the device is rewritten by the firmware of the device itself (S27). Thereby the firmware of each device connected to the network can easily be rewritten, and the firmware elements of all devices having the same machine sort as that of the device itself can be rewritten in the firmware stored by the device itself or newer firmware. Thereby labor required for the management of the network system can be reduced. COPYRIGHT: (C)1999,JPO

Arrangements offering firmware support for different input/output (i/o) types

Abstract: The invention is a system, a method of operating the system and a method of customizing a processing system to operate with different input/output (I/O) systems. A system in accordance with the invention includes a processor, an I/O system coupled to the processor and system firmware, including a plurality of parts which each operate to perform system firmware functions required for and customized to only one of a plurality of different I/O systems which are operational when coupled to the processor, and a storage coupled to the processor, for storing identifying information which, when read, causes only one of the parts of the system firmware to be executed by the processor to perform the system firmware function necessary to operate the one of the different I/O systems identified by the identifying information.