Showing papers on "Gate count published in 2017"

Use of global interactions in efficient quantum circuit constructions

Abstract: In this paper we study the ways to use a global entangling operator to efficiently implement circuitry common to a selection of important quantum algorithms. In particular, we focus on the circuits composed with global Ising entangling gates and arbitrary addressable single-qubit gates. We show that under certain circumstances the use of global operations can substantially improve the entangling gate count.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

Abstract: In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the n-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground ...

Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits

Abstract: Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum equivalent circuits using cascading reversible gates is complex. Predominantly, this work targets implementation of quantum equivalent circuits using cascading reversible gates. In this work, novel code converters and a dual-rail checker with lower cost metrics such as gate count, garbage output, ancilla input, unit delay, logical calculation, and quantum cost are constructed. Several new reversible gates, namely BE (binary excess), BG-2 (binary Gray), GB-2 (Gray binary), and NG-R1 and NG-R2 (N $$=$$= new, R $$=$$= reversible), are designed and used to construct efficient code converter and dual-rail checker circuits. The main contribution of these novel circuits is the consideration of the gate-level schematics in the respective quantum equivalent circuit using our proposed algorithm. The performance results establish that the novel binary-coded decimal (BCD)-to-excess-3, binary-to-Gray, and dual-rail checker achieve improvement of 25 and 66.6 % in gate count and 44.4 % in quantum cost, respectively, compared with counterpart designs.

High Speed Error Tolerant Adder for Multimedia Applications

Abstract: In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

Novel parity-preserving reversible logic array multipliers

Abstract: Reversible logic as a new promising design domain can be used for DNA computations, nanocomputing, and especially constructing quantum computers. However, the vulnerability to different external effects may lead to deviation from producing correct results. The multiplication is one of the most important operations because of its huge usage in different computing systems. Thus, in this paper, some novel reversible logic array multipliers are proposed with error detection capability through the usage of parity-preserving gates. By utilizing the new arrangements of existing reversible gates, some new circuits are presented for partial product generation and multi-operand addition required in array multipliers which results in two unsigned and three signed parity-preserving array multipliers. The experimental results show that the best of signed and unsigned proposed multipliers have the lowest values among the existing designs regarding the main reversible logic criteria including quantum cost, gate count, constant inputs, and garbage outputs. For $$4\times 4$$ multipliers, the proposed designs achieve up to 28 and 46% reduction in the quantum cost and gate count, respectively, compared to the existing designs. Moreover, the proposed unsigned multipliers can reach up to 58% gate count reduction in $$16\times 16$$ multipliers.

A pulsed decimal technique for single-channel, dynamic signaling for IoT applications

Abstract: Pulsed-Index Communication (PIC) is a recent technique for single-channel communication which is based on the principle of transferring the indices of only the ON bits in the form of a series of pulse streams. In this paper, we present a modified version of PIC which is based on the same underlying idea but with key improvements in data rate and reliability. The proposed technique is called Pulsed Decimal Communication (PDC). Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It however achieves higher data rates by introducing a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step. The segmentation step is used to split the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step is used to split further the segments into smaller sub-segments. The complete process reduces the number of pulses required to transmit binary data, thus improving the data rate. Compared with PIC, PDC achieves a 78% improvement in data rate and is more reliable as it eliminates the variations in the number of symbols to be transmitted. An FPGA and an ASIC (65nm technology) implementation of the protocol show that the low-power operation and small footprint of PIC are maintained in PDC, which consumes around 25of power at a clock frequency of 25MHz with a gate count of approximately 2150.

FPGA implementation of combined S-Box and InvS-Box of AES

Abstract: An implementation of a combinational memory-less S-Box and invS-Box (combinely) for ByteSub and InvByteSub transformations of AES on a same hardware. This is a part of the combined architecture of AES in which both encryption and decryption can be performed with an enable pin. Previously LUTs are used to implement the S-Box and InvS-Box of AES separately, which causes large amount of memory and area. In this paper, the proposed architecture is implementing using composite field arithmetic in finite fields GF(28) which is advantageous than LUT approach on the basis of hardware complexity. As both S-Box and InvS-Box are implementing on a same hardware, there is large reduction in gate count as well as in area. The power consumption is also reduced because of the resource sharing of multiplicative inverse module in both S-Box and InvS-Box. The proposed architecture implemented on Atrix7 FPGA board using Verilog HDL in Xilinx ISE 14.7.

Two-dimensional sorting algorithm for high-throughput K-best MIMO detection

Abstract: This brief presents a novel two-dimensional parallel sorting algorithm for high-throughput K-best detectors utilised in multiple-input multiple-output (MIMO) systems. The proposed sorting algorithm enhances the throughput by sorting a data set in parallel and avoids the relatively long latency of the traditional algorithms. This is especially important in MIMO systems utilising high-order modulation schemes. The authors used the sorting algorithm in a K-best detector with variable K values at different layers of the search tree, which improves the bit error rate performance and reduces the computational complexity significantly. The detector using the sorting algorithm is designed and implemented in TSMC 90-nm CMOS technology for 4 × 4 64-QAM MIMO systems. Operating at 200 MHz, the detector's throughput is 1.2 Gbps. Its equivalent gate count is 182K.

Exact Synthesis of Reversible Logic Circuits using Model Checking.

Abstract: Synthesis of reversible logic circuits has gained great atten- tion during the last decade. Various synthesis techniques have been pro- posed, some generate optimal solutions (in gate count) and are termed as exact, while others are scalable in the sense that they can handle larger functions but generate sub-optimal solutions. Although scalable synthe- sis is very much essential for circuit design, exact synthesis is also of great importance as it helps in building design library for the synthesis of larger functions. In this paper, we propose an exact synthesis technique for re- versible circuits using model checking. We frame the synthesis problem as a model checking instance and propose an iterative bounded model checking calls for an optimal synthesis. Experiments on reversible logic benchmarks shows successful synthesis of optimal circuits. We also illus- trate optimal synthesis of random functions with as many as 10 variables and up to 10 gates.

Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of 512 × 512 Frames

Abstract: Motion estimation accounts for major part of the computational complexity of any video coding standard. In this paper, we present efficient VLSI architecture for the implementation of hexagonal search algorithm for fast motion estimation. The proposed architecture employs sequential processing of pixel data rather than parallel processing in order to reduce the hardware area substantially while achieving the real-time speed. A novel on-chip memory organization is proposed, which reduces the address generation complexity and helps improve the speed. The architecture when implemented in Verilog HDL and mapped to Virtex-5 FPGA achieves a maximum frequency of 340 MHz, while the gate count is calculated to be 3.1 K. Thus, the proposed architecture is considered suitable to be incorporated in commercial devices such as camcorders and smart phones.

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

Abstract: Summary This paper presents a hardware design capable of supporting high-efficiency video coding inverse discrete cosine transform (IDCT) with a 32×32 transform unit size, using a single 1-D IDCT core with transpose memory to reduce costs. The proposed 1-D IDCT core employs 16 computation paths for high throughput and is implemented using distributed arithmetic to facilitate the sharing of hardware resources. The proposed 1-D IDCT is capable of calculating 1-D and 2-D data simultaneously along 32 parallel paths. When implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS technology, the proposed 2-D transform core provides throughput of 6.4 gigapixels/s with a gate count of 335 k. The results show that a superior hardware efficiency can be achieved in the proposed 32-point IDCT core compared with the existing works.

Test Pattern Compression for Probabilistic Circuits

Abstract: Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS'89 benchmark circuits show the total test length of our proposed ILP method is 64% shorter than a greedy method.

Comprehensive quantum analysis of existing four variable reversible gates

Abstract: Throughout the last decade, reversible logic has been an emerging research topic. Over the years, a considerable number of application specific new reversible gates with varied characteristics have been proposed. Barring few, most of the gates lack fundamental quantum mapping in contemporary literature. This paper takes into account the four variable reversible gates those have been proposed and provides the Toffoli mapping using positive control lines. The authors optimize the designs using negative control lines wherever possible. The quantum cost, quantum gate count and two-qubit gate count required to implement those reversible gates have been provided which will set a benchmark for optimized gate choice for complex Boolean realizations. The authors also provide Hamming Distance based Complexity analysis.

Controlled and Uncontrolled SWAP Gates in Reversible Logic Synthesis

Abstract: This paper presents a quantum-level realization and synthesis approach using SWAP and Fredkin (SF) gates. Our quantum realization of negative-controlled Fredkin gate requires five 2-qubit elementary quantum gates, the same as that required for realizing a positive-controlled Fredkin gate. We also propose and evaluate the performance of a synthesis approach using SF gates for realizing conservative reversible functions. Our result shows that circuit realization for conservative function using SF gates is more efficient than Toffoli gates. We achieve up to \(87\%\) improvement in gate count and quantum cost for \((4 \times 4)\) conservative reversible functions.

Novel conservative reversible error control circuits based on molecular QCA

Abstract: Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.

Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC

Abstract: In this paper, a hardware sharing architecture is proposed to support multi-standards--VP8 and H.264/AVC. To achieve a common architecture, the deblocking filters of VP8 and H.264/AVC are reorganized, and the lossless sharing architecture (RO-DBK) is obtained. For the lossy application such as low-resolution display devices, the modified coefficients to derive a highly sharing architecture (LC-DBK) are further adapted. The experimental results show that the PSNR only drops 0.36% on average for LC-DBK. These two proposed architectures save 74.2% and 80.2% arithmetic logic units, respectively. To further reduce memory usage, we propose a new VLSI architecture. In this VLSI architecture, the deblocking filter and the interpolation result of motion compensation and inverse transform share the same SRAM. To achieve this, a rearranged filtering order is also proposed. This design only uses 32 bytes transpose buffer without any SRAM usage. To reach real-time processing, a 3-staged pipeline scheduling is also proposed. The proposed design is implemented within 0.18 μm process. The working frequency is 100 MHz and the overall gate count is 3.9K.

Fast rate distortion optimization with adaptive context group modeling for HEVC

Abstract: Rate distortion optimization helps decide the best coding mode and partition to improve coding efficiency, but suffers from serious data dependency and complexity that hinders an efficient hardware encoder implementation. Thus, this paper presents a hardware-friendly fast rate-distortion method and its design. For rate estimation, we propose a context group adaptive entropy based method for more precise estimation and parallel computation that is applied to both intra and inter predictions instead of intra prediction only as in previous approaches. For distortion estimation, we use the transform domain instead of spatial domain computation to save inverse discrete transform computation and image reconstruction, and reduce cost further by adopting fixed zero sub-blocks in the high frequency part for 32×32 and 16×16 blocks. The simulation results shows 1.77% BD-rate loss in average. The proposed hardware design adopts the interleaved Luma/Chroma coding schedule to improve hardware utilization. The final implementation with TSMC 40nm CMOS process can achieve real time 4K×2K@30fps encoding with 57.95K gate count while operating under 400MHz clock frequency.

Reversible circuit design for GCD computation in cryptography algorithms

Abstract: Summary The implementation of cryptography algorithms is constantly observing threat from multiple techniques in breaking secure system. The current trend in breaking the secure system of cryptography is by power analysis technique. In order to break the secure key, the energy consumed in the digital circuit during computation is measured. This technique is commonly known as differential power analysis, explored by the hackers to break the secure systems. To circumvent these type of attacks, it is necessary to explore different designs, which dissipate less energy. Ideally, reversible circuits dissipate zero energy. We present a new reversible architecture for greatest common divisor (GCD) computation using modified Binary GCD algorithm. We present the generalized design methodology of reversible GCD computation unit. We compare the proposed GCD computation design with the existing design. The proposed reversible GCD architecture takes less number of iterations compared with the existing GCD architecture in the literature. The proposed design outperforms the existing GCD design in terms of Quantum Cost, Gate Count, and Ancilla Inputs. Copyright © 2016 John Wiley & Sons, Ltd.

Design and analysis of reversible multiplexer and demultiplexer using R-Gates

Abstract: The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation of their quantum cost, gate count, garbage outputs and depth of the circuit. The simulation results are obtain edinXilinxISE version 14.1. Reversible logic circuits are designed and implemented using Verilog code. The circuit is beneficial for further designing of reversible digital designs with low power loss. The devices designed through this circuit are expected to have a better performance as compared to the existing circuits.

Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling

Abstract: Pulsed-Index Communication (PIC) is a recent technique for single-channel communication that is based on the principle of transmitting the indices of only the ON bits as a series of pulse streams. In this paper, a modified version of PIC, called Pulsed Decimal Communication (PDC), is presented that uses the same underlying principle but with key improvements in data rate and reliability. Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It consists of a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step to achieve higher data rates. The segmentation step splits the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step further splits the segments into smaller sub-segments. The complete process significantly reduces the total number of pulses required for transmitting binary data, thus improving the data rate by about 78%. A theoretical model of the PDC protocol is exploited to estimate its data rate and derive the optimum segmentation. Furthermore, PDC is shown to be more reliable than PIC as it eliminates the variations in the number of symbols to be transmitted. The FPGA and ASIC (65 nm technology) implementations of PDC show that the low-power operation and small footprint of PIC are preserved. PDC consumes around \(25\,\upmu \mathrm{W}\) of power at a clock frequency of 25 MHz with a gate count of approximately 2150 gates.

Emulation Using FPGAs

Abstract: For the purpose of this chapter, we will use emulation to include prototyping also—since underlying challenges and methodologies are common. We read about simulators in Chap. 11. An emulator is a simulation-specific hardware, which is capable of retaining the parallelism of the blocks of the design, thereby significantly improving the speed of execution.

A Hierarchical Distributed Linear Evolutionary System for the Synthesis of 4-bit Reversible Circuits

Abstract: Even limited to 4-bits reversible functions, the synthesis of optimal reversible circuits becomes an arduous task owing to the extremely large problem space. The current paper tries to answer the following question: is it possible to implement optimal 4-bit reversible circuits without relying on existing partial solutions libraries? A distributed linear genetic programming based-approach (DRIMEP2) is presented. It consists of a hierarchical topology with a new communication policy to allow the evolutionary algorithm to explore and exploit the search space in an efficient way. To test the effectivity and the efficiency of the proposed system, the design of 69 benchmarks (4-bits reversible functions) was performed. With respect to good results available in the literature, a gate count reduction up to 60 % was achieved with an average of 16.82 % (for the two first benchmark groups where the gate count of the circuit was considered by the reference authors) and a quantum cost reduction up to 62.71 % was reached with an average of 10.79 % (for the two remaining benchmark groups where the quantum cost of the circuit was considered by the reference authors).

Implementation of quantum gate operations using neural networks

Abstract: All quantum circuits are designed using different quantum gates, which can be decomposed into elementary gates. The number of elementary gates in a quantum circuit is called the gate count. Typically, there is a direct correspondence between the gate count and the complexity of a quantum circuit. Quantum systems are generally very fragile, and a quantum bit (qubit) can lose its super-position state very easily. This process is called decoherence. As such, when implementing a quantum operation, it becomes necessary to minimize the gate count as much as possible. This thesis focuses on two important applications where reducing the gate count is very significant. The first is quantum error correction (QEC). In a quantum error correction code (QECC), one information qubit is encoded with two or more auxiliary qubits to form a logical/encoded qubit. Oftentimes, when performing gate operations on logical qubits, decoding is required, which opens the system to decoherence. The aim here is to design encoded quantum gates in such a way that the decoding process is no longer needed for implementing gate operations on QEC circuits. The second focus is a controlled-NOT (CNOT) gate operation between uncoupled (remote) qubits. In order to implement a gate operation in a linear nearest neighbor (LNN) architecture, the qubits that are not neighbors need to be brought adjacent to each other before a gate operation can be performed between them. The LNN architecture is significant because most physical implementations of a practical quantum computer use this layout. Here, the aim is to implement a CNOT gate between remote qubits in an LNN architecture without bringing the qubits adjacent to each other, thereby tremendously reducing the gate count. This research employed a neural network approach based on gradient descent technique to reduce the gate count.

Design of Ancilla Invariant and Quantum Cost efficient reversible arithmetic components

Abstract: Reversible computing is an emerging field of research and has made remarkable progress. Owing to the reduced energy dissipation in reversible circuits, a lot of research has been done on the design of reversible circuits. In reversible logic circuit designs, along with primary inputs, few constant inputs (Ancilla Inputs) are used to realize required reversible functions. In addition to this, few unused or extra output bits are generated; these bits are named as Garbage Output bits. A challenge in the reversible computation is to use minimum Ancilla Inputs and generate zero Garbage Outputs. In this work, we present designs for addition, subtraction, and addition or subtraction operations. The designs are primarily optimized to achieve zero Garbage Outputs and minimum Ancilla Inputs. In addition, these proposed arithmetic circuits are designed for best Gate Count and Quantum Cost values compared to the existing counterparts.

Nanotechnology-Based Efficient Fault Tolerant Decoder in Reversible Logic

Abstract: Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2n fault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.

Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications

Abstract: Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5m W, and 0.06m W, respectively, at 10MHz in a 0.18μm digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50μW/MHz with 10,800 gates in a 0.18μm CMOS process.

Review and Comparative Analysis of Stream Cipher for LTE Technology

Abstract: With the advancement in the telecommunication system, fast evolution in mobile communication has been observed. Besides this there are many applications in the wireless sensor network which needs limited resources such as low gate count, low power consumption, low memory etc. These applications are mobile phones, smart grids, electronic identity cards, and RFID (Radio Frequency Identification Devices) tags. In this paper, we have discussed about the evolution of communication technology from first generation to fourth generation. We have also studied the security issues of LTE (long Term Evolution) technology. We have surveyed the various stream ciphers and comparative analysis of the various stream ciphers has also been done. On the basis of comparative analysis we have provided the research direction for the future work.

Implementation Fault Tolerant Full Adder/Subtractor Using Reversible Logic Gates

Abstract: Reversible logic is most popular concept in energy efficient computations and this will be demand for upcoming future computing technologies. Reversible logic is emerging as an important research area and it will be having wide applications in many fields such as optical information processing, quantum computing and Low power CMOS design. Under ideal conditions, the reversible logic gates will produce zero power dissipation. So this concept will helpful for Low power VLSI design. This paper will proposes the design of Full adder/subtractor circuit using fault tolerant reversible gates. The design can work singly as an adder/subtractor. The proposed design offers less hardware complexity and is efficient in terms of gate count, delay, constant inputs and garbage outputs compared to previous Fault tolerant Full Adder/Subtractor design. A parallel adder/subtractor design using fault tolerant reversible gates also proposed in this paper. The proposed circuits will be simulated using ModelSim simulator and implemented in Xilinx FPGA platform.

A novel design and analysis of reversible barallel shifter using new FF-gate

Abstract: The need for low power has gained attention towards lot of low power techniques from quantam physics the concept of reversible logic has evolved to reduce the power dissipiation. This paper deals with the design of 8 bit shift register using reversible logic. The existing system the implementation carring out using Fredkin gate Feynman gate. Our design using implementation 4 × 4 ff gate which reduces the gate count as well as the gorbadgeoutput. The proposed design shows better output performance and provides and low power consumption than the existing design.