Showing papers on "Gate driver published in 1992"

High frequency resonant gate drive for a power MOSFET

Abstract: An efficient power MOSFET resonant gate drive circuit having a large coupled inductor between and in series with two switching transistors. The inductor prevents cross-conduction from the power bus through the drive transistors as may be caused by simultaneous turn-on due either to switching delays or single-event-upset-radiation from energetic cosmic rays. In either case, the inductor presents a high impedance for current that tries to flow through both transistors simultaneously. A center tap on the inductor is connected to the gate of the power MOSFET. An equivalent inductance resonates with the equivalent capacitance of the gate of the power MOSFET providing fast turn-on of the power MOSFET. During turn-off of the power MOSFET, one drive transistor is switched-off and the other drive transistor is switched-on. The voltage generated by the coupled inductor exceeds the magnitude of the input voltage causing a diode within the off-transistor to turn-on and return energy back to the power source, thereby further increasing the circuit efficiency.

Soft-switched high-frequency, high power DC/AC converter with IGBT

Abstract: A 20 kVA direct DC/LFAC dual active bridge (DAB) power converter projected for operation at 100 kHz with insulated gate bipolar transistor (IGBT) switches is presented. It has dual-angle, constant-frequency phase shift control, and is soft switched in a large part of the output V-I plane. It also has a high performance digital control system. The topology and its properties are presented. The control strategy and regulation of the loop are examined. Experimental results are shown for both a small-scale model and a full-scale converter. >

A novel lossless resonant MOSFET driver

Abstract: A low-impedance isolated or nonisolated capacitor driver with negligible practical losses is presented. Peak capacitor voltages are totally predictable, and the driver can self-regulate to drive a 1 nF-10 mu F capacitor with unchanged risetime. Circuit results exhibit MOSFET gate-drive losses below 2% of the power lost in classical drive circuits. >

Drive amplifier for power line communications

Abstract: A power line communication amplifier circuit for providing a signal transmission across a power line medium when operating in a transmit mode, and for providing a relatively high input impedance to the power line when in a receive mode includes a unity gain buffer integrally coupled with a filter. The filter operates upon an input signal provided by a digital driver means. A control means is coupled to the digital driver means and to the buffer such that when said amplifier is switched to a receive mode, both the driver means and buffer provide a high input impedance.

Power transistor driver circuit with current sensing and current overprotection and method for protecting power transistor from overcurrent

Abstract: A circuit and method for driving a power transistor device. The circuit for driving a power transistor device has a driver having an input and an output, the output coupled to a control input of the power transistor device and the input coupled to a primary control voltage source for driving the power transistor device. A current sensing device is coupled to the power transistor device for providing a signal proportional to the current in the power transistor device. An amplifier is coupled to the current sensing device for providing a substantially linear control signal proportional to the current in the power transistor device, the linear control signal being provided to the input of the driver as a secondary drive signal for driving the power transistor device when a current level in the power transistor device greater than a threshold level is detected. A detector is provided for detecting when the current in the power transistor device is greater than the threshold level. The detector is coupled to the current sensing device and to a reference level source, and provides an overcurrent signal to the driver for switching the driver from being driven by the primary control voltage source to the secondary drive signal. The secondary drive signal drives the driver so as to reduce the current level in the power transistor device. The driven power transistor device is preferably a power MOSFET or IGBT.

High efficiency floating gate driver circuit using leakage-inductance transformer.

Abstract: A gate driver for turning on and turning off a power switching device (118) having a capacitive gate control input (162) provides galvanic isolation between low-level control circuitry (122) and the power switching device by means of a transformer (104) having a controlled amount of effective secondary leakage inductance. The secondary (108) of the transformer is connected in series with the gate control input (162) and a first unidirectional conducting device (110). Driver logic on the secondary side of the transformer controls a gate switch which is connected across the gate control input. The gate driver operates in a multiplexed mode: if a voltage pulse is applied across the primary winding (106) of the transformer at a time when the power switching device is off the driver logic will turn the gate switch off, thereby enabling charging of the effective gate capacitance (116) as a means of turning the power switching device on; if a voltage pulse is applied across the primary winding of the transformer at a time when the power switching device is on the driver logic will turn the gate switch on, thereby discharging the effective gate capacitance as a means of turning the power switching device off.

Transistor structure for use in erasable and programmable semiconductor memory devices

Abstract: A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.

High power mos device with protective circuit against overcurrent or the like

Abstract: This invention relates to an improvement of a high power mos device which includes a plurality of power MOSFETs whose drain regions and source regions are respectively connected in common with each other and respectively receive on-off control voltages (VGa-VGn) to the respective gate regions, and circuits for generating the control voltages (VGa-VGn). When short-circuiting occurs between the gate and the source in either of these power MOSFETs, a gate current detection and interruption circuit (11a-11n) is inserted between a control voltage source (2) and the gate so as to interrupt the supply of the control voltage (VGa-VGn) to the gate. With such an arrangement it becomes possible to dissolve adverse effect due to the short-circuiting between the gate and the source, which was not possible in the prior device of this kind, and to improve the reliability of the monolithic power MOSIC device.

Method and apparatus for feedback control of I/O characteristics of digital interface circuits

Abstract: A transceiver network having a driver and a receiver circuit for providing an interface between, for example, a data bus and a system controller or the like is disclosed herein. The receiver circuit includes a first logic gate of a first predefined type for providing output signals in response to input signals in accordance with a first transfer characteristic governed by a first reference voltage. A compensation arrangement is provided for adjusting the first reference voltage, and includes a first compensation gate of the first predefined type having an output governed by the first reference voltage. A first feedback loop coupled to the first compensation gate's output varies the first reference voltage until the first compensation gate generates a predefined output signal. The driver network includes a second input logic gate of a second predefined type having a first current transfer characteristic governed by a gate control voltage. A second compensation arrangement adjusts the gate control voltage, and includes a second compensation gate of the second predefined type having a current transfer characteristic proportional to the first current transfer characteristic. A second feedback loop coupled to the second compensation gate varies the gate control voltage until current flowing through the second compensation gate matches a supply current.

Insulated gate thyristor with gate turn on and turn off

Abstract: An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T5) that can turn off the latched IGBT.

Three level IGBT inverter

Abstract: To extend the application of insulated gate bipolar transistor (IGBT) inverters in motor drives to higher voltages, a three-level IGBT inverter has been developed. The power circuit realized and a pulse pattern generator with space voltage modulation are described. A method to control the middle point potential is suggested. The three-level IGBT inverter can be applied to industrial drives with a three-phase supply voltage of 660 V and drives for local traffic with DC line voltage of 600-750 V. >

Overcurrent protector for power element

Abstract: A circuit for providing an overcurrent protection for a power element, such as an IGBT, MOSFET or bipolar transistor, which is inserted between the power supply and a load, the protection circuit comprising a control circuit that provides an input to a gate amplifier at the power element gate. The gate amplifier comprises a photodiode that is connected between the amplifier power supply and the power element gate. The photodiode provides a clamp of the gate voltage in the event of an overcurrent and communicates optically with a phototransistor to provide a detection signal that can modify the control circuit operation. Specifically, the detection circuit can modify the input to the control circuit or control the output of the control circuit so that the energization of the power element is stopped or limited. The control can be through Darlington-connected transistors at the output of the phototransistor.

Driver for backplane transceiver logic bus

Abstract: A driver which is particularly suitable for use with a backplane transceiver logic bus in a computer system is disclosed. In a preferred embodiment, a MOSFET is connected such that its gate and source are in a feedback loop which includes an amplifier and a first switching MOSFET. The source and drain of the MOSFET are connected in a connection path from the bus to ground, and a second switching MOSFET is connected between the gate of the MOSFET and ground. The first and second switching MOSFETS are arranged such that they switch in opposition to each other (one being turned on when the other is turned off) and a CMOS input signal is connected to the gates of the switching MOSFETS. In one state of the driver the MOSFET is turned off, in the other state the feedback loop is closed and the MOSFET is conductive. The rise and fall times of the driver's output can be controlled independently of each other.

Ultra low-noise charge coupled device

Abstract: Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

Double gate MOS device having IGBT and MCT performances

Abstract: A new MOS-bipolar device having IGBT and MCT performances is described. The double gate MOS (DGMOS) can operate at a thyristor action in the on-state and a bipolar transistor action in the turn-off transient state by applying gate signal to two MOS gate electrodes. This new device exhibits very good performance with the almost same low forward voltage drop as a conventional thyristor and the almost same turn-off characteristics as a fast IGBT. This paper reports the new device concept and the results of numerical simulation of its perkormances using two dimensional numerical simulation.

High stability static memory device having metal-oxide semiconductor field-effect transistors

Abstract: A static memory device has memory cells each having a pair of driver MOSFETs, two load resistors each connected between a power source and a drain of each of the driver MOSFETs, two access MOSFETs each of which is connected between the drain of each of the driver MOSFETs and each of bit lines and gates of which are connected to a word line. In the memory cell, the thickness of a gate oxide film of the access MOSFET is made thicker than that of the gate oxide film of the driver MOSFET. The operation stability of the memory cell is enhanced, without the need of increasing a chip size, by increasing a ratio between the driver MOSFETs and the access MOSFETs of the memory cell (the ratio of current supplying capabilities of the two transistors) without making a gate size large or without making it so small as to cause process variations.

Semiconductor switching device with reduced switching loss

Abstract: A semiconductor switching device including a first IGBT and a second IGBT connected in parallel The first IGBT has a low saturation voltage and a long fall time, whereas the second IGBT has a high saturation voltage and a short fall time. An input resistor is connected to the gate of the second IGBT, and a common drive signal is applied to a gate of the first IGBT, and to a gate of the second IGBT through the input resistor. The cutoff of the second IGBT is delayed when the first and second IGBTs are driven by the common drive signal so that the semiconductor switching device is turned off in the short fall time of the second IGBT. The switching speed is increased and the switching loss is decreased. Only a single drive circuit is enough for driving the device, enabling the miniaturization and low cost of the driving circuit.

Multiple-gate split-drain MOSFET magnetic-field sensing device and amplifier

Abstract: A new split-drain MOSFET magnetic-field sensing device is reported which uses multiple gates to establish a longitudinal electric field in the channel. A relative sensitivity of 185 mA/AT was measured for a double-polysilicon, multiple-gate, split-drain MOSFET. A triple-drain multiple-gate MOSFET device achieved relative sensitivities greater then 10,000 mA/AT. A new amplifier circuit for the multiple-gate, split-drain device achieved an absolute sensitivity of 10 V/T at a 400 nA bias current corresponding to a relative sensitivity of 2.5*10/sup 7/ V/AT. The intrinsic power dissipation of the magnetic amplifier sensor is as small as 8 mu W. >

Driver circuit for sinking current to two supply voltages

Abstract: An insulated gate bipolar transistor (IGBT) gate driver circuit with a push-pull output stage which provides current sinking to two power supply rails. Current sinking to a low impedance power supply rail (GND) via a high current NPN bipolar transistor provides fast IGBT turn off. A PNP bipolar transistor forward biased emitter-base junction in series with an N channel field effect transistor provides current-limited current sinking to a higher impedance power supply rail (VEE). The on resistance of the N channel field effect transistor can be chosen to set the maximum current drawn from the higher impedance VEE power supply rail. This current-limiting avoids the need for a second low impedance power supply. The transition of the output of the driver from ground to VEE is only a function of the output voltage output by the driver. It is not a function of any timed switching of transistors.

Null consumption, nonvolatile programmable switch

Abstract: A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

Transmission power amplifier device

Abstract: Disclosed is a transmission power amplifier device comprising a GaAs power amplifier using a GaAs FET as its amplifier element. In order to compensate the non-linearity of the frequency characteristic of the transmission power amplification efficiency of the GaAs power amplifier with respect to individual amplified signal transmission channels, gate voltage information for each of the channels is stored beforehand in a memory, and a gate voltage obtained by adding a fixed voltage to an analog voltage generated on the basis of the gate voltage information read out from the memory is applied to the gate of the GaAs FET so as to flatten the frequency characteristic of the transmission power amplification efficiency.

Semiconductor memory device having a word driver

Abstract: Each driver circuit included in a word driver includes a transfer transistor and a driver transistor. A voltage of a predetermined voltage lower than a threshold voltage of the transfer transistor plus a power supply voltage is applied to the gate of the transfer transistor in an active period.

Balancing of communications transport connections over multiple central processing units

Abstract: A communications control system in a multi-processor system includes a connection distribution data structure, including, for each central processing unit, a connection count means for storing a number representing the number of communication connections currently being executed by the corresponding central processing unit, and a gate driver interface service module. The gate driver interface service module is a single task resident in the computer system memory with an active invocation in a single central processing unit of the processing system. The gate driver interface service module responds to each request by selecting the central processing unit presently executing the least number of communication connections, and assigning the communication connection to the central processing unit for execution by constructing a corresponding control block containing the identification of the central processing unit assigned to execute the communication operation. The gate driver interface service module provides the control block to a communication controller, and the communication controller being responds to a control block for performing the requested communication operation.

Fast turn-off circuit for use with an AC bridge circuit

Abstract: A power output driver circuit that converts a DC voltage into an AC voltage includes a gate driver circuit for turning on electronic switching devices. The gate driver circuit allows for a rapid turn-off of the conducting electronic switching device by having a first conduction path for the gate drive signals that turn-on the switching devices and a second conduction path that rapidly discharges stored energy in the gate/drain capacitance of the switching devices, resulting in a faster turn-off time. A transistor in the gate circuit shunts the stored charge directly to the source terminal of the switching device.

Soft switching self-oscillating FET-based DC-DC converters

Abstract: The authors introduce a family of topologies utilizing both zero voltage switching and self-oscillation. The Royer oscillator is modified to use MOSFETs as power switches. Thus insulated gate bipolar transistors (IGBTs) can also be used as power switches, enhancing the power capability for higher voltage and current ratings. A further advantage obtained by the use of FET-input switches, compared to the bipolar-transistor-based Royer and Jensen oscillators, is that stable operation can be obtained without the saturation of any core material. This enables very high efficiency of the power converter as well as a very high oscillation frequency. Typical applications of the family of topologies considered include DC-DC converters, high-frequency inverters, and high-frequency link converters. In high-power (>1 kW) applications, the use of IGBTs in the nonlinear resonant pole soft switching self-oscillating inverter will be advantageous to the efficiency, due to the reduced onstate voltage of a minority carrier device. >

A thorough investigation of dynamic bias on linear GaAs FET power amplifier performance

Abstract: The authors present the results of a thorough study on the effects of dynamic gate bias on GaAs power FET performance. Detailed information concerning the effects of gate bias changes on gain, input return loss, and linearity are included. A two-stage linear power amplifier was built and tested that successfully demonstrated dynamic gate bias optimization. This amplifier produced over 5 W of output power at the L-band with high efficiency and excellent linearity. >

Gate drive circuit for igbt

Abstract: PURPOSE: To attain complete protection of an IGBT gate drive circuit used for an inverter or the like even when a voltage of a control power supply is abnormally low. CONSTITUTION: The circuit is provided with a short-circuit circuit 24 comprising a 1st transistor(TR) 18, a resistor 19, a 2nd TR20 and a voltage division circuit 21. When a voltage of a control power supply 5A is reduced less than a prescribed value, the 1st TR20 is turned off. When a voltage due to a high dv/dt is induced to the gate of the IGBT 3A in this state, the voltage is used for a power supply to turn on the 1st TR18 and then a sink use TR17 thereby suppressing a gate voltage of the IGBT3A to a low value and preventing mis- trigger. COPYRIGHT: (C)1993,JPO&Japio

Driving and protecting the latest high voltage and current power MOS and IGBTs

Abstract: The new smart high-voltage gate drivers, the IXBD4410 and the IXBD4411, were designed to drive and protect power MOS and insulated gate bipolar transistor (IGBT) devices and modules in a phase leg or a totem pole inverter output configuration. These gate drivers function reliably under extreme d nu /dt and di/dt noise environments, with the half bridge inverter output voltages limited only by the breakdown of the external discrete devices. The IXBD4410 provides a diagnostic fault output flag, reflecting the condition of not only the low side but the high side device in a half bridge application. The IXBD4410 family devices can be configured to detect operating overcurrents using a resistor in series with the power device source, or by using one of several desaturation sense circuits presented. If the drive current output of the IXBD4410 is not adequate, a simple circuit consisting of a pair of complementary bipolar transistors can be placed between the IXBD4410 family device and the power MOS, IGBT, or module. >

Current limit circuit for IGBT spark drive applications

Abstract: An improved method for current limiting applications to control the current through MOSFETs or IGBTs. An amplifier having a single, high-frequency pole is used to drive the large gate capacitance of a power MOSFET or IGBT. The current in the power transistor generates a negative feedback voltage in a sensing resistor. This feedback voltage is compared with a reference voltage to determine the output voltage of the amplifier. This provides greater stability for driving IGBT transistors, and the actual frequency response is only dependent upon the poles generated by the power transistor and its load. The current in the transistor ramps up to a value determined by the reference voltage, and then settles to a constant value with little or no overshoot or oscillation.

An improved power MOSFET macro model for SPICE simulation

Abstract: The SPICE MOSFET model was originally designed for modeling small signal lateral MOSFETs. Due to structural differences between small signal IC FETs and large geometry vertical FETs, the model is not able to simulate a power MOSFET accurately. Several macro models have been developed to overcome this problem. These models have served power designers well. However, inaccuracies in the gate charge and switching time characteristics cannot satisfy the needs of designers in the simulation of modern high frequency power supply design. To improve the accuracy of gate charge and switching time characteristics, a new model is developed based on the approach proposed by C.E. Cordonnier. In the new model an arbitrary current source is used to model the nonlinear gate to drain capacitance, Cgd. To improve simulation efficiency, the model avoids the use of any switches, which often cause voltage discontinuities. The model is fully tested in a variety of test circuits and results are compared to data sheet information to demonstrate the accuracy of this new model.< >