Showing papers on "Hardware register published in 2005"

Network-Based System for Configuring a Programmable Hardware Element in a Measurement System using Hardware Configuration Programs Generated Based on a User Specification

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Method and apparatus for register allocation in presence of hardware constraints

Abstract: A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.

Parallel software testing based on a normalized configuration

Abstract: A system of testing software is provided. The system comprises a first hardware system having hardware components to execute a first version of the software, and additionally comprises a second hardware system having hardware components to execute a second version of the software at approximately the same time as the hardware components of the first hardware system execute the first version of the software. Here, the hardware components of the first hardware system are essentially equal to the hardware components of the second hardware system. In addition, the system includes a simulator coupled to the first hardware system and the second hardware system through the same network. This simulator comprises an agent to input a substantially same amount and a substantially same type of input data into the first and second hardware systems for execution by the first and second versions, respectively.

Electronic software distribution method and system using a digital rights management method based on hardware identification

Abstract: An electronic software distribution (ESD) method is provided for digitally distributing a software application. The method starts by receiving a set of user data, and then generates from the user data a digital hardware signature having a hardware identification attribute. The digital hardware signature is then appended to a software application to generate a software application package. The digital hardware signature assures that the software application package is fully executable only on a hardware device having a matching hardware identification attribute.

Online specification of a system which compares determined devices and installed devices

Abstract: A system and method for online configuration of a measurement device for a measurement system. The user accesses a server with a client computer over a network and specifies a desired measurement task. If the user lacks the hardware required to perform the task, hardware specifications and configuration software and/or data specific to the user's application, i.e., to perform the task, are sent to a manufacturer, who pre-configures the hardware with the configuration software and/or data to perform the task and sends the pre-configured hardware to the user. The hardware may be re-configurable hardware, such as a programmable hardware element or processor/memory based device. Configuration software and/or data for configuring the user's measurement system hardware (and/or software) to perform the desired task may also be sent to the user. The configuration software sent to the user may comprise a graphical program usable by the measurement system to perform the task.

Comparison of the Hardware Implementation of Stream Ciphers.

Abstract: In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area in an FPGA device. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards, especially wireless communication protocols. The Helix cipher is a recently introduced fast, word oriented, stream cipher. W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems concerning A5/1. The designs were implemented using VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each stream cipher in terms of throughput-to-area ratio. This ratio equals to: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

Technique to read special mode register

Abstract: Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command self-terminates by placing the data bus in a high impedance state. One or more unused address bits may specify one of a plurality of special mode registers to be accessed by the command. The command to access the special mode register may be incapable of changing one or more bits in a mode register.

System and method for information handling system manufacture with verified hardware configuration

Abstract: An information handling system hardware signature based on a verified hardware configuration for the information handling system serves as a reference to confirm the hardware configuration of the information handling system through a manufacture process. For instance, after hardware component testing, the hardware components of the information handling system are queried and compared against the hardware signature to ensure continued compliance with the verified configuration. Similarly, the hardware configuration is confirmed against the hardware signature after loading an image and prior to final test of the assembled information handling system. Comparison of current hardware with the hardware signature throughout the manufacture process ensures compliance with a predetermined hardware configuration without requiring multiple hardware verifications.

Hardware Security Module.

Abstract: PCT No. PCT/JP81/00132 Sec. 371 Date Dec. 10, 1981 Sec. 102(e) Date Dec. 10, 1981 PCT Filed Jun. 5, 1981 PCT Pub. No. WO82/04298 PCT Pub. Date Dec. 9, 1982.A bonnetless outside-screw type globe valve made of carbon steel, 31/2 nickel steel or other kind of stainless steel and designed to be usable for controlling a high-pressure fluid is provided. A yoke 19 is screw-joined directly to the body 1, and a stuffing box 7 is provided in the body 1. A flanged cylindrical buck seatring 18 is screwedly fixed to the lower portion of the stuffing box 7, and a disc guide hole 9 arranged to make a slide fit with the disc 16 is formed in said lower portion of the stuffing box. The valve body seat 10 and the inlet and outlet holes 12 and 13 are formed smaller in diameter than the pipeline connected thereto, and each of said inlet hole 12 and outlet hole 13 is provided with a throttling portion (14, 15). This valve is suited for use in the petrochemical apparatuses for the control of a high-pressure fluid.

Hardware functionality scan for device authentication

Abstract: Systems and methods for verifying the authenticity of a graphics chip or other hardware chips or hardware devices by performing a hardware functionality scan.

Method and apparatus for discovering hardware in a data processing system

Abstract: A method, apparatus and computer instructions for discovering hardware nodes having a hierarchical organization. A subset of the hardware nodes in the data processing system is initialized prior to loading an operating system supporting parallel threads. In response to loading the operating system, thread for each hardware node discovered below a known hardware node is created to form a set of threads.

FPGA-aware garbage collection in Java

Abstract: During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. This paper identifies the different levels of abstraction of hardware and software as a major culprit of this mismatch. For example, when programming in high-level object-oriented languages like Java, one has disposal of objects, methods, memory management, that facilitates development but these have to be largely abandoned when moving the same functionality into hardware. As a solution, this paper presents a virtual machine, based on the Jikes Research Virtual Machine, that is able to bridge the gap by providing the same capabilities to hardware components as to software components. This seamless integration is achieved by introducing an architecture and protocol that allow reconfigurable hardware and software to communicate with each other in a transparent manner i.e. no component of the design needs to be aware whether other components are implemented in hardware or in software. Further, in this paper we present a novel technique that allows reconfigurable hardware to manage dynamically allocated memory. This is achieved by allowing the hardware to hold references to objects and by modifying the garbage collector of the virtual machine to be aware of these references in hardware. We present benchmark results that show, for four different, well-known garbage collectors and for a wide range of applications, that a hardware-aware garbage collector results in a marginal overhead and is therefore a worthwhile addition to the developer's toolbox.

Hardware based online profiling in AMIDAR processors

Abstract: Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. Yet, the question has to be answered, which parts of the running application should be transformed into hardware. The migration of complete methods or procedures into hardware is often not feasible. In this contribution we show a hardware circuit that enables the processor to collect an execution profile of Java methods with a high resolution. We also show, how this profile information can be used to make reasonable choices for candidate instruction sequences.

Multithreaded hardware systems and methods

Abstract: Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an integer greater than or equal to one, and an offline storage structure having M hardware threads, where M is an integer greater than or equal to one. The multithreaded processor system may further comprise a thread control that transfers register values associated with at least one of the N hardware threads to registers of at least one of the M hardware threads and transfers register values of at least of one of the M hardware threads to registers of at least one of the N hardware threads.

Network-based specification and delivery of a measurement system

Abstract: System and method for online configuration of a device for a measurement system. The user accesses a server with a client computer over a network and specifies a task. If the user lacks the hardware to perform the task, hardware specifications are sent to a manufacturer, who sends the hardware to the user. The hardware may be re-configurable hardware (a programmable hardware element or processor/memory based device). Software products (programs and/or data) for configuring measurement system hardware (and/or software) to perform the task may be sent to the user. The hardware may be configured automatically or by the user. The software products may include programs usable by the measurement system to perform the task, configuration information for configuring the client computer or other measurement device, and/or hardware configuration program(s) for configuring a programmable hardware element. Thus, hardware and/or software specific to the user's application are be provided to the user.

System and method of automating the addition of programmable breakpoint hardware to design models

Abstract: Hardware logic for generating breakpoint signals based on state changes in observed (“tagged”) hardware resource of a design under test is automatically generated and added to the simulation model of the design under test. These breakpoints halt simulation when a user programmable event, such as an assertion, test-case failure, or trigger occurs. Allowing the end-user to define the register values used in comparison to or timing of tagged resources, results in breakpoints that can be created, changed, enabled, or disabled without rebuilding the simulation model. Because the breakpoint logic is in-circuit, it takes full advantage of the acceleration made possible by hardware simulators, while providing an interactive environment for both functional hardware verification and software development on the simulated hardware mode.

Hardware linked product key

Abstract: Software piracy is inhibited by distributing unique software product keys operable in hardware or a hardware linked device. Software operable on the hardware requires the presence of the key in or accessible via the hardware, and operates only if the hardware product key is present. A method for securing software includes the steps of: providing a plurality of unique product activation keys designed for access by a computer program and delivering the keys to a hardware manufacturer. The computer program seeks at least one of said plurality of unique product activation keys in the read only memory device.

Hardware/software interface for multi-dimensional processor arrays

Abstract: On most recent systems on chip, the performance bottleneck is the on-chip communication medium, bus or network. Multimedia applications require a large communication bandwidth between the processor and graphic hardware accelerators, hence an efficient communication scheme using burst mode is mandatory. In the context of data-flow hardware accelerators, we approach this problem as a classical resource-constrained problem. We explain how to use recent optimization techniques so as to define a conflict-free schedule of input/output for multi-dimensional processor arrays (e.g. 2D grids). This schedule is static and allows us to perform further optimizations such as grouping successive data in packets to operate in burst mode. We also present an effective VHDL implementation on FPGA and compare our approach to a run-time congestion resolution showing important gains in hardware area.

Hardware checkpointing system

Abstract: A method and a system for recovering a computing system's hardware state. In one embodiment the method includes simulating a removal of a hardware device from a bus of the computing system, simulating the replacement of the hardware device onto the bus and executing a configuration program for the computing system. In another embodiment the removal of the hardware device from the bus is simulated following a detection of a fault in the computing system. In another embodiment the simulating of the removal of the hardware device from the bus includes modifying a list of hardware devices connected to the bus by removing the hardware device from the list.

Use of a soft-core processor in a hardware/software codesign laboratory

Abstract: This paper describes our experience to date and current plans for a senior-level microelectronics laboratory course on hardware/software codesign. The course utilizes an open-source, soft-core processor deployed on the FPX platform as an integral component of the students' designs. Students write software to execute on a Leon SPARC-compatible processor and write VHDL to implement hardware-accelerated computational functions in FPGA hardware.

System for Configuring Hardware in a Downhole Tool

Abstract: A system for loading a hardware configuration into downhole configurable hardware includes a surface control unit in communication with a downhole tool string component over a downhole network. The surface control unit initially has the hardware configuration and transmits it through the downhole network to the configurable hardware. The hardware configuration is implemented in the configurable hardware. The configurable hardware is preferably an FPGA.

A Plug and Play GNC Architecture Using FPGA Components

Abstract: The goal of Plug and Play, or PnP, is to allow hardware and software components to work together automatically, without requiring manual setup procedures. As a result, new or replacement hardware can be plugged into a system and automatically configured with the appropriate resource assignments. However, in many cases it may not be practical or even feasible to physically replace hardware components. One method for handling these types of situations is through the incorporation of reconfigurable hardware such as Field Programmable Gate Arrays, or FPGAs. This paper describes a phased approach to developing a Guidance, Navigation, and Control (GNC) architecture that expands on the traditional concepts of PnP, in order to accommodate hardware reconfiguration without requiring detailed knowledge of the hardware. This is achieved by establishing a functional based interface that defines how the hardware will operate, and allow the hardware to reconfigure itself. The resulting system combines the flexibility of manipulating software components with the speed and efficiency of hardware.

A hardware implementation of the cell matrix self-configurable architecture: the Cell Matrix MOD 88/spl trade/

Abstract: A hardware version of the Cell Matrix self-configurable architecture is described. Its main features are summarized, and the advantages of the hardware system over software simulators are discussed. Further details of the MOD 88's operation and software are given. An overview of the relation of the Cell Matrix and the MOD 88 to the field of evolvable hardware is given. Research and educational ideas are presented. A freely available, shared, online MOD 88 system is discussed.

Exploiting register-usage for saving register-file energy in embedded processors

Abstract: Low power register file design plays an important role in an embedded processor. In this paper, we exploit register-usage in a program to find out unused registers, and turn these unused registers into low power mode by annotating power-controlling instructions. The whole work is performed by applying the hardware/software co-design principle. For the hardware part, we propose a voltage-scaling control logic to supply voltages for each register. For the software part, we propose a power-controlling-code annotation approach to determine the voltage scaling behavior for each register. Simulation results show that the proposed approach outperforms the other related approaches in terms of the energy-delay product.

Deterministic microcontroller with context manager

Abstract: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided.

Device and method for data-processing

Abstract: A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.

System and method for online specification of a system

Abstract: A system and method for online configuration of a measurement device for a measurement system. The user accesses a server with a client computer over a network and specifies a desired measurement task. If the user lacks the hardware required to perform the task, hardware specifications and configuration software and/or data specific to the user's application, i.e., to perform the task, are sent to a manufacturer, who pre-configures the hardware with the configuration software and/or data to perform the task and sends the pre-configured hardware to the user. The hardware may be re-configurable hardware, such as a programmable hardware element or processor/memory based device. Configuration software and/or data for configuring the user's measurement system hardware (and/or software) to perform the desired task may also be sent to the user. The configuration software sent to the user may comprise a graphical program usable by the measurement system to perform the task.

Universal graphic adapter for interfacing with UGA hardware via UGA virtual machine and means for abstracting details of the UGA hardware

Abstract: The subject invention relates to a Universal Graphics Adapter (UGA) that is a hardware-independent design that encapsulates and abstracts low-level graphics hardware in a standard manner through firmware. UGA is a firmware standard, intended to wrap existing or planned hardware, including VGA. UGA does not require the use of real-mode assembly language, direct hardware register, or frame buffer access to program, thus providing advantages over conventional systems. UGA supports basic drawing operations, continuous display modes, and power management. As a firmware-based standard, UGA facilitates updating a system to support both evolving and new hardware features.