Showing papers on "Integrating ADC published in 1995"

Transient voltage protection circuit for electrical power converters

Abstract: A transient over-voltage protection circuit includes a normally closed switch connected between a rectifier circuit and a DC to DC converter. This switch is caused to partially open when the voltage input to the DC to DC converter exceeds a predetermined value, thereby protecting the DC to DC converter from input voltages that exceed the converter's operational limits. The switch is returned to its normally closed state when the level of voltage input to the converter drops below a predetermined lower value. A capacitor connected across the input terminals of the converter is charged up when the switch is closed and functions to supply power to the DC to DC converter when the switch is in its partially opened or current limit state.

A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS

Abstract: An analog-to-digital converter (ADC) circuit is proposed that utilizes the linearity of the single-bit first-order sigma-delta in a first mode technique. In a second mode, successive approximation is used to convert the remaining voltage from the first conversion to increase the resolution without significantly increasing the conversion time. Both operations can be made in the same hardware, and only a counter is needed as decimation filter so that the converter becomes both area and power efficient. A channel of the ADC implemented in standard CMOS occupies an area of 40/spl times/1640 /spl mu/m/sup 2/. The control logic and reference voltage generation circuits, common for the ADC array, occupy a similar area. Estimated power consumption per ADC channel is about 0.5 mW including reference voltage generation. The conversion speed per ADC channel is 12.8 ksamples/s at a clock rate of 3.4 MHz. The ADC concept is suitable whenever a high resolution at a moderate speed is needed.

A three-switch high-voltage converter

Abstract: A novel three-switch HV converter derived from the Cuk converter is presented. This converter can operate into a capacitor-diode voltage multiplier, which offers simpler structure and control, higher efficiency, reduced EMI, size and weight savings than traditional switched-mode regulated voltage multipliers. Two significant advantages are the continuous input current and easy isolation extension. The new converter is experimentally verified. Both the steady state and dynamic theoretical models are correlated well with the experimental data. >

Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method

Abstract: An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM (108) is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90 % of the input analog signal voltage. A high voltage ramp (112) is applied to the memory cell to set the voltage of the cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached (104). Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. The 'read-while writing' operations are performed a predetermined number of times to achieve programming of the cell.

A three-phase series-parallel resonant converter-analysis, design, simulation, and experimental results

Abstract: A three-phase DC-to-DC series-parallel resonant converter is proposed and its operating modes for a 180/spl deg/ wide gating pulse scheme are explained. A detailed analysis of the converter using a constant current model and the Fourier series approach is presented. Based on the analysis, design curves are obtained and a design example of a 1-kW converter is given. SPICE simulation results for the designed converter and experimental results for a 500-W converter are presented to verify the performance of the proposed converter for varying load conditions. The converter operates in lagging power factor (PF) mode for the entire load range and requires a narrow variation in switching frequency, to adequately regulate the output power.

Charge redistribution analog-to-digital converter with system calibration

Abstract: A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Microprocessor controlled sensor signal conditioning circuit

Abstract: A method and apparatus for measurement signal compensation comprises providing an analog-to-digital converter that includes a dual slope integrator. A microprocessor controls the reference voltage applied to the integrator. An amplifier having a switchable gain, controls the amplification of the input signal to the integrator during the various phases of integration. An off-set compensation value is stored in a memory device for providing off-set compensation by charging a capacitor connected to the integrator. A full-scale rough adjust value is also stored on the memory device and is used as a specific reference to produce a reference voltage that is, in turn, used in the integrator during the negative slope phase. During the positive slope phase, the integration time is controlled by means of full-scale fine adjust values. The temperature dependent full-scale fine adjust values are produced from the preprogrammed values in memory by using interpolation techniques. For example, in the case of a piezo-resistive pressure sensor application, the temperature sensing is undertaken by intermittently sensing the temperature of the measuring circuitry using an on-chip temperature sensor, or the temperature at the top of the sensor bridge using the pressure sensors, or by using external temperature sensors. Pressure measurement depends on the plus and minus outputs of the sensor bridge, and measurement is performed by appropriately adjusting the integrator to provide for temperature compensation during the analog-to-digital conversion process.

Analog-to-digital converter with local feedback

Abstract: An analog-to-digital converter is provided for converting an analog signal to a digital signal and for maintaining a linear gain relationship therebetween, regardless of the analog input signal full scale voltage. The analog-to-digital converter utilizes oversampling and delta-sigma techniques within a cascaded, multiple order circuit arrangement. A local feedback loop is coupled across the output and input nodes of at least one latter order integrator within the first stage and subsequent stage of the cascaded analog-to-digital converter. The local feedback loop monitors the output from the connected integrator and modifies that output through local feedback to ensure the input level of the second and subsequent stages is optimally maintained. Proper scaling of the latter stages ensures that quantization noise caused by the first stage is cancelled, and that any and all direct noise leakage from the first stage does not enter into the digital signal produced by the noise cancellation circuit.

Analog-to-digital converter and sensor device comprising such a converter

Abstract: The present invention relates to a periodically integrating analog-to-digital converter and a sensor device comprising such a converter. The analog-to-digital converter comprises a measured-value-to-pulse-amount converter, i.e. a sigma-delta converter of the first order that is reset to zero before each new period, and a digital counter for the number of feedback signals of known reference value in the measured-value-to-pulse-amount converter. This constitutes a rough measure of the input signal. It further comprises an analog-to-digital converter which converts the residual value of the measured-value-to-pulse-amount converter at the end of the period to a digital value, and an adder which adds this value to the output signal from the digital counter, resulting in a more accurate measure of the input signal.

Gated integrator with signal baseline subtraction

Abstract: An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

Sampled-data interface circuit for capacitive sensors

Abstract: In one embodiment of the present invention, a sensing system utilizing a capacitive sensor includes an integrator which is connected to the sensor and has an operational amplifier and an integrator capacitor, a reference voltage source, a clock generator generating a 3-phase clock, and a number of switches. The switches, during the first phase of the clock connect the sensor capacitors to the reference voltages and cause the capacitors to become charged, and connect the output and the input of the amplifier cand cause the integrator to be shorted. During the second phase, the switches connect the sensor capacitors contained in the capacitive sensor to the ground and disconnect the input of the integrator from the output of the integrator to cause the charges on the sensor capacitor to be transferred to the integrator capacitor. During the third phase, the switches connect the sensor capacitors to the output of the integrator, and the integrator capacitor to the groung so that the charge is transferred from the integrator capacitor to the sensor capacitors of the capacitive sensor. Thus, the output of integrator becomes a scaled version of the difference over the sum of the sensor capacitors. The scale factor can be adjusted by adjusting the reference voltage.

Current-input, autoscaling, dual-slope analog-to-digital converter

Abstract: A current-input, autoscaling, dual-slope A/D converter includes means for adjusting the integration period of the input current to effectively adjust a scale factor associated with the converter. An integrator circuit of the converter includes means for precharging an integration capacitor of the integrator circuit to an off-set voltage associated with an amplifier of the integrator circuit, so as to effectively eliminate integration error due to the off-set voltage. A PMOS switching transistor associated with precharging the integration capacitor is formed in an n-well biased to a voltage approximately equal in magnitude to a voltage held across the integration capacitor, so as to minimized leakage current from the capacitor through the PMOS switching transistor.

System for calibrating analog-to-digital converter

Abstract: A calibrating system calibrates an analog-to-digital converter which has an integrator (20) and first and second reference current sources (IL, IS). A quantity of charge is accumulated in the integrator (20). The quantity of charge is removed from the integrator (20) by applying the first and second reference currents (IL, IS) to the integrator (20) for first and second time periods until the accumulated charge reaches a threshold level. The quantity of charge is reaccumulated in the integrator (20) and again removed by applying the first and second reference currents (IL, IS) for third and fourth time periods wherein the first and second time periods are different from the third and fourth time periods. The relative magnitude of the first and second reference currents (IL, IS) is determined based on the first, second, third and fourth time periods.

Gated integrator preamplifier for infrared data networks

Abstract: A method and apparatus for receiving infrared signals are provided. The circuit includes preamplifier that includes an integrator that charges based on light detected by a photodiode. The circuit includes a warning circuit that generates a warning flag when the charge on the integrator exceeds a predetermined level. To prevent the integrator from saturation, digital logic resets the preamplifier by dumping the charge on the integrator in response to the warning signal. The digital logic is also configured to reset the integrator at predetermined intervals. When the incoming signal is encoded using pulse position modulation, the interval at which the integrator is reset is the length of a single time slot in the pulse position modulation frame. A sample and hold circuit is provided to hold a previous output of the preamplifier. The difference between the previous output of the preamplifier and the current output of the preamplifier is compared with a threshold voltage to detect pulses on the incoming signal.

Linear tunable Gm-C integrator

Abstract: A time-continuous tunable Gm-C integrator including a "super Gm" differential input stage (O1; MI1/O2, MI2) and using linear and constant degeneration resistors (R1/R2) for obtaining the most optimal linear input-voltage to output-current conversion is tunable in a time-continuous manner. The integrator is provided with three tuning CMOS transistors (MU1, MU2, MU3) controlling the integrating currents flowing between the input stages and from the input stages towards the outputs (OP/ON). By a suitable control of the tuning transistors and owing to the fact that the voltage swing across the latter is small, it is possible to obtain a perfectly linear transconductance (Gm) characteristic over the whole operating range of the integrator.

Pulse width modulated amplifier

Abstract: A class-D pulse width modulated amplifier. The amplifier includes a current switch, an integrator and a comparator connected in a feedback loop. The feedback loop generates an ultrasonic frequency carrier which is utilized in the pulse width modulation of an audio input signal. In one embodiment a current switch and an audio input source are in electrical communication with an integrator. The output signal of the integrator is the input signal to a phase split differential output comparator having hysteresis. The differential output signals of the comparator are the input signals both to a load and to the current switch, thereby completing the feedback loop. In one embodiment the current switch includes compression circuitry.

Overcurrent detecting device for a DC motor

Abstract: An overcurrent-detecting device for a DC motor includes a converter for changing a current signal to a voltage signal in a motor; an integrator for comparing an input signal from the convertor with a first reference voltage, and for integrating an excessive value of the reference voltage; and a detector for comparing an input signal from the integrator with a second reference voltage, sensing an overcurrent when the input signal is smaller than the second reference voltage, and outputting a resultant signal. In detecting an overcurrent of the DC motor, the device integrates a higher voltage than a reference voltage, and then detects an overcurrent when the DC motor is constrained. This overcurrent-detecting device, therefore, can be exactly operated by a small-capacity capacitor without incorrect operation with respect to noise and abrupt overload, while not permitting forced operation in the initial operation, and also can be operated quickly in response to an actual mechanical constraint having a reasonable overcurrent.

Data independent loading of a reference in a discrete time system

Abstract: A 1-bit discrete time digital-to-analog converter which samples a reference voltage and ground potential onto two charging capacitors during a sample phase of each sampling period, and which transfers the charge on one of the capacitors, as determined by a digital input signal, onto an integrator during a transfer phase of said sampling circuit, draws current from the reference voltages which is independent of the data into the converter. The improvement comprises the addition of at least one phase to each sampling period so that the current drawn from said reference voltage is essentially independent of said digital input signal.

Small-signal modelling of the half-bridge complementary-control DC-to-DC converter

Abstract: The half-bridge complementary-control converter has been proposed as a low-output voltage DC-to-DC converter due to its excellent features (efficiency around 90% at as low output voltage as 3.3 volts). A study of the dynamics of this converter is proposed in this paper. Thus, a small-signal average model has been obtained. From it, transfer functions between duty cycle and output voltage and between input and output voltages have also been obtained, and some simplifications and design rules have been proposed to facilitate the design of the feedback loop.

Double-input analog-to-digital converter using a single converter module

Abstract: The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

Inverter circuit utilizing a frequency synchronization device

Abstract: An inverter circuit that can provide a stable AC power supply by synchronizing the switching operations of a DC-to-DC converter and a DC-to-AC converter which constitute the inverter circuit with each other The inverter circuit includes an error amplifier for comparing a feedback control voltage from the DC-to-AC converter with a reference voltage and amplifying the resultant voltage of comparison, a frequency synchronizing section for providing a sawtooth voltage synchronized with the frequency of a ripple voltage occurring at an output terminal of the DC-to-DC converter due to the switching operation of the DC-to-AC converter, and a comparator for comparing the sawtooth voltage with the output voltage of the error amplifier, and providing a switching control signal to the DC-to-DC converter as result of comparison

D/A converter with constant gate voltage

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier (V1) and a p-type FET (X9), where the drain of the p-type FET is fed back to a non-inverting (NINV) input of the amplifier, and a reference voltage (VREF) is applied to an inverting input (INV) of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor (R1) is connected to the drain of the p-type FET.

Voltage to frequency converter

Abstract: A voltage to frequency converter including a first selector (SW₃,SW₄) for receiving an input voltage and for generating an input current based on the control signal (Sc). The input current is proportional to the input voltage or an inverse polarity input voltage when the control signal designates plus, or minus integration period, respectively. The converter further includes a second selector (SW₂,SW₁) for generating a reference current such that the reference current is on/off controlled based on the selection signal and a polarity of the reference current is determined by the control signal (Sb), and an integrator (1) for integrating a resultant current of the input current and the reference current to obtain an integrated voltage. The integrator integrates the resultant current complementarily in a forward or in a reverse direction. The converter also includes a comparator (2) for comparing the integrated voltage and a reference voltage to generate a comparison output signal, a selection signal generator (3A) for generating the selection signal based on the comparison output signal and the control signal, a control signal generator (4) for generating the control signal based on the selection signal, and an output circuit for generating the selection signal as an output signal of the converter having a frequency corresponding to the input voltage.

CMOS low-voltage rail-to-rail V-I converter

Abstract: A low-voltage rail-to-rail voltage/current-controlled voltage-to-current converter, which is first order insensitive to the threshold voltage variation, is introduced. This circuit can be used as a basic building block to construct low-voltage current-mode analog computational circuits, which can perform functions such as square-rooting, squaring, multiplication, sum of squares, difference of squares and etc. First, a low-voltage N-type V-I converter cell is presented. A complementary P-type V-I converter is used in parallel with the N-type V-I converter to achieve common-mode rail-to-rail operation. Moreover, to achieve a constant transconductance of the V-I converter, P-type and N-type bias control circuits are utilized to provide bias currents. Finally, SPICE simulations results are given. The variation of the transconductance is shown to be less than 5%.

Experimental results for the small-signal study of the pwm boost dc–dc converter with an integral-lead controller

Abstract: An experimental verification of previously derived small-signal low-frequency open- and closed-loop characteristics and step responses of a voltage-mode-controlled pulse-width-modulated (PWM) boost DC–DC converter is presented. The Bode plots of the voltage transfer function of the control circuit, the converter and the PWM modulator, the open-loop control-to-output and input-to-output transfer functions, the loop gain, and the closed-loop control-to-output and input-to-output transfer functions are measured. The step responses to the changes in the input voltage, the duty cycle, and the reference voltage are measured. The theoretical results were in good agreement with the measured results. The small-signal model of the converter is experimentally verified.

Improved full bridge zero voltage switched phase shift DC/DC converter using a secondary clamped inductor

Abstract: This paper presents the analysis, simulation and experimental results of a full-bridge zero voltage switched phase shift DC-DC power converter, working with an internal frequency of 250 kHz, with an output power of 1 kW. The power converter uses a two windings inductor with the secondary connected to the output by means of two clamping rectifier diodes, to allow resonant commutation of the passive to active leg of the power converter. With this process it is possible to improve the efficiency of the power converter.

Voltage monitor device

Abstract: PROBLEM TO BE SOLVED: To precisely monitor voltage variation and easily vary a comparison voltage. SOLUTION: This device is equipped with a circuit (resistance 1 and Zener diode 2) which generates a constant voltage Vz lower than an analog input voltage (e.g. Vcc) to be monitored from the analog input voltage and an analog- digital converter 3. Then the analog input voltage to be monitored is supplied to a reference voltage terminal 3s reversely to an ordinary method for using the A/D converter and the constant voltage Vz is supplied to an analog input terminal 3a. Further, this device is equipped with a CPU 4 which monitors variation in th digital value outputted from the analog-digital converter.

Charge integrating-type analog to digital converter employing rapid charge neutralization and N-bit feedback

Abstract: A Sigma Rho A/D converter (10) includes a transconductance element (R) having an input node for receiving an input voltage signal V in and an output node providing an analog current I in ; a charge integrator (12) having an input coupled to the output node, the charge integrator having feedback provided by an integrating capacitor C and an output node providing an output signal V o ; and a clocked voltage comparator (14) having an input coupled to V o for comparing V o to a reference potential. An output of the comparator updates in response to an occurrence of a first clock signal CLK1. A current sink (16) is switchably coupled to the output node of the transconductance element as a function of the logic state of the output of the comparator. A sum and dump accumulator (18) has an input coupled to the output of the comparator and an output having N output bits, and operates to sum together individual ones of first logic states and outputs a sum value on the N output bits in response to an occurrence of a second clock signal CLK2. The frequency of CLK2 is equal to CLK1/N. A unique bit stream is output from the comparator (14) for each allowed input voltage such that complete information about the input voltage is embedded within, or encoded by, the bit stream output from the comparator.

Analysis and prediction of regulation in a multiple-output current-mode controlled DC-to-DC converter

Abstract: A technique is developed for predicting the closed-loop steady state output voltage regulation of a multiple-output current-mode controlled converter. The proposed model accounts for the current loop, the voltage loop, and the integrator in the compensation scheme. This method allows tradeoffs with respect to regulation between different components or feedback configurations to be evaluated during the design of a converter. Experimental verification on a three-output current-mode controlled push-pull converter with single output voltage feedback is provided. >