Showing papers on "Logarithmic number system published in 2013"

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters

Abstract: This paper presents techniques for low-power addition/subtraction in the logarithmic number system (LNS) and quantifies their impact on digital filter VLSI implementation. The impact of partitioning the look-up tables required for LNS addition/subtraction on complexity, performance, and power dissipation of the corresponding circuits is quantified. Two design parameters are exploited to minimize complexity, namely the LNS base and the organization of the LNS word. A roundoff noise model is used to demonstrate the impact of base and word length on the signal-to-noise ratio of the output of finite impulse response (FIR) filters. In addition, techniques for the low-power implementation of an LNS multiply accumulate (MAC) units are investigated. Furthermore, it is shown that the proposed techniques can be extended to cotransformation-based circuits that employ interpolators. The results are demonstrated by evaluating the power dissipation, complexity and performance of several FIR filter configurations comprising one, two or four MAC units. Simulations of placed and routed VLSI LNS-based digital filters using a 90-nm 1.0 V CMOS standard-cell library reveal that significant power dissipation savings are possible by using optimized LNS circuits at no performance penalty, when compared to linear fixed-point two's-complement equivalents.

Simplified floating-point division and square root

Abstract: Digital Signal Processing (DSP) algorithms on low-power embedded platforms are often implemented using fixed-point arithmetic due to expected power and area savings over floating-point computation. However, recent research shows that floating-point arithmetic can be made competitive by using a reduced-precision format instead of, e.g., IEEE standard single precision, thereby avoiding the algorithm design and implementation difficulties associated with fixed-point arithmetic. This paper investigates the effects of simplified floating-point arithmetic applied to an FMA-based floating-point unit and the associated software division and square root operations. Software operations are proposed which attain near-exact precision with twice the performance of exact algorithms and resolve overflow-related errors with inexpensive exponent-manipulation special instructions.

Low complexity QR-decomposition architecture using the logarithmic number system

Abstract: In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink precoding environment for 4×4 and 8×8 multi-antenna wireless communication systems. In addition, the results are compared to default CORDIC-based architectures. In a second step, HDL implementation as well as logical and physical CMOS synthesis are performed. The comparison to actual references highlight our approach as highly efficient in terms of hardware complexity and accuracy.

Logarithmic arithmetic as an alternative to floating-point: A review

Abstract: The logarithmic number system (LNS) has found appeal in digital arithmetic because it allows multiplication and division to be performed much faster and more accurately than with the widely used floating-point (FP) number formats. We review the sign/logarithmic number system and present a comparison of various techniques and architectures for performing arithmetic operations efficiently in LNS. As a case study, we describe the European logarithmic microprocessor, a device built in the framework of a research project launched in 1999. Comparison of the arithmetic performance of this microprocessor with that of a commercial superscalar pipelined FP processor leads to the conclusion that LNS can be successfully deployed in general-purpose systems.

ASIC based logarithmic multiplier using iterative pipelined architecture

Abstract: Multiplication is a significant process in digital signal processing algorithms. These algorithms involve large number of multiplications, which is time consuming. In digital signal applications time is more important as compared to accuracy. In this paper a simple and efficient architecture of multiplier is proposed which uses adders, shifters, encoders and decoder etc. that consume less area, time and power. The multiplication is based on Mitchell's algorithm. This multiplier gives arbitrary accuracy but with only two iterations it gives very less error that is limited to 2% which is tolerable in digital signal algorithms. This multiplier is implemented in ASIC using SOC encounter and NCSIM simulator in Cadence with 180nm technology for 16 bit operands at 12.5 MHz frequency.

Improved DNA-sticker arithmetic: tube-encoded-carry, Logarithmic Number System and Monte-Carlo methods

Abstract: The sticker model of computation, implemented using robotic processing of DNA, manipulates in parallel many bitstrings, called strands, that are contained in a limited number of tubes. Prior sticker arithmetic algorithms, patterned on digital-electronics, generate carry bits in the strand, either wasting bits or using a clear operation (with problematic biochemical implementation). The novel addition algorithm here does not need to record the carry. Instead, which tube holds a particular strand implicitly encodes the carry. The speed and number of tubes are half that of prior approaches. Further encoding data in the Logarithmic Number System (LNS) allows such integer operations to perform cost-effective real multiplications, divisions and roots. An example LNS Euclidian norm is more efficient than prior methods, assuming perfect operations. Unfortunately, DNA-stickers are unreliable. This paper uses sticker unreliability as a source of randomness to implement Monte-Carlo (MC) arithmetic (previously fabricated in silicon at the cost of pseudo-random generators). With stickers, the randomness is free. MC engineering mimics natural systems using unreliable but redundant components. Here, MC randomness is only useful in low-order bits. Multiple re-testing of the same bit ("refinement") trades improved reliability for slower operation using more tubes. Simulations (with different sizes, probabilities and refinement) show that increasing refinement as a function of bit position allows imperfect implementations to achieve suitable MC strand-error distributions, predicting 1000x speed-mass advantage of sticker-MCLNS over conventional supercomputers.

Base-N logarithm implementation on FPGA for the data with random decimal point positions

Abstract: Logarithmic transformation is an important part of many digital signals processing system, especially in the fields of instruments design. This paper gives details on a simple way based on CORDIC algorithm and the idea of data initialization to implement logarithmic transformation. Given the number of bits for input data, we can get the corresponding base-N logarithmic results after we specify their decimal point positions at will. The logarithmic converter introduced by this paper is able to support the logarithmic transformation of data with the number of bits up to 48.

Hybrid logarithmic number system arithmetic unit: A review

Abstract: Logarithmic number system (LNS) arithmetic has the advantages of high performance and high-precision in complex function computation. However, the large hardware problem in LNS addition/subtraction computation has made the large word-length LNS arithmetic implementation impractical. In this paper, the concept of merging the LNS and Floating Point (FLP) operation into a single arithmetic logic unit (ALU) that can execute addition/subtraction and division/multiplication more faster, precise and less complicated has been reviewed. The advantages of using hybrid system were highlighted while comparing and explaining about FLP and LNS.

A logarithmic approach to energy-efficient GPU arithmetic for mobile devices

Abstract: Graphic processing units (GPUs) have emerged as useful components in the realization of high-performance and cost-effective digital systems for numerically intensive applications, from simple personal devices to large-scale supercomputers. In this paper, we consider GPUs that incorporate energy-efficient logarithmic arithmetic units. After analyzing numerical errors arising from such an implementation scheme, we present a simple fine-tuning of the design to reduce the worst-case error.

Low level source code optimizing for single/multi/core digital signal processors

Abstract: Paper presents the optimized implementation of the digital signal processing algorithms (real and complex Fast Fourier Transforms) for the specific hardware architecture. The algorithms' source codes were optimized at low level, while all redundant operations (e.g. branching instructions) were avoided. Contrary to results compiled from the high level codes, time consuming load/store operations were considerably eliminated as well and temporal data were stored in the general purpose registers. Contrary to other implementations, the several calls of the identical functions (but with shared data) provide a reducing of the processor idle states. The TMS320C6748 and TMS320C6678 digital signal processors with the Very Long Instruction Word architecture were used for the implementation of proposed functions. The average duration of FFT optimized functions is between five CPU cycles for four real values and 44 CPU cycles for sixteen real values, respectively.

The Denormal Logarithmic Number System

Abstract: Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almost-constant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The conventional Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. Moderate-precision addition in SLNS uses table lookup with properties similar to FP (including underflow). This paper proposes a new number system, called the Denormal LNS (DLNS), which is a hybrid of the properties of FXNS and SLNS. The inspiration for DLNS comes from the denormal numbers found in IEEE-754 (that provide better, gradual underflow) and the μ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. A wide gradual underflow range acts like FXNS; a narrow one acts like SLNS. Simulation of an FFT application illustrates a moderate gradual underflow decreasing bit-switching activity 15% compared to underflow-free SLNS, at the cost of increasing application error by 30%. DLNS reduces switching activity 5% to 20% more than an abruptly-underflowing SLNS with one-half the error. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel ALU to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26%.

A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications

Abstract: As the evolution of smart phone, 3D graphics become more and more important in mobile computing systems. Within 3D graphics, logarithmic arithmetic is usually utilized to simplify multiplication, division, and power operations. In this paper, we propose a low-error and Rom-free logarithmic arithmetic unit for 3D graphics applications. The logarithmic arithmetic unit applies non-uniform regional linear interpolation and compensation method for logarithmic converters. According to experiment results, proposed 2-region logarithmic converter reduces 48.0% error range and 42.1% percent error. 21.6% area and 13.8% power consumption are gained.

A comparative analysis between logarithmic number system and floating-point ALU

Abstract: A B S T R A C T The ease and accuracy of executing the multiplication and division operations by using either fixed-point addition or subtraction is what makes the logarithmic number system an attractive option. However, its main drawback is the complexity of performing addition and subtraction operations. In this paper, an analysis is carried out to compare the current state-of-the-art logarithmic number system and floating-point. The results predominantly show that the logarithmic number system offers better speed, accuracy and power-efficiency than floating-point. A new proposal for logarithmic addition and subtraction using a co-transformation method is presented, with the aim of improving its performance further.

Circuit Design Residue Logarithmic Number System (RLNS) Using the One-Hot System

Abstract: In this study, we proposed high speed adder and low power and secure for module set {2 n -1, 2 n , 2 n +1} where we have provided to achieve maximum speed circuits for addition and subtraction computational method called the One-hot has been used where the delayed implementation using this method is that the size of a transistor in comparison with other previous implementations has improved dramatically. Another benefit of One-hot having a simple structure and regular implementation of the minimum power dissipation is the use of the Residue Logarithmic Number System arithmetic circuit with a balance can be very useful.

Improved Addition and Subtraction in Logarithmic Number System: Technique and Analysis

Abstract: Logarithmic Number System (LNS) Fixed Point (FXP) Logarithmic Number System (LNS) is an alternative beside Floating Point (FLP) when an application requires a large dynamic range in the number processed. It allows simple implementation of multiplication and division using a Fixed Point (FXP) method without rounding error. In contrast, LNS addition and subtraction become more complex procedure. Therefore over the year, difference ways of improving the addition and subtraction function have been purposed. In this paper several techniques have been discussed and analysed such as direct lookup table, interpolation, table partitioning and co-transformation for approximating LNS addition and subtraction.

Arithmetic circuit for calculating correction value

Abstract: An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value.