Showing papers on "Master clock published in 2000"

Clock generation and distribution for the first IA-64 microprocessor

Abstract: The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

Clock-gating and its application to low power design of sequential circuits

Abstract: This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip flops to generate a derived clock for each flip flop in the circuit. A technique for clock gating is also presented, which generates a derived clock synchronous with the master clock. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.

Apparatus and method for SCDMA digital data transmission using orthogonal codes and a head end modem with no tracking loops

Abstract: A system for bidirectional communication of digital data between a central unit and a remote unit wherein the need for tracking loops in the central unit has been eliminated. The central unit transmitter generates a master carrier and a master clock signal which are used to transmit downstream data to the remote units. The remote units recover the master carrier and master clock and synchronize local oscillators in each remote unit to these master carrier and master clock signals to generate reference carrier and clock signals for use by the remote unit receiver. These reference carrier and clock signals are also used by the remote unit transmitters to transmit upstream data to the central unit. The central unit receiver detects the phase difference between the reference carrier and clock signals from the remote units periodically and adjusts the phase of the master carrier and master clock signals for use by the central unit receiver to receive the upstream data.

Sample rate conversion for software radio

Abstract: Software radio terminals must be able to process many various communications standards. These standards are generally based on different master clock rates and thus employ different bit/chip rates. The most obvious solution to cope with the diversity of master clock rates in one terminal is to provide a dedicated master clock for each standard of operation. Not only too costly, this kind of solution limits the applicability of a realized terminal. Hence, it is much more elegant to run the terminal on a fixed clock rate, and perform digital sample rate conversion controlled by software.

Synchronizing clock signals in wireless networks

Abstract: A communications system extends over a cellular region formed of a plurality of wireless cells where each cell covers a portion of the cellular region. Each cell has a base station clock unit that facilitates reliable and accurate synchronization with other clocks units in other cells using a master clock signal from a global positioning system (GPS) or other accurate frequency source. The clock unit in each cell includes a local clock providing a local clock signal for clocking the cell. A master clock source provides one or more master clock signals and a clock synchronizer receives the master clock signals and forms a synchronizing master clock signal for synchronizing the local clock signal. In one or more of the wireless cells of the communication system, the clock unit is a master clock unit which includes a clock distributor for distributing a distributed master clock signal to one or more other wireless cells having slave clock units.

Dynamic evaluation logic system and method

Abstract: In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation. Once the output has stabilized, the global control unit will then instruct the system to accept and process the next set of input data. Thus, the global control unit in conjunction with the propagation detectors can dynamically provide varying evaluation time periods based on the needs of the input data. Whether the system needs longer or shorter evaluation times, the system will dynamically adjust the amount of time necessary to properly process that input and then move on to the next evaluation time for the next set of inputs.

Emulation system with multiple asynchronous clocks

Abstract: An emulation system includes a clock generation logic for generating multiple asynchronous clocks, where each generated clock's relative phase relationship with respect to all other generated clocks is strictly controlled to speed up the emulation logic evaluation. Unlike statically designed emulator systems known in the prior art, the speed of the logic evaluation in the emulator need not be slowed down to the worst possible evaluation time since the clocking is generated internally in the emulator and carefully controlled. The emulation system does not concern itself with the absolute time duration of each clock, because only the phase relationship among the multiple asynchronous clocks is important. By retaining the phase relationship (and the initial values) among the multiple asynchronous clocks, the speed of the logic evaluation in the emulator can be increased. The RCC clock generation logic comprises a clock generation scheduler and a set of clock generation slices, where each clock generation slice generates a clock. The clock generation scheduler compares each clock's next toggle point from the current time, toggles the clock associated with the winning next toggle point, determines the new current time, updates the next toggle point information for all of the clock generation slices, and performs the comparison again in the next evaluation cycle. In the update phase, the winning slice updates its register with a new next toggle point, while the losing slices merely updates their respective registers by adjusting for the new current time.

Assessment of GPS carrier-phase stability for time-transfer applications

Abstract: We have conducted global positioning system (GPS) carrier-phase time-transfer experiments between the master clock (MC) at the U.S. Naval Observatory (USNO) in Washington, DC and the alternate master clock (AMC) at Schriever Air Force Base near Colorado Springs, Colorado. These clocks are also monitored on an hourly basis with two-way satellite time-transfer (TWSTT) measurements. We compared the performance of the GPS carrier phase and TWSTT systems over a 236-d period. Because of power problems and data outages during the carrier-phase experiment, the longest continuous time span is 96 d. The data from this period show agreement with TWSTT within /spl plusmn/1 ns, apart from an overall constant time offset (caused by unknown delays in the GPS hardware at both ends). For averaging times of a day, the carrier-phase and TWSTT systems have a frequency uncertainty of 2.5 and 5.5 parts in 10/sup 15/, respectively.

Model-based clock synchronization in networks with drifting clocks

Abstract: This paper examines a clock synchronization algorithm in which processors identify dynamic models of neighboring processor clocks. These models are then used as signature functions to develop a clock synchronization algorithm that functions in the presence of drifting clocks.

Self calibrating clocks for globally asynchronous locally synchronous systems

Abstract: We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local clock domain is made possible by stretching the local clock if a metastable condition could be encountered. Stretching the clock just requires the rising clock edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.

Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit

Abstract: A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.

Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel

Abstract: Precompensated NRZ-encoded data for writing to magnetic storage medium operates with multiple NRZI-to-NRZ decoders that are each supplied with a selectably-variable version of a master clock. The delayed versions of the master clock are stably produced by delay elements operating with D-flip flops and charge pumps in a delay-locked feedback loop. The direction of current supplied to or from a capacitor by the charge-pump during a cycle of delayed clock signal is controlled by the delayed clock signal for shaping the feedback signal to trigger appropriately the next cycle of the delayed clock signal. The duration of the selectable delay is adjusted by setting the amplitudes of the charge and discharge currents supplied by the charge-pump. Stable delayed versions of the master clock promote reliable conversions of NRZI data to write precompensated NRZ recordable data.

Synchronization and access of the nodes in a communications network

Abstract: A wireless network is provided with a method to eliminate the commonly encountered problems associated with the development of the master timing in a network According to the provided method, the master network timing is completely eliminated Accordingly, in an exemplary implementation of the present invention, each node of a network has its own master clock used for transmissions that is free running and not adjusted in any way Each node has also a receiver equipped with a mechanism to acquire and track the timing of all the network nodes that are within the communications range and that are permitted the access In essence there is no master network timing and each transmitter hops and transmits according to its master clock Furthermore, it is the responsibility of each receiver to track multiple timing separately for each hopping transmitter The provided method is suitable for a wide range of applications including wireless networks and in particular for networks using frequency hopping

Critical evaluation of the motorola m12+ gps timing receiver vs. the master clock at the united states naval observatory, washington, dc

Abstract: : The paper describes the challenge of calibrating a new GPS Timing receiver so that its timing performance can be characterized with traceability to true UTC. This effort involved development of a custom test bed with improved software, installing the test bed at USNO, calibrating all the elements if the USNO and test bed equipment, collecting the data, and data analysis. This test bed allows testing of four GPS Timing receivers simultaneously so that variations in the manufacturing process and "zero baseline" comparisons can be evaluated. The work was extended to include a test of the level of synchronicity obtained between receivers separated by a 21.5 km baseline.

Multiplexed synchronization circuits for switching frequency synthesized signals

Abstract: Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

System and method for providing master and slave phase-aligned clocks

Abstract: A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide a control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system. The second clock board is switched from being the slave clock source to the master clock source, while the third clock board is configured to operate as the slave clock source. The method provides a first clock signal as a master clock signal. A second clock signal is provided as a slave clock signal, with the slave clock signal phase aligned with the master clock signal. Upon a failure of either the master clock signal or the slave clock signal, a user is notified of the failure. Upon the failure of the first clock signal, the second clock signal is switched in place of the first clock signal as the master clock signal. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

Method and apparatus to synchronize a bus bridge to a master clock

Abstract: A method and apparatus for synchronizing a bus bridge to a master clock comprising receiving a time stamp packet at an input clock register of the bus bridge, comparing the value of the input clock register to the value of an output clock register of the bus bridge, obtaining an error value of the output clock register from the comparison, and determining whether the error value is below a predetermined threshold are described.

Clock slaving methods and arrangements

Abstract: In accordance with certain aspects of the present invention, an algorithm is provided that can be used to detect and track the difference between an on-host clock (i.e., “host clock”) and a remote clock (i.e., “reference clock”). As part of the algorithm, a scaling value is computed and tracked over time. The scaling value, when applied to the host clock, results in clock values that increase at substantially the same rate as the reference clock itself increases. Hence, the host clock will have been slaved to the reference clock.

Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method

Abstract: Multi-processor system including processors, a host-PCI bridge, and other devices which are connected to each other by a processor bus and a clock control bus for clock frequency adjustment. Each of the processors, a host-PCI bridge, and other devices operate in synchronism with others based on clocks generated by incorporated clock generation circuits. Each of the processors, a host-PCI bridge, and other devices dynamically execute clock frequency changing operations to the incorporated clock generation circuits by using at least the clock control bus in synchronism with others. Thus, the frequencies of clocks generated by each of the processors, a host-PCI bridge, and other devices can be dynamically changed in synchronism with others.

Reduction of power consumption with increased standby time in wireless communications device

Abstract: A method and apparatus for reducing power consumption of a receiver of a communications device that does not change the global hardware of the device and uses the current master clock to lower the clock frequency In an example embodiment, a method directed to reducing power consumption of a receiver of a communications device during an idle state The receiver has an internal power source and a corresponding base unit The method includes generating a clock signal that has an output frequency that varies, the frequency being higher in an active state and lower in an inactive state, such that the receiver consumes more power during the active state then when in the inactive state Power consumption by the receiver is reduced by dynamically and synchronously switching the clock frequency to a lower clock frequency Receiver power consumption is a function of the power consumed during the active and inactive states and the duration of the idle state

Method of synchronizing each local clock to a master clock in a data bus system

Abstract: A method of synchronizing each local clock to a master clock in a data bus system is described. In an embodiment, the data bus system includes a plurality of nodes each having a local clock. Initially, a clock source for each local clock is the respective local clock generator of each node. During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. If a node has a first identifier port, the node changes a clock source for its local clock from the local clock generator to a particular clock recovery circuit that is coupled to the first identifier port. In another embodiment, a clock source for each local clock is initially the respective multiple mode clock recovery circuit (MMCRC) operating in the unlocked mode. During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. If a node has a first identifier port, the node changes a clock source for its local clock from the MMCRC operating in the unlocked mode to the MMCRC operating in the locked mode, which is coupled to the first identifier port. The local clock of the root node serves as the master clock for synchronizing the local clocks of the other nodes.

High phase margin low power flip-flop

Abstract: An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.

System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes

Abstract: An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.

Method of synchronizing a reference clock of a ground station and a clock of a remote system

Abstract: The invention relates to a method of synchronizing a reference clock of a first ground station and a local clock of a remote system, in particular a satellite. It includes: a) acquisition in a first loop of synchronization between reference bursts received by the remote system and generated bursts synchronized with the local clock, b) detection of the recognition word of the reference bursts received by the first remote system and generation of a time window containing N pulses of the reference clock, c) acquisition of the average phase of said pulses and comparison with the phase of the local clock, and d) in a second loop, synchronization of the phase of the local clock with said average phase. The method can be reiterated to synchronize a second ground station with the first one via the remote system.

Rubidium clock sound velocity meter

Abstract: A precision sound velocity meter has been made by adding a high stability rubidium oscillator to pulsed ultrasound instrumentation, where its stability and low noise is utilized as a quality time scale and a master clock, to which major timing events such as sound excitation, scope triggering, and time measurements are synchronized Measuring operations are computer controlled A reproducibility of ±0005 m s−1 has been achieved in applications in research chemistry

Method and device for synchronisation of distant clocks to a central clock via satellite

Abstract: The invention relates to a method and device for synchronisation of one or more distant clocks (2) to a central clock (1) by means of a bi-directional satellite radio frequency link (9.1, 9.2). Suitable radio signal transmitters (8, 12) and receivers (5, 1) at both sides of the link exchange timing and data signals. From the time-difference measurements (6, 14) performed at both sides, a control signal is derived to adjust the distant clock, which is directly built into the remote ground station equipment (11), to be in synchronism with respect to time and frequency to the central clock by means of the Two-Way Satellite Time and Frequency Transfer (TWSTFT) method. The user has access to timing signals (18) which directly represent the time of the central clock (1). For data transmission, the same signals are used which are already used for the timing measurements. Hence, a system operating in real-time is established which makes available the information about the control-loop error (15, 16) at both sides of the system.

Delay locking high speed clock synchronization method and circuit

Abstract: A clock synchronizer circuit provides an internal clock signal for an integrated circuit that is synchronized to an external system clock signal, such that the internal clock integrated is aligned with and has minimal skew from the external system clock signal. The clock synchronizer circuit allows synchronizing of internal clocks of an integrated circuit with the external system clock having a period τ ck less than the cumulative delay of internal receiving and distribution circuits of the integrated circuit.

Method and apparatus for selecting a first clock and second clock for first and second devices respectively from an up-converted clock and an aligned clock for synchronization

Abstract: A method and apparatus for synchronizing clocks is provided that is flexible and compensates for process, voltage, and temperature (PVT) variations and other timing differences between two devices. The present invention includes producing an up-converted clock from a system clock, the up-converted clock having a frequency that is a multiple of the frequency of the system clock, producing an aligned clock from a data-aligned clock from a first device and a counter clock from a second device, producing a de-jittered clock, selecting a first reference clock to send to the first device from the up-converted clock, the aligned clock and the de-jittered clock, and selecting a second reference clock to send to the second device from the up-converted clock, the aligned clock and the de-jittered clock.

Low-power design of sequential circuits using a quasi-synchronous derived clock

Abstract: This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master clock and using it to isolate the flip flops in the circuit from the unwanted triggering action of the master clock. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.