Showing papers on "Master clock published in 2020"

Exploring the role of circadian clock gene and association with cancer pathophysiology.

Abstract: Most of the processes that occur in the mind and body follow natural rhythms. Those with a cycle length of about one day are called circadian rhythms. These rhythms are driven by a system of self-sustained clocks and are entrained by environmental cues such as light-dark cycles as well as food intake. In mammals, the circadian clock system is hierarchically organized such that the master clock in the suprachiasmatic nuclei of the hypothalamus integrates environmental information and synchronizes the phase of oscillators in peripheral tissues.The circadian system is responsible for regulating a variety of physiological and behavioral processes, including feeding behavior and energy metabolism. Studies revealed that the circadian clock system consists primarily of a set of clock genes. Several genes control the biological clock, including BMAL1, CLOCK (positive regulators), CRY1, CRY2, PER1, PER2, and PER3 (negative regulators) as indicators of the peripheral clock.Circadian has increasingly become an important area of medical research, with hundreds of studies pointing to the body's internal clocks as a factor in both health and disease. Thousands of biochemical processes from sleep and wakefulness to DNA repair are scheduled and dictated by these internal clocks. Cancer is an example of health problems where chronotherapy can be used to improve outcomes and deliver a higher quality of care to patients.In this article, we will discuss knowledge about molecular mechanisms of the circadian clock and the role of clocks in physiology and pathophysiology of concerns.

FPGA Implementation of a Synchronization Circuit for Arbitrary Trigger Sequences

Abstract: In several applications, the generation/acquisition of data sequences is triggered by an external signal. Frame jitter, i.e., random temporal variations between the trigger signal and the actual start of data generation/acquisition, produces errors and inaccuracies. When, in a digital approach, the trigger is sampled by the internal clock of the receiving system, an uncertainty corresponding to the clock period (e.g., 10 ns for a 100-MHz clock) is produced. For several sensitive applications, like, for example, radar interferometry or ultrasound velocimetry, this uncertainty cannot be tolerated, making difficult the synchronization of external instrumentation or separated apparatuses. The problem is theoretically solved by sharing a common master clock among instruments, but not all the systems allow this solution. In this article, a full digital synchronization circuit is proposed, which measures the phase difference between the input trigger and the next edge of its internal clock and generates a copy of the clock with a phase tuned on the input trigger. This way, for every trigger pulse, the clock is rephased and the frame jitter is reduced. The circuit accepts nonperiodic triggers, making it suitable for a wider range of applications. Experiments with the proposed circuit implemented in a Field Programmable Gate Array (FPGA) are presented, which show a frame jitter reduction below 90 ps rms.

Distributed Nodes-Based Collaborative Sustaining of Precision Clock Synchronization Upon Master Clock Failure in IEEE 1588 System.

Abstract: This paper proposes a distributed nodes-based clock synchronization method to sustain sub-microsecond precision synchronization of slave clocks upon master clock failure in IEEE 1588 PTP (precision time protocol) system. The sustaining is achieved by synchronizing the slave clocks to the estimated reference clock which is obtained from the analysis of distributed slave clocks. The proposed method consists of two clock correction functions (i.e., a self-correction and a collaborative correction, respectively). Upon master failure, the self-correction estimates a clock correction value based on the clock model which is constructed during normal PTP operation. The collaborative correction is performed in the preselected management node. The management node estimates a reference clock by collecting and analyzing clock information gathered from the other slave clocks. The performance of the proposed method is simulated by computer to show its usefulness. It is confirmed that the fifty (50) clock model-based collaborative correction maintains 10−6 second PTP accuracy for 10 min prolonged period after the master failure when tested with clock offset variations less than 50 ppm.

Measures to Improve the Accuracy and Reliability of Clock Synchronization in Time-Sensitive Networking

Abstract: Most of the time-sensitive networking standards are based on a high precise and reliability time reference, which is accomplished by IEEE 802.1 AS. However, the accuracy and reliability of clock synchronization could be affected in practice. To conquer the inaccuracy resulting from the collision between different packets, an algorithm that combines time-slot-based synchronization and priority scheduling is proposed. To improve the reliability, an abnormal recovery strategy of the master clock is proposed. The proposed algorithms are implemented on the OMNet++ simulation platform with an typical in-vehicle network topology. The simulation results show that the clock synchronization accuracy could achieve sub-microsecond level even if there are interference flows, and the abnormal recovery mechanism can maintain the stable state of the clock.

Common-View Time Transfer Using Geostationary Satellite

Abstract: The National Time Service Center (NTSC), Chinese Academy of Sciences (CAS), Xi’an, China, has developed a method for common-view time transfer using Geostationary Earth Orbit (GEO) satellite (GCV) applicable to the time and frequency transfer at distant stations. This method is independent of Global Navigation Satellite System (GNSS) time and frequency transfer, as well as two-way satellite time and frequency transfer (TWSTFT). A master clock at the time laboratory transmits pseudorandom code signals to a GEO telecommunication satellite, and the time signals are retransmitted by the satellite. Receivers at the time laboratory and user locations coincidentally receive the time signals, and the offsets between the user clocks and the master clock of the time laboratory are determined with high precision if the precise coordinates of the user locations are known. For this technology, only a parabolic antenna with receiver devices and a demodulator are required at each user station, but the coordinates and precise orbits need to be obtained in advance. The key features of GCV include 1) continuous coverage of the signal from GEO communication satellites; 2) differential observations to reduce the effects of orbit error and the imprecision of the propagation delay model; 3) using a very small aperture terminal (VSAT) to enhance high signal ratio to noise to obtain precise ranging accuracy and antimultipath ability; and 4) utilizing the C-band or Ku-band to decrease the impact of the ionosphere. Experiments based on the TWSTFT network of CAS showed that the performance of GCV was at the same level as that of TWSTFT, and the rms of the residuals of GCV was less than 1.5 ns with respect to TWSTFT.

Marching to another clock.

Abstract: For several decades, researchers have studied the molecular mechanisms underlying circadian rhythms, the daily oscillations ubiquitous in biology. This basic clockwork is well understood in animal cells: Conserved clock proteins form a transcription-translation feedback loop that drives circadian oscillations of gene expression and downstream processes. These cellular clocks in peripheral tissues are hierarchically synchronized by a “master clock” in the brain [the suprachiasmatic nucleus (SCN) in mammals] responding to daylight, and also by other physiological signals such as feeding. On page 800 of this issue, Ray et al. (1) demonstrate that many circadian oscillations—in transcription, translation, and protein phosphorylation—can continue in mouse cells in the absence of an essential circadian clock gene, Bmal1 (brain and muscle ARNT-like 1). Thus, there might be other unknown clocks that also control circadian gene expression.

Master-Slave Topologies with Phase-Locked Loops

Abstract: Since phase-locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids, electronic instrumentation, computational clusters, and integrated circuits. In all of these practical cases, isolated or networked PLLs are responsible for recovering the correct time basis and synchronizing the processes. According to the application needs, different clock distribution strategies were developed, with the master-slave being the simplest and most used choice. Considering that the master clock is obtained from a stable periodic oscillator, two topologies are studied: one-way, not considering clock feedback; and two-way master-slave, with the slave nodes providing clock feedback to the master. Here, these two cases are studied by using simulation strategies, presenting results about the clock signal recovery process in the presence of disturbances, indicating that master-slave clock distribution networks can be useful for networks with few nodes and a stable master oscillator with the one-way topology presenting better results than the two-way arrangement.

Presence of Clock genes in equine full-term placenta.

Abstract: Mammals have a circadian rhythm that is synchronized by a master clock located in the hypothalamic suprachiasmatic nucleus (SCN). The SCN regulates additional clocks located in peripheral tissues, including some involved in endocrine or reproductive functions. Studies in humans and mice report that molecular clocks also exist in the placenta. However, little is known about the presence of "Clock genes," namely Circadian Locomotor Output Cycles Kaput (CLOCK), Brain and Muscle Arnt-Like 1 (BMAL1), Period 1 (PER1), Period 2 (PER2), Cryptochrome 1 (CRY1), and Cryptochrome 2 (CRY2), in equine placenta. Pregnancy length in mares varies and shows fluctuations in hormone concentrations throughout pregnancy. We postulate that similar to humans and mice, Clock genes are present in the horse placentas. Our goal was to determine if relative levels of clock genes were different between placentas associated with males and female fetuses or correlated with gestational length. We used polymerase chain reaction and immunofluorescence to study the presence of CLOCK, BMAL1, PER1, PER2, CRY1, and CRY2 in full-term mare placentas. Clock genes were present in all placentas, with significant lower levels of CRY2 and CLOCK in placentas that were associated with male fetuses. There was no association between relative levels of Clock genes and gestational length. These data provide the stage for future studies aimed at uncovering a function for Clock genes in the horse placenta.

Peer-to-peer transparent clocks and methods of estimating skew in peer-to-peer transparent clocks

Abstract: This invention relates to peer-to-peer transparent clocks and methods of estimating skew in peer-to-peer transparent clocks. Embodiments of the invention relate to techniques for estimating clock skew between a free-running clock in a transparent clock and a master clock, in particular by using the timing information embedded in timing messages passing through the transparent clock. Further embodiments of the invention set out uses of these estimates to modify the residence times computed by the transparent clock and a synchronization network including such transparent clocks.

Clock synchronization method and system of wireless network based on IEEE1588 protocol

Abstract: The embodiment of the invention provides a clock synchronization method and system for a wireless network based on an IEEE1588 protocol, and the method comprises the steps: respectively obtaining a first time stamp, a second time stamp, a third time stamp and a fourth time stamp through second equipment of the clock synchronization system; wherein the first timestamp is a moment before the synchronization message leaves the network layer of the first device and arrives at the first wireless communication module; wherein the second timestamp is a moment before the synchronization message leavesthe second wireless communication module and arrives at a network layer of the second device; based on the first timestamp, the second timestamp, the third timestamp and the fourth timestamp, obtaining time deviation between the slave clock and the master clock and network time delay between the second device and the first device; and inputting the time deviation and the network time delay into apreset deviation correction formula to obtain deviation correction time, and adjusting the slave clock by utilizing the deviation correction time. According to the method, the clock synchronization precision can be improved.

Systems and methods for integration of injection-locked oscillators into transceiver arrays

Abstract: Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

Time synchronization for clocks separated by a communication link

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Synthesized clock synchronization between networks devices

Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

Multiple vehicle signaling synchronization from adaptive timing sources

Abstract: A synchronization signaling system and method for operating the synchronization signaling system including a master clock, a set of alert devices, a user input adapted to receive a pattern request, at least one pattern cycle defining an alert pattern, and a controller having a local clock and defining a local time, where the controller is configured to operate the synchronization signaling system.

Slave apparatus, time synchronization program, embedded system, and time synchronization method

Abstract: According to the present invention, a slave node (300) is a slave apparatus which operates according to a control frame transmitted from a master node (200). The slave node calculates a control frame statistic which is a statistic of one or more control frames transmitted from a master apparatus, and estimates a master environment value on the basis of the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock on the basis of the estimated master environment value, and estimates a frequency deviation of a slave clock on the basis of the measured slave environment value. The slave node corrects the clock value of the slave clock on the basis of the difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.

Multi-clock synchronization in power grids

Abstract: Disclosed are methods and systems to improve the time synchronization of power distribution systems and/or other distributed device networks. The disclosure relates to nesting selection algorithms to elect a grand master clock from among groups of devices in a network.

Self-Regulated Clock Distribution Network for a Fast-Timing Active Hybrid Single Photon Detector

Abstract: Time resolution of active pixel sensors whose time stamp mechanism is based on Time-to-Digital Converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The Clock Distribution Network that delivers the master clock signal must be robust to the non-idealities of the electronics, mainly process-voltage-temperature variations, device and layout mismatch and noise coupling to minimize static time errors and jitter. In order to achieve sub-100ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the resolution in the adjustment of the network propagation delays or latencies must be well below that value. In this work, a self-regulated Clock Distribution Network that is robust to static and dynamic time errors is presented for the FastICpix hybrid single photon detector - aiming at a 65nm process. A 40 MHz clock is distributed to 64×64 pixels over an area of 2.4×2.4 cm2using digital Delay-Locked Loops. The latency from the clock source to the nodes of the network can be adjusted in steps finer than 20 ps, which is essential to enable a single photon time resolution of this order.

Time Synchronization Method in Precision Time Protocol Network and Computer Program Therefore

Abstract: An embodiment of the present invention relates to a time synchronization method in a precision time protocol network and a computer program therefor which solve the problem of an unbalanced master-slave structure that can cause imbalance problems such as high communication loads and high bandwidth consumption at multiple boundary clocks and enable a fast recovery mechanism in the event of a master clock failure.

Methods and systems for ultra wideband (uwb) receivers

Abstract: Ultra-Wideband (UWB) wireless technology transmits digital data as modulated coded impulses over a very wide frequency spectrum with very low power over a short distance. Accordingly, the inventors have established UWB devices which accommodate and adapt to inaccuracies, errors, or issues within the implemented electronics, hardware, firmware, and software. Beneficially, UWB receivers may accommodate offsets in absolute frequency between their frequency source and the transmitter, accommodate drift arising from phase locked loop and/or from relative clock frequency offsets of the remote transmitter and local receiver. UWB devices may also employ modulation coding schemes offering increased efficiency with respect to power, data bits per pulse transmitted, and enabled operation at higher output power whilst complying with regulatory emission requirements. Further, UWB devices may support a ranging function with range / accuracy not limited to the low frequency master clock employed within these devices enabling operation with ultra-low power consumption.

AHB bus clock domain crossing system and working method

Abstract: The invention discloses an AHB bus clock domain crossing system. The clock domain crossing system comprises a master clock data latch module, a master clock data merging module, a master clock data storage module, a slave control logic module, a slave clock data latch module, a slave clock data merging module, a slave clock data storage module and a master control logic module. The invention further discloses a clock domain crossing working method of the AHB, and read operation and write operation of data under the master clock domain and the slave clock domain are achieved. According to the invention, clock domain crossing processing of the AHB bus is realized, the delay of the clock domain crossing process can be reduced, the occupation amount of the bandwidth of the AHB bus is reduced,the bit width of a signal needing to be synchronized is reduced, and the error probability in the synchronization process is reduced.

Clock synchronization in a device

Abstract: To provide an indication of an accuracy level of a grandmaster clock, a solution using at least three different grandmaster types and grandmaster information maintained in a device is introduced. The three grandmaster types are a primary grandmaster, a secondary grandmaster and neither of them. The grandmaster information comprise information on a primary grandmaster and information based on which one or more secondary grandmasters may be determined. After master-slave hierarchy negotiations (401), the grandmaster information and information on a master clock negotiated is used (402) to determine whether the master clock negotiated for the device is the primary grandmaster (403), a secondary grandmaster setting a warning (404), or neither of them in which case an alarm is set (405).

Time synchronization correction method and time synchronization correction device applied to master clock and slave clock

Abstract: The invention provides a time synchronization correction method and a time synchronization correction device applied to a master clock and a slave clock. The device comprises the master clock and theslave clock. After the slave clock receives a synchronization time message sent by the master clock, the time offset of the master clock and the slave clock is calculated, and clock offset correctionis conducted on the slave clock through the time offset but the clock frequency of the slave clock is not corrected; and after the slave clock receives the master clock synchronization message at a preset moment, the clock offset and the clock frequency offset of the slave clock is corrected by calculating the clock offset and the clock frequency offset of the master clock and the slave clock. Ina preset long time T, only the clock offset of the slave clock is corrected for the first time and the (n-1)th time without correcting the clock frequency, and only the clock offset and the clock frequency offset of the slave clock are corrected for the nth time. Compared with the prior art, the method is high in precision, and can quickly correct the time synchronization of the slave clock according to the trend data after the synchronization time is lost.

Clock synchronization in a centralized radio access network having multiple controllers

Abstract: Embodiment are directed to systems and methods for use with a central radio access network (C-RAN) comprising a plurality of controllers and a plurality of radio points. Each of the controllers is configured to determine if that controller should serve as a timing master for the controllers and the radio points and, if that controller should serve as the timing master, synchronize the local clock of that controller with a master clock source over a backhaul network and transmit synchronization messages from that controller over a fronthaul network for reception by the other controllers and the radio points and for use by the other controllers and the radio points in synchronizing the local clocks thereof with the local clock of that controller. Other embodiments are disclosed.

Clock synchronization method and device and storage medium

Abstract: The invention discloses a clock synchronization method and device and a storage medium, and belongs to the technical field of communication. The method comprises the following steps: enabling networkequipment to receive an Announce message from a first master clock node and an Announce message from a second master clock node; when the identifier of the first clock source node carried in the Announce message of the first master clock node is the same as the identifier of the second clock source node carried in the Announce message of the second master clock node, selecting the master clock node with smaller clock deviation from the first master clock node and the second master clock node, and calibrating the clock of the network equipment according to the time information of the master clock node. According to the clock synchronization method and device, the main clock node with smaller clock deviation is selected as the main clock node for clock synchronization of the network equipment, so the accuracy of clock synchronization of the network equipment is higher, and the accuracy of the clock calibrated by the network equipment is higher.

Time synchronization method, time synchronization sending end, time synchronization receiving end and time synchronization system

Abstract: The invention discloses a time synchronization method, a time synchronization sending end, a time synchronization receiving end and a time synchronization system. The time synchronization method comprises the steps: judging whether parameters causing recalculation of an optimal master clock BMC algorithm are changed or not; if the judgment result is yes, issuing an Announce message based on the 1588 standard; if the judgment result is no, issuing a keep-alive message of the Announce message. According to the method, the keep-alive message and the protocol message are distinguished, so the problem that a CPU system is busy due to processing of the Announce message is solved, the 1588 protocol is optimized, and the effect of reducing impact on the CPU is achieved.

Clock synchronization in device

Abstract: To provide an indication of an accuracy level of a grandmaster clock, a solution using at least three different grandmaster types and grandmaster information maintained in a device is introduced. Thethree grandmaster types are a primary grandmaster, a secondary grandmaster and neither of them. The grandmaster information comprise information on a primary grandmaster and information based on whichone or more secondary grandmasters may be determined. After master-slave hierarchy negotiations (401), the grandmaster information and information on a master clock negotiated is used (402) to determine whether the master clock negotiated for the device is the primary grandmaster (403), a secondary grandmaster setting a warning (404), or neither of them in which case an alarm is set (405).

Intelligent Master and Secondary Clock System For Displaying Environment State

Abstract: The present invention relates to a master-slave clock system installed in a guest room in a hotel, a hospital, a school, a ship, or the like, and more particularly, to a master-slave clock system capable of displaying current weather or environmental changes on a slave clock as well as adjusting time or environment information of the slave clock by a master clock. The master-slave clock system comprises: an operating computer; a transmission device; and a portal site server.

Method for clock synchronization of protocols, and network, base station and user equipments

Abstract: A method for clock synchronization of protocols in a network comprising a base station, BS, the BS comprising a BS scheduler, a user equipment, UE, and a master clock as an Over-the-Top, OTT, IP service on uplink and downlink channels, the method comprising the steps of: a) enabling, by the network, one or more IP communication flows between interfaces of the master clock and the UE for IP time synchronization packets or packets with similar symmetrical delay and low jitter requirements; b) receiving at the UE and the BS packets of these IP communication flows; c) disabling, at the BS and the UE, the use of Carrier-Aggregation, CA, Coordinated MultiPoint, CoMP, and Dual Connectivity, DC, for data of these IP communication flows; d) setting, at the BS and the UE, the target radio Block Error Rate, BLER, of the uplink and downlink channels to a value equal to or less than that of the IP communication flow's target packet loss rate; e) calculating, at the BS and the UE, the radio packet size so as to ensure that each packet is transmitted over a single radio transmission; f) signaling, from the network to the BS scheduler, a signal indicating to bypass radio scheduler queues; g) receiving a signal at the BS scheduler to bypass radio scheduler queues; h) signaling, from the BS to the UE, a signal indicating to utilize grant-free transmission on the uplink channel; and i) receiving, at the UE, a signal indicating to utilize grant-free transmission on the uplink channel.