Showing papers on "Memory controller published in 1998"

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Memory controller supporting DRAM circuits with different operating speeds

Abstract: A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Memory system including a memory module having a memory module controller

Abstract: A system (300) that has a system memory controller (304) and memory module (306, 308). The memory modules (306, 308) include memory module controller (310, 316) coupled to the system memory controller (304) and a plurality of memory devices (312-315, 317-320) coupled to the memory module controllers (310, 316).

Memory module system having multiple memory modules

Abstract: There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Method and apparatus for implementing multiple memory buses on a memory module

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Using FET switches for large memory arrays

Abstract: The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.

Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface

Abstract: A storage management system for a Redundant Array of Independent Disks (RAID) data storage system and an AutoRAID memory transaction manager for a disk array controller are disclosed. The disk array controller enables a consistent, coherent memory image of the data storage space to all processors across hot-plug interfaces. To external processes seeking to read or write data, the memory image looks the same across the hot-plug interface. The disk array controller has two identical controllers, each with its own non-volatile memory, to maintain redundant images of disk array storage space. A hot-plug interface interconnects the two controllers. Each controller has an AutoRAID memory transaction manager that enables sharing of cyclic redundancy check (CRC)-protected memory transactions over the hot-plug interface between the two controllers. The AutoRAID memory transaction managers also have transaction queues which facilitate ordered execution of the memory transactions regardless of which controller originated the transactions. The AutoRAID transaction manager includes first and second bus interfaces, a mirror entity, and a local memory interface. Mirrored read and write transactions are handled atomically across the hot-plug interface.

Memory device and system including a low power interface

Abstract: A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.

Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module

Abstract: A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and control logic. The first interface circuitry is configured to receive from the system memory controller a first memory transaction in a first format. The control logic is coupled to the first interface circuitry and configured to convert the first memory transaction into a second memory transaction in a second format for the plurality of memory devices. The second format of the second memory transaction is different than the first format of the first memory transaction.

Memory controller for interchanging memory against memory error in interleave memory system

Abstract: In a memory system having a plurality of banks which forms interleave groups for independently forming an interleave, when a memory error is detected in an operating system resident space, the group having the error is interchanged with another group that has not had any error yet. After a group interchange, a page having the error is also deallocated. When a determination is made that the group interchange causes deterioration of performance, a bank deallocation can be also executed. As this criterion for determination, it is possible to employ a policy that a bank is deallocated when a capacity of a bank including an erroneous sub-bank is equal to or less than a predetermined rate of all the memory capacity and an interleaving factor is less than the interleaving factor of an interchange partner after the bank deallocation.

Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof

Abstract: A semiconductor memory device which is applicable not only to a cache system but to the field of graphic processing is provided. The semiconductor memory device includes a DRAM portion, an SRAM portion and a bidirectional data transfer circuit 106 which carries out data transfer between a DRAM array included in the DRAM portion and an SRAM array included in the SRAM portion as well as data input/output with the outside of the device. Driving of the DRAM array and data transfer operation between the DRAM array and the bidirectional data transfer circuit are controlled by a DRAM control circuit. Driving of the SRAM array, data transfer between the SRAM array and the bidirectional data transfer circuit, and the data input/output operation are controlled by the SRAM control circuit. The address to the DRAM array is applied to a DRAM array buffer 108, while an address for selecting a memory cell in the SRAM array is applied to the SRAM address buffer.

Increasing TLB reach using superpages backed by shadow memory

Abstract: The amount of memory that can be accessed without causing a TLB fault, the reach of a TLB, is failing to keep pace with the increasingly large working sets of applications. We propose to extend TLB reach via a novel Memory Controller TLB (MTLB) that lets us aggressively create superpages from non-contiguous, unaligned regions of physical memory. This flexibility increases the OS's ability to use superpages on arbitrary application data. The MTLB supports shadow pages, regions of physical address space for which the MTLB remaps accesses to "real" physical pages. The MTLB preserves per-base-page referenced and dirty bits, which enables the OS to swap shadow-backed superpages a page at a time, unlike conventional superpages. Simulation of five applications, including two SPECint95 benchmarks, demonstrated that a modest-sized MTLB improves performance of applications with moderate-to-high TLB miss rates by 5-20%. Simulation also showed that this mechanism can more than double the effective reach of a processor TLB with no modification to the processor MMU.

Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

Data storage system storing data of varying block size

Abstract: A data system comprising a store ( 10 ), a memory ( 12 ), a user interface ( 32 ) and a memory controller ( 24 ) where the memory is used to buffer all data transferred between the user interface and the store, the system being characterized in that the memory controller copies data directly between the store and the memory, whereas the memory controller re-organizes data when the data is transferred between the memory and the user interface.

Method for aligning clock and data signals received from a RAM

Abstract: One embodiment of the present invention provides a method for aligning a data signal and a data clock signal received from a memory during a read operation. The method includes receiving the data signal and the data clock signal from the memory, and determining an offset between these signals. If the offset is outside of a valid range, the system adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the method is performed by special-purpose hardware located in a memory controller, and operates periodically while the computer system is running. In another variation, the method is carried out by a BIOS program stored in read only memory, and operates during system startup.

Addressing scheme for a double data rate SDRAM

Abstract: A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. A unique addressing circuit controlled by an internal clock generates addresses for each plane from one external address. The generated addresses allow both planes to be accessed simultaneously. Thus, two sets of data from two independent planes of memory are simultaneously accessed in one system clock cycle.

Multi-chip memory apparatus and associated method

Abstract: A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Integrated circuit with unified memory system and dual bus architecture

Abstract: A unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.

Memory controller architecture

Abstract: An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

Memory controller with error correction memory test application

Abstract: Apparatus and method for testing of memory locations containing both test data and test check bits are provided The apparatus includes a memory controller that communicates with memory devices In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data The test data and test check bits are written to desired memory locations of the memory devices The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read Any lack of correspondence is indicative of one or more memory location faults Both the test data and the test check bits are checked for accuracy during single transfer operations and the checking of the test check bits is conducted using at least some of the values of the associated test data

Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system

Abstract: A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.

Memory module and data processing system

Abstract: PROBLEM TO BE SOLVED: To easily realize necessary function and performance such as a protocol for high-speed memory access without incorporating any complex input/output circuit or control circuit for high-speed operation in a mounted memory. SOLUTION: A memory module (MODc) is provided with input/output terminals (IPO0-IPO15), to which a control signal based on a protocol control configuration is supplied, a protocol converter (23) connected to the input/output terminals for mutually converting different access control configurations, and SDRAM devices (M0-M15) connected to the input/output terminals via the protocol converter for working based on the access control configuration different from the protocol control configuration. The protocol converter has register buffers (RBUFc0-RBUFc15) each having a parallel-serial conversion function, converts serial data fed from the input/output terminals to the SDRAM devices into parallel data, and converts parallel data fed from the SDRAM devices to the input/output terminals into serial data. COPYRIGHT: (C)2006,JPO&NCIPI

High speed stackable memory system and device

Abstract: A stackable memory system for minimizing the stub lengths of the memory data bus and data skew. The invention provides a memory controller, a memory connector, a data bus, a first stackable memory module and a terminator plate. The data bus electrically connects the controller to the memory connector. The first stackable memory module is mechanically and electrically connected to the memory connector. The terminator plate is adapted to substantially reduce reflections to the data bus and is electrically connected to the data bus through the first stackable memory module. Additional, the memory system may be expanded by adding stackable memory modules substantially similar to the first stackable memory module to the stackable memory system between the first memory module and the terminator plate. Each stackable memory module may include memory chips each of which has trace lines connecting the memory chip to a module connector. Each of the trace lines is substantially equal in length and connects to a single side of the memory chip.

Command vector memory systems: high performance at low cost

Abstract: The focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from SDRAM parts, we propose a new memory system organization based on sending commands to the memory system as opposed to sending individual addresses. A command specifies, in a few bytes, a request for multiple independent memory words. A command is similar to a burst found in DRAM memories, but does not require the memory words to be consecutive. The command is sent to all sections of the memory array simultaneously, thus not requiring a crossbar in the proper sense. Our simulations show that this command based memory system can improve performance over a traditional SDRAM-based memory system by factors that range between 1.15 up to 1.54. Moreover, in many cases, the command memory system outperforms even the best SRAM memory system under consideration. Overall the command based memory system achieves similar or better results than a 10 ns SRAM memory system (a) using fewer banks and (b) using memory devices that are between 15 to 60 times cheaper.

Selective power distribution circuit for an integrated circuit

Abstract: A memory circuit is described which includes distributed voltage generators to selectively provide power to memory arrays of the memory circuit. Each memory array can be turned off by deactivating its voltage generator if it is determined that the memory array is defective and cannot be repaired. The memory device, therefore, can be salvaged by reducing the operational capacity of the memory device. The distributed voltage generators can be selectively deactivated to test the memory circuit.

Method and circuit for testing a semiconductor memory device operating at high frequency

Abstract: A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.

Single-port trace buffer architecture with overflow reduction

Abstract: A buffer circuit includes a buffer input, a memory, a memory controller and an upper buffer limit register. The memory is coupled to receive information from the buffer input. The memory has a single-port for accessing a plurality of storage locations for storing the information. The upper buffer limit register is for storing an upper buffer limit value. The memory controller is coupled to the memory and the upper buffer limit register. The memory controller prioritizes writes over reads when the number of storage locations of the memory storing the information is less than the upper buffer limit value. The memory controller prioritizes reads over writes when the number of storage locations storing the information is greater than the upper buffer limit value.

Smarter memory: improving bandwidth for streamed references

Abstract: Processor speeds are increasing so much faster than memory speeds that within a decade processors may spend most of their time waiting for data. Most modern DRAM components support modes that make it possible to perform some access sequences more quickly than others. The authors describe how reordering streams can result in better memory performance.

Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module

Abstract: A system that has a system memory controller and a memory module. The memory module includes a memory module controller coupled to the system memory controller and a plurality of memory devices coupled to the memory module controller.

Dynamic configuration of memory module using modified presence detect data

Abstract: A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.