Showing papers on "Memory refresh published in 1979"

A fault-tolerant 64K dynamic random-access memory

Abstract: A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.

Nonvolatile static random access memory devices

Abstract: Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents

Word-by-word electrically reprogrammable nonvolatile memory

Abstract: A word-by-word electrically reprogrammable nonvolatile memory has memory cells arranged in a matrix and provided with a control circuit, interconnected with the memory matrix in such a manner that variable erase and write durations are provided for each memory line. The termination of the variable durations is indicated by attainment of a predetermined erase or, respectively, write condition of one or more memory cells from the memory line to be erased or written. The erase or write condition of these cells is monitored during the erase or write duration of the memory line to provide a condition-effected termination of the variable duration.

A fault-tolerant 64K dynamic RAM

Abstract: A 64K MOS RAM, featuring 100ns worst-case column access time, 128 refresh cycles, and pin compatibility with 16K RAMs, will be described Polysilicon bit lines provide a high cell/column capacitance ratio, while spare memory elements improve yield

Laser programmable read only memory

Abstract: A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal. When a particular column is addressed, and the associated transistors in the address line turned on, all of the bits in the associated word will be "ones." The memory is programmed as desired after circuit manufacture in the wafer die sort operation by severing selected links with a laser beam. The severed device will program a "zero" into the bit location. The word lines are coupled to a decoder that employs an array of gates having input pairs, one of which displays hysteresis. The memory also includes an external program simulation circuit which permits externally generating a particular digital word to simulate the memory content prior to programming.

Duplicated memory system having status indication

Abstract: A fully duplicated memory system for a single central processing unit (CPU) is disclosed. The memory system comprises a primary and a secondary control unit and a primary memory bank and a secondary memory bank. Each memory bank comprises one memory controller and a plurality of memory modules (e.g. six memory modules). Each memory module stores a plurality of binary words in distinct addressable storage locations with a unique address code defining both one distinct addressable storage location in a memory module in the first memory bank and one distinct addressable storage location in a memory module in the second memory bank. A random access memory (RAM) stores an indication of the read and write status of each memory module in both the first and second memory banks. One of the control units, responsive to both the CPU and the RAM determines which memory bank (primary or secondary) is accessed in response to a read or a write command from the CPU addressed to the memory banks.

Refresh system for dynamic RAM memory

Abstract: A method and apparatus for controlling the refreshing of a volatile memory is disclosed in which conflicts between a memory refresh operation, the requirements for access to the memory during a data processing operation and a power up or power down condition are resolved. When a conflict occurs, clock signals are generated to provide a contention refresh operation of the memory with minimum interruption to normal access time between the control processor and the memory.

Multiple bit read-only memory cell and its sense amplifier

Abstract: The bit density of stored information in a read-only memory (ROM) can be substantially increased by increasing the number of bits which can be stored in each memory cell. This can be accomplished without increasing the size or complexity of the memory cell by having the read only memory capacity stored in each memory cell as one of a multiple number of discrete states achievable by the cell. In a semiconductor chip this can be accomplished by having the semiconductor element, such as a transistor, capable of assuming one of a multiple of parametric values or states. For example, as described herein, impedance or cell width of a semiconductor transistor can be varied to assume one of four different states. The state assigned to a selected memory cell is bracketed by the value of the outputs of a plurality of comparator circuits coupled thereto. The outputs of the comparator circuits are then analyzed by a logic circuit to provide the appropriate binary readout representative of the parametric state of the selected cell.

Electrically alterable read-mostly memory

Abstract: An electrically alterable read-mostly MOS memory (commonly referred to as E2 PROM) employing floating gate memory devices is described. Each word stored in memory may be separately accessed for reading and writing. The memory array is arranged with additional lines and selection means to prevent the high-level programming signals from the X-decoders from programming all the floating gate devices along a selected X-line. A high voltage circuit is described which permits the handling of potentials greater than the grounded gate breakdown voltage associated with the shallow junction devices used in the memory. A unique sensing amplifier is also disclosed which detects low currents at high speeds.

Postage meter having means transferring data from a working memory to a non-volatile memory under low power conditions

Abstract: An electronic postage has a working memory and a non-volatile memory. A voltage sensing circuit senses low power conditions, and, in response thereto, controls a data transfer circuit to transfer data from the working memory to the non-volatile memory.

Program Behavior and the Performance of Interleaved Memories

Abstract: One of the major factors influencing the performance of an interleaved memory system is the behavior of the request sequence, but this is normally ignored. This paper examines this issue. Using trace driven simulations it is shown that the commonly used assumption, that each request is independently and equally likely to be to any module, is not valid. The duality of memory interference with paging behavior is noted and this suggests the use of the least-recently used stack model to model program behavior. Simulations indicate that this model is reasonably accurate. An accurate, though approximate, expression for the bandwidth is derived based upon this model.

Memory system wherein individual bits may be updated

Abstract: A memory system having a word-addressable memory and bit changing circuitry for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory and a copy memory. The copy memory stores duplicates of the data words stored in the primary memory. The bit changing circuitry receives a word having a bit to be changed from the copy memory and returns the word, including the changed bit, to both the primary memory and copy memory.

Data processing system having centralized memory refresh

Abstract: In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

Computer input/output arrangement for enabling a simultaneous read/write data transfer

Abstract: A computer input/output arrangement is disclosed which utilizes a rotate memory instruction of a computer instruction set for performing a bit by bit read/write data transfer between the computer memory and a connected peripheral device. The arrangement enables the rotate memory instruction to perform read and write steps simultaneously from memory and the peripheral device. During the read step data is simultaneously read from the memory location and the peripheral device into associated locations in a computer register. The register data is rotated such that the received data in the peripheral device bit location is rotated into the memory bit locations of the register while simultaneously rotating a memory data bit into the peripheral device bit location. The write step writes register data from the peripheral device bit location to the peripheral device while simultaneously writing the data from the memory bit locations into the memory.

Memory device for processing picture images data

Abstract: The memory device for processing picture images data is comprised from a memory bank including a number of memory boards each constituted by a bit plane, and bits constituting a picture element information are located in different memory boards. There are provided a data write circuit for writing the picture element data having any desired bit length in the memory bank starting from any desired bit location of the memory bank, and a read out circuit for reading out the stored picture element information having any desired bit length from any desired bit position of the memory bank.

A high-speed low-power Hi-CMOS 4K static RAM

Abstract: A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.

Protection circuit for storage of volatile data

Abstract: A protected memory circuit for use with an electronic data system includes a memory element such as a shift register, and memory control or lock means to selectively control enablement of the memory element for read/write operations. A separate power supply which may be a charged capacitor is used to power the memory and memory lock circuits in case of a power interruption in the main system with which the memory is being used, so that volatile data can be stored for re-use by the main system after the main power is restored. The lock includes a counter and a gate for inhibiting clock pulses to the memory element until a predetermined number of control pulses have been received to initiate a read/write operation. At all other times the clock input is blocked or clamped to prevent spurious signals or power surge transients from altering the stored data.

A clocked static memory

Abstract: A clocked static memory comprising a memory matrix (10) including a plurality of static memory cells (11) arranged in rows and columns and providing a voltage differential at bit lines (13, 14) whenever an associated memory cell is selected. Sense amplifiers (22) are connected between the bit lines of each column and a sense clock line (27) connected to a sense driver (40) crosses transistors in a sense amplifier (22) in each column. A logic circuit (50) detects the actual data output on data lines (15, 16) coupled to the bit lines and is buffered by an amplifier (51) to provide a memory status output signal indicating the existence of valid data output.

Memory test device with write and pseudo write signals

Abstract: A memory device having a test function for detecting abnormal memory cells having low hold ability is disclosed. The memory device characteristically comprises a first write control circuit which operates in a normal write mode and a second write control circuit which operates in a pseudo write mode to supply a pseudo write signal lower than a threshold value at which the state or content of the normal memory cell is changed or inverted, to the memory cell to be tested. In such a pseudo write mode, the state of the normal memory cell remains unchanged, but if the tested memory cell is abnormal, its state is changed. After the pseudo write mode, the tested memory cell can be detected to be normal or abnormal by reading out the content of the tested memory cell.

A 6ns 4Kb bipolar RAM using switched load resistor memory cell

Abstract: current memory cell operation and fast word line switching are the keys to fast, large capacity (above 4Kb) bipolar RAMs. However, it is difficult to achieve this performance in large capacity memories with conventional parallel diode memory cells’. This problem was overcome with a switched load resistor memory cell; Figure 1. At standby, the load resistance of the memory cell is high ( R ~ ~ 1 5 0 k f i ) . When the memory cell is selected, a read current flows through Schottky diodes, and consequently, the load resistance is automatically switched to a lower value ( R ~ = 2 5 0 f i ) . This load resistor switching affords a large read current (2mA), smaller standby current (4pA) and a fast memory cell readtime of 0.511s. Power dissipation does not increase in spite of the large read current, because the read current is directed only to the selected memory cell by the use of a switched read current It has been found by computer simulation that large-read-

Plural microcode control memory

Abstract: A microcode control memory having a first memory for receiving initial instructions is shown in combination with at least one additional memory for executing multistep control functions in a computer system. The first memory receives all initial control instructions from an instruction stack and produces the appropriate control output. Simultaneously as part of the initial instruction, a memory select network receives a control bit so that an output select network connected to the output of all memories passes the output from the first memory to the output register. Single step instructions are processed continuously this way. Multistep instructions are performed by using a portion of the output from the first memory to serve as the address selection in one of the other memories. When a multistep instruction is completed, the output select network again selects the output from the first memory for gating to the output register. The memory select network provides a control for the selection of the output of the first or any other memory at the same time that the memory is generating an output from an input address.

Memory system for programmable controller

Abstract: In a programmable controller having a central processing unit (10) and a memory, the invention provides memory in the form of a fast memory (2) (preferably a RAM) and a slow memory (1) (preferably a EAROM). The processor is normally controlled by a program whose information is stored in slow memory. When you want to change the circuit program, a new information program is entered into the fast memory. Control is then transferred to fast memory, the new information program is transferred to slow memory, and finally control is returned to slow memory.

Microprogrammed system having single microstep apparatus

Abstract: In a data processing system which includes a central processing unit and one or more main memory units comprised of semiconductor dynamic random access memory chips, logic is provided within the system to provide for the single stepping of the central processing unit clock thereby allowing for the execution of one CPU cycle. The system logic is organized such that the memory refresh command signals, which are normally generated by the CPU, are generated by the single step logic thereby maintaining the contents of the main memory modules. The logic of the overall data processing system is organized such that most transfers of information between the main memory, the CPU and I/O controllers, to which peripheral devices are connected, may take place in the single step mode of operation without the loss of information.

Memory refresh means including means for providing refresh addresses during power failures

Abstract: Memory control circuitry is disclosed for providing memory refresh during battery back-up operation. Memory addressing circuitry is connected between circuitry, such as a processor, providing memory refresh addresses, and memory addressing inputs. During normal main power supply operation, refresh addresses are provided to the memory from the processor. Upon occurrence of a main power supply failure, and start of battery back-up operation, the last refresh address provided by the processor is stored in the memory addressing circuitry and successively incremented to provide refresh addresses to the memory .

Dynamic memory with on-chip refresh invisible to CPU

Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.

Low power quasi-static storage cell

Abstract: A semiconductor memory device forming a static type memory cell uses three field effect transistors. One is connected between a storage node and a bit line so it functions as an access transistor. The storage node is connected to a refresh node through a second transistor having its gate shorted to drain, and the third transistor connects the refresh node to a supply voltage. A voltage dependent capacitor connects the refresh node to a refresh clock. A logic 1 on the storage node turns on the third transistor and charges the refresh node, which turns on the capacitor so the refresh clock is coupled through to turn on the second transistor and refresh the storage node. When a logic 0 is stored, this will not happen.

Static read only memory

Abstract: A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node corresponding to a bit line of the memory cell, and a highly sensitive differential sense amplifier including first and second cascaded connected inverter stages.

Display device with variable capacity buffer memory

Abstract: A display system which has a source of blocks of codes representing characters to be displayed and a display device which converts the blocks of codes to lines of visually displayed characters is provided with a buffer memory which connects the source to the display device. The buffer memory includes a random access memory (RAM) with addressed registers for storing the codes and an address generator in the form of a counter. When a block of codes is transferred from the source to the buffer memory, the counter is initialized and as each code is transmitted to the buffer memory the counter is incremented. Each time the block of codes is transferred from the buffer memory to the display device the counter is again initialized and with the reading of each code from the memory the counter is again incremented. The buffer memory includes two identical RAMs and is controlled such that while one RAM is being loaded the other RAM is being read.

Device for reducing the time of access to information contained in a memory of an information processing system

Abstract: A circuit arrangement for reducing access time to information contained in a memory system that includes a register for collecting the information contained in the memory system. The register operates as a flip-flop and is composed of a first inverter, an AND gate and a second inverter. The input of the first inverter is connected to receive the information bits read in a memory block. The AND gate includes two inputs, one of which is connected to the output of the first inverter. The other input receives, at the beginning of the memory reading cycle, an initialization signal for positioning the flip-flop in a given state. The output of the AND gate is connected to the second inverter which has its output connected, in turn, to the input receiving information read from the memory system.

A 64 Kbit MOS dynamic random access memory

Abstract: A 65536 word/spl times/1 bit dynamic random access memory is developed using 4 /spl mu/m design rules, a 320-/spl Aring/ thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 Kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.