Showing papers on "Metal gate published in 1971"

Radiation Hardening of P-MOS Devices by Optimization of the Thermal Si02 Gate Insulator

Abstract: It has been found for p-channel MOS devices that considerably better radiation tolerance than generally believed possible can be obtained with gate insulators of thermally grown SiO2, provided that the processing conditions are optimized for radiation resistance. The oxidation ambient and temperature, the post-oxidation annealing temperature, the silicon orientation, and the method of depositing the gate metal all have pronounced effects on the radiation-induced degradation. With these parameters optimized for radiation hardness, gate threshold shifts of less than one volt after 1 × 106 rads (Si) can be obtained over the entire range of gate biases from 0 to -30 volts. This paper describes these findings and their applicability to the fabrication of radiation-hardened MOS circuits.

Memory Behavior in a Floating-Gate Avalanche-Injection MOS (famos) Structure

Abstract: A novel charge‐storage structure is described. The floating‐gate avalanche‐injection MOS (FAMOS) structure is shown to exhibit memory behavior in the form of long‐term charge storage on the floating conductive gate of an insulated gate field‐effect device. Charge is stored in the floating polysilicon gate by avalanche injection of electrons from an underlying p‐n junction.

The adjustment of mos transistor threshold voltage by ion implantation

Abstract: Two new techniques have been demonstrated to set the threshold voltage of p‐channel MOS transistors and integrated circuits. Both processes employ ion implantation to alter the doping profile near the Si–SiO2 interface. The first centers the ion distribution at the interface while the second places it well inside the silicon. Thresholds may be modified from enhancement through depletion mode. Either method is compatible with standard MOS processes.

D.C. measurement of the space charge capacitance and impurity profile beneath the gate of an MOST

Abstract: An analysis of the MOS Transistor with bias between the source and substrate has shown that when the surface is weakly inverted, the silicon space charge capacitance over a wide range of temperature and bias can be obtained from the change in gate voltage required to maintain a constant channel current. The substrate impurity profile beneath the gate oxide can then be calculated from capacitance-bias measurements. Measurements made on n -channell and p -channel transistors following the growth of a thick gate oxide indicate a segregation coefficient of ⋍ 0·3 and ⋍ 100 for boron and phosphorus respectively.

Shift of the Gate Threshold Voltage of MOS Transistors dne to the Introduction of Shallow Impurities

Abstract: It is possible to shift the gate threshold voltage of MOS transistors with little sacrifice of other device performances by introducing shallow level impurities only into a region near the semiconductor surface under the gate. Some theoretical information is given which may be useful for designing MOS transistors in an attempt to realize such a shift. The effects of the impurity introduction on the characteristics of MOS diode structures are also described.

Floating gate solid state storage device and method for charging and discharging same

Abstract: A floating gate solid state storage device comprising a floating silicon or metal gate in a field effect device which is particularly useful in integrated circuit devices such as a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO2 is charged by transferring charged particles (i.e., electrons) at relatively low voltages (e.g., less than approximately 50 volts) across a thick insulation layer (e.g., greater than approximately 500 angstroms) from the substrate during an avalanche injection condition.

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

Abstract: A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO 2 energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to 2 \times 10^{-4} A/cm2. The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.

Gate protection of MIS devices

Abstract: Gate shorts caused by electrical breakdown of the gate dielectric are a major yield and reliability problem for MOS transistors and integrated circuits. Diodes or diffused resistors with breakdown voltages of about 40 V can be used to protect the gate from high voltage transients or static discharges. This paper provides a uniform approach to gate protection. It is shown theoretically that in order to obtain effective gate protection: the protecting device should have a low dynamic resistance in breakdown; the breakdown voltage of the protecting device should be above, but close to, the maximum gate operating voltage; and protection by a diffused resistor in series with the gate is much more effective than by a diode in parallel with the gate. It is shown experimentally that, compared to the widely used fieldplate-induced breakdown, breakdown due to reach-through to a highly doped substrate provides: a dynamic resistance that is almost two orders of magnitude lower; reasonable control of the breakdown voltage; much better protection against simulated static discharges. Since under pilot line conditions no adverse effects on performance or yield have been observed, reach-through breakdown devices seem to improve gate protection decisively without any coincident disadvantages.

Planar silicon gate mos process

Abstract: THIS INVENTION REFERS TO A METHOD OF MANUFACTURING A METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAV- ING A SOURCE, DRAIN AN CHANNEL REGION AND A GATE FORMED OVER THE CHANNEL REGION. THERE IS FORMED A FIRST INSULATING LAYER ON A SEMICONDUCTOR SUBSTRATE COVERING THE NON-ACITVE REGIONS OF THE TRANSISTOR AND THEN A SECOND INSULATING LAYER IS FORMED OVER THE ACTIVE REGION OF THE TRANSISTOR. A SEMICONDUCTIVE LAYER IS DEPOSITED OVER THE ACTIVE AND NON-ACTIVE REGIONS AND SUBSEQUENTLY THE GATE PERIPHERY OF THE SEMICONDUCTOR LAYER IS CONVERTED TO AN OXIDE WHICH IS SUBSEQUENTLY ETCHED AWAY THUS EXPOSING THE SOURCE AND DRAIN REGIONS OF THE TRANSISTOR AND THE REAMINDER OF THE GATE PERIPHERY TO THE SUBSTRATE SURFACE. THE GATE AND SOURCE AND DRAIN REGIONS ARE THEN DIFFUSED WITH A DOPING IMPURITY AND METAL CONTACTS ARE DEPOSITED TO THE SOURCE AND DRAIN REGIONS AND TO THE GATE SEMICONDUCTOR.

A distributed gate bistable MOS transistor

Abstract: A distributed gate multi-electrode MOS transistor with voltage controlled stable negative resistance characteristic is described. The use of standard planar techniques to fabricate this device has overcome essentially all the difficulties encounted in making the junction field effect tetrode proposed by Stone and Warner. In addition, there are several advantages such as the complete pinch-off characteristic or the zero current off state, and the wide range of stable negative resistance which is controllable through the applied voltage to the gates.

Ion-implanted MOS technology

Abstract: This paper discusses the current state of ion-implantation as applied to MOS technology. It is shown how impurity doping by ion-implantation is used to produce self-aligned MOS gate structures. The reduction in circuit capacitance gives the designer a choice of higher switching speed or lower power dissipation. The availability of a linear resistor of value 1–10 kω/□ allows many new circuit techniques to be applied to monolithic circuits. This paper discusses ion-implantation technology, device design, and circuit performance. A number of implanted circuits are shown. Finally, improvements to the present technology which are still in the R & D phase are described.

Enhancement mode n-channel mos structure and method

Abstract: Enhancement mode N-channel MOS structure having a semiconductor body with a region of P conductivity type formed in the body and extending to the surface. A polycrystalline gate structure is formed on said surface. Spaced source and drain regions are formed in the region of P conductivity type and form a channel in said body underlying said gate structure with the polycrystalline material of the gate structure having an N-type impurity therein. A layer of insulating material is formed on the surface and covers the gate structure. Contact elements are formed on the layer of insulating material and extend therethrough to make contact with the source and drain regions and said polycrystalline gate structure to form an active device. In the method for fabricating the structure, the polycrystalline material of the polycrystalline gate structure is doped independently of doping for forming the channel underlying the polycrystalline gate structure.

Method of making an mos transistor including a gate insulator layer of aluminum oxide and the article so produced

Abstract: A method of making an MOS transistor which has a gate insulator layer composed of aluminum oxide made by plasma anodizing a thin layer of aluminum, in which the thin aluminum layer and the anodized layer are not defined by etching. The gate electrode insulator layer is formed by depositing a thin layer of aluminum over the entire surface of the device after the source and drain contacts are made and then converting the entire aluminum layer to aluminum oxide.

Variable delay,mos,monostable pulse generating circuit

Abstract: There is disclosed a voltage controlled pulse width, MOS, monostable circuit which comprises first and second enhancement mode MOS transistors wherein the gate electrode of the second MOS transistor is connected to the drain electrode of the first MOS transistor and the gate electrode of the first MOS transistor is connected to an RC timing circuit of which the resistor is connected between the gate electrode and the source electrode and the capacitor is connected from the gate electrode to the drain electrode of the second MOS transistor. The MOS transistors are adapted to be connected across a source of power and a third enhancement mode MOS transistor is connected as a source follower between the drain of the second MOS transistor and the source of power. A fourth enhancement mode MOS transistor is connected across the first transistor and includes a differentiating circuit connected to its gate electrode for introducing a sharp pulse into the monostable circuit for initiating its operation. The terminal of the differentiating circuit and the gate electrode of the third transistor are adapted to be supplied with the gate pulse which initiates operation of the circuit to generate an output pulse and whose amplitude determines the width, or time duration, of the output pulse.

Radiation hardening of mos devices by boron

Abstract: A NOVEL TECHNIQUE IS DISCLOSED FOR RADIATION HARDENING OF MOS DEVICES AND SPECIFICALLY FOR STABILIZING THE GATE THRESHOLD POTENTIAL AT ROOM TEMPERATURE OF A RADIATION SUBJECTED MOS FIELD-EFFECT DEVICE OF THE TYPE HAVING A SEMICONDUCTOR SUBSTRATE, AN INSULATING LAYER OF OXIDE ON THE SUBSTRATE, AND A GATE ELECTRODE DISPOSED ON THE INSULATING LAYER. IN THE PREFERRED EMBODIMENT, THE NOVEL INVENTIVE TECHNIQUE CONTEMPLATES THE INTRODUCTION OF BORON INTO THE INSULATING OXIDE, THE BORON BEING INTRODUCED WITHIN A LAYER OF THE OXIDE OF ABOUT 100 A-300 A THICKNESS IMMEDIATELY ADJACENT THE SEMICONDUCTOR-INSULATOR INTERFACE, THE CONCENTRATION OF BORON IN THE OXIDE LAYER IS PREFERABLY MAINTAINED ON THE ORDER OF 10**18 ATOMS/CM.3. TH NOVEL TECHNIQUE SERVES TO REDUCE AND SUBSTANTIALLY ANNIHILATE RADIATION INDUCED POSITIVE GATE CHARGE ACCUMULATIONS, WHICH ACCUMULATIONS, IF NOT ELIMINATED, WOULD CAUSE SHIFTING OF THE GATE THRESHOLD POTENTIAL OF A RADIATION SUBJECTED MOS DEVICE, AND THUS RENDER THE DEVICE UNSTABLE AND/OR INOPERATIVE.

A high voltage ion-implanted MOSFET

Abstract: The drain breakdown voltage of usual p-channel MOS devices is limited to about 30 to 40 V by field crowding at the drain junction. By optimizing certain design parameters like diffusion depth, substrate resistivity and gate oxide thickness, 80 V breakdowns can be achieved. To date, higher breakdowns are only possible with special device geometries (e.g. the stacked gate tetrode) which are generally not compatible with common MOS processes. By adding an ion-implantation step to the conventional aluminum-gate MOS process, it is possible to fabricate MOSSFET's with source-drain breakdown potentials of greater than 240 V on the same chip with conventional MOS circuitry. The device looks identical to the conventional MOSFET except that an unmetalized gate oxide region is left between the gate and the drain juction. During a subsequent ion-implantation this portion of the channel is lightly doped with a p-type dopant in the case of p-channel devices. Since-both the metal and the field oxide are thick enough to stop all ions, the implantation affects only the high voltage devices on the wafer. The implanted channel has the effect of reducing the field in the vicinity of the drain junction, thereby increasing the source-drain breakdown voltage. P-channel devices were made on 10 Ω-cm material using 1µm diffused junctions. The aluminum gate was 10 µm long and the implanted channel was 25µm long. Breakdowns up to 240 V were achieved after an optimum dose of 2 \times 10^{12} boron ions/cm2were implanted at 80 keV through 1300 A of gate SiO 2 . The wafers were subsequently annealed for 15 minutes at 525°C in N 2 . Implanted resistors made at the same time had sheet resistivities of 25 kΩ/□. Of critical importance in obtaining best results are low threshold voltages and accurate implantation dose control To obtain long term reliability it is necessary to prevent charge build-up on the oxide over the implanted channel. This is accomplished by the deposition of a layer of phosphosilicate glass after ion-implantation. It is now possible to include decoding circuitry on the same chip as the high voltage drivers for display tubes.

Operation of dual gate MOS field effect transistors at 77 K and use in rf and video amplifiers

Abstract: Measurements have been made with dual gate MOS field effect transistors when immersed in liquid nitrogen. It has been found that such devices are suitable for wideband and tuned rf amplifiers, with improved characteristics. Simple practical amplifier circuits and their characteristics are described.

A method for the measurement of the turn-on condition in mos transistors

Abstract: Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.

Semiconductor device with two mos transistors of non-symmetrical type

Abstract: A semiconductor device constituted by two MOS transistors of diffusion-self-alignment type, the source electrode and the gate electrode of one transistor being connected with the source electrode and the gate electrode of the other transistor, respectively. In the device, the mutually connected gate electrodes serve as a new gate electrode, while the drain electrode of said one transistor serves as a new drain electrode and the drain electrode of said other transistor serves as a new source electrode.

Improvements relating to "hall effect" devices

Abstract: 1,243,178 Semi-conductor devices PLESSEY CO Ltd 23 Dec, 1968 [22 Sept, 1967; 7 Feb, 1968], Nos 43259/67 and 6023/68 Heading H1K A Hall effect device comprises a MOSFET having a source 2, a metal gate 6 insulated from the semi-conductor body 1 by an insulating layer 5, and two or more drains 3, 4 the device being arranged so that an appropriate voltage applied to the gate electrode establishes an inversion channel below the oxide layer 5 between the source and the drains, wherein the current flow in that inversion channel, being dependent upon any magnetic field acting on the semi-conductor body, produces a voltage differential between the drains proportional to such a magnetic field due to the deflection of the current by the field preferentially towards one of the drains The device is used to measure magnetic fields The semi-conductor material is silicon, the insulating layer is of silicon oxide and the metal gate is of aluminium