Showing papers on "Pass transistor logic published in 1970"

Multiple phase logic gates for shift register stages

Abstract: Logic gates having an isolation transistor connected to a common point between a load transistor and a two terminal logical network are combined at least partially with logic gates having the output connected to a common point between the load and isolation transistors for forming shift register stages.

Nonsaturated logic circuits compatible with ttl and dtl circuits

Abstract: A nonsaturated logic circuit compatible with TTL and DTL circuits. The output transistor of the logic circuit has its base terminal connected to the junction of a resistor divider pair and its collector terminal connected through a diode to the drive input of the resistor pair. When current flows through the resistor divider pair to turn on the transistor, the diode conducts and the collector of the output transistor is clamped to a voltage higher than that which would otherwise be obtained in the absence of the diode. The transistor does not saturate and the transistor can then be turned off rapidly.

Bidirectional transmission data line connecting information processing equipment

Abstract: A communicating port in an information processing device is equipped with an interconnected logic gating wherein the bidirectional transmission line is connected to an output of one logic gate and to an input of another logic gate. Series and parallel interconnections permit one bidirectional transmission line for each bit of information per device and per port of each device, respectively. A transmitter-receiver circuit pair is disclosed for the logic gating using current mode logic driving a grounded base amplifier.

Complementary metal oxide semiconductor exclusive or gate

Abstract: A complementary metal oxide semiconductor (CMOS) exclusive OR gate is shown having a minimum number of devices for performing the exclusive OR function. The exclusive OR function is performed by utilizing the normal two input signals as logic indicating signals and generating a control signal which is a complement of one of the two logic signals. A different configuration results with the selection of the logic signal from which the control signal is to be generated. The capacitance of the output node or output signal is charged by any one of a plurality of current paths associated with each logic configuration.

Power converter with self-synchronization and bias

Abstract: A power converter having a self-synchronized commutator that causes the power pass transistor in the converter to very rapidly assume its completely turned off state when converter power output is no longer desired. Also provided is apparatus for the converter which supplies base drive to the power pass transistor in response to a triggering pulse. The base drive apparatus has a feed back transistor bias circuit which includes a starting gate that allows the converter to operate during the first several cycles until bias by the bias circuit is provided.

Temperature controlled clocking of logic circuits

Abstract: A variable frequency pulse generator whose pulse repetition rate is controlled as a function of temperature is used as a source of gating signals for a logic array so that the propagation delay of data signals through the logic array is optimized.

Transmission line series termination network for interconnecting high speed logic circuits

Abstract: A series termination network interconnects high speed logic circuits in a transmission line system for transmitting binary ONE and binary ZERO information. When the logic circuit drives the transmission line to a high voltage state, a first impedance branch of the termination network applies a voltage whose magnitude approximates one half of the magnitude of voltage which defines a binary ''''ONE.'''' When the logic circuit switches the line to a low voltage state, corresponding to a binary ZERO, the network through a second impedance branch terminates the line in its characteristic impedance.

Logic circuit for providing a short signal transit time as an integrated element

Abstract: A logic circuit to reduce the transit time of a signal and to make the circuit more easily subject to integration as a single element. The logic circuit includes two logic partial circuits, each having two current switches. The partial circuits are coupled to the bases of two emitter follower transistors with the emitters of the two transistors coupled to a joint gate resistance and to an outlet clamp. The first partial circuit forms an AND linkage and the coupling of the two partial circuits of an additional transistor which is connected in parallel with one of the current switches of the second partial circuit forms an OR gate.

Field effect transistor logic gate with isolation device for reducing power dissipation

Abstract: The logic gate includes a two-terminal logic network comprising one or more field effect transistors Signals on the gate electrodes of the field effect transistors determine the impedance of an electrical path between the terminals During a first phase recurring clock signal, a first semiconductor switch is turned on to connect a first voltage level to the output and to a first terminal of the logic network During the first phase recurring clock signal, the second terminal of the logic network is isolated from a second voltage level by an isolation field effect transistor connected between the second terminal and the second voltage level During a second phase recurring clock signal, the isolation field effect transistor is turned on to permit the output to be connected to the second voltage level through the logical network if a relatively low-impedance path exists during the second phase recurring clock signal

Distributed logic memory cell for parallel cellular-logic processor

Abstract: In a parallel cellular logic processor including a program control unit and a plurality of logic memory cells, all data inputs, except intercell inputs, for any cell are channeled through common input coupling logic to a one-bit intracell bus. The coupling logic is enabled or disabled in accordance with predetermined combinations of states of program control signals and of a plurality of control flip-flop circuits within the cell. Those flip-flop circuits receive data signal inputs from the bus. The same bus also provides data inputs for a data flip-flop circuit and for a data store within the cell. Data input to the bus is provided by way of the coupling logic from a program-selected one of the data flip-flop circuit, the store, an external source, or from program. Additional logic allows communication among cells by way of selective interconnection of their respective intracell buses as determined by further program control signals.

Field effect transistor dynamic logic buffer

Abstract: A buffer circuit for interfacing multi-phase dynamic field effect transistor (FET) logic circuits with conventional logic circuits by converting pulsating logic signals to steady-state logic signals. A sampling stage gates the true and complement phases of the pulsating signal at an equilibrium state, thereby converting the pulsating signal to a steady-state level. An output stage detects the steady-state level and provides the output drive. The buffer is fabricated in accordance with FET technology and is placed on the same monolithic chip with the multi-phase FET circuits. Circuits for generating true and complement phases of the pulsating signal are also disclosed.

Ecl logic circuit

Abstract: An emitter-coupled logic circuit for realization of an AND linkage in positive logic, utilizing a differential amplifier in the form of emitter-coupled transistors, in which a polyemitter transistor forms the control input for the differential amplifier and has the emitter electrodes thereof connected over respective emitter-follower stages to the respective input signal sources.

All transistor logic employing transistors of a single-conductivity-type

Abstract: A logic element fabricated entirely of transistors of a single-conductivity-type and having logic states represented by two ranges of current levels. The transistors are operated in their linear regions and have reference currents passing therethrough for establishing the operating current levels of the logic element.

Logic nand gate circuits

Abstract: Disclosed are logic NAND gate circuits of the type capable of driving a low impedance or a high capacitance load while maintaining relatively fast propagation speed which include a pair of output transistors of one type respectively connected to bias voltage supplies and connected in common to an output circuit, and a plurality of input transistors connected between the bases of the output transistors. A logic 1 input signal at any one of the input transistors produces a logic 0 output signal.

Display annunciator using scr memory and digital logic circuitry

Abstract: Alarm annunciator circuitry comprising input digital logic gates for selectively controlling the conductivity of an SCR bistable memory element. Output digital logic gates are connected to and controlled by both the SCR and the input logic gates to provide both constant DC and periodically varying output control potentials for driving a lamp display portion of the alarm annunciator circuitry.

A system of computer aids for designing logic circuit tests

Abstract: A system of computer programs which aid in generating and validating logic circuit tests is described. Easy to use and available on a time-share computer, the system includes: 1) a preprocessor that translates a logic topology from a simple input language to binary (machine readable) form and determines indistinguishable fault sets, 2) an automatic test sequence generator for combinational circuits, and 3) a fault simulator for asynchronous sequential circuits. The faults considered are those causing any single wire branch to be fixed at logic 0 or fixed at logic 1. Wires which fan-out are simulated with independent faults on each fan-out branch as well as with faults common to all the fan-outs. Gates are simulated with unit delay and are allowed three possible logic values—0, 1 and “don't know”. “Don't know” is the starting value on every gate, representing the uncertainty of internal states when power is applied to a circuit. “Don't know” is also used to settle critical races and oscillations.

Gunn-effect pulse and logic devices

Abstract: Further developments of high-frequency pulse and logic elements employing semiconductor bulk-effect devices are presented. Regeneration gain of high values has been achieved. The effects of circuit and device parameters have been investigated. Experimental and theoretical results are presented on a wide range of logic gates `Exclusive OR?, `Inclusive OR?, `AND? and `Inhibitor?. Designs for three more basic gates, namely, the `Inverter?, `NOR? and `NAND? are proposed. Further experimental results on highspeed transformation of analogue information into pulses are presented. A storage loop employing two Gunn devices has been developed.

Photo-scr card reader circuits

Abstract: In a card reader compatible with electronic data processing equipment, electronic sensing circuits are disclosed which utilize photo-silicon controlled rectifiers in cooperation with logic circuitry. A photo-SCR rear sensor having binary memory is provided comprising a photo-SCR in series with one branch of a logic gate, with another branch connected to a reset pulse generator. An automatic reset sensor comprises a photo-SCR with its cathode in series with the base of a transistor, the anode of the photo-SCR being in series with a first branch of a logic gate and the collector of the transistor being in series with a second gate.

Modelling of transistors for fast integrated logic circuits

Abstract: A large-signal equivalent circuit is described based on a simplified analysis of the operation of a planar transistor. The extra stored charge in saturation and the d.c. characteristics are related to the geometry and impurity profile, and the results are used to define the value of the circuit elements.

Sequential circuits using threshold logic gates

Abstract: The possible uses of threshold logic gates in sequential design problems is investigated, and circuit configurations disclosed. Whilst it is shown that threshold gates can be used to perform all the functions now carried out with Boolean-typo gates, it is concluded that only in the realm of ring and chain counters does threshold realization shove any potential economic advantage.

Ternary logic circuit

Abstract: A ternary logic circuit, in which values of series-connected two controllable resistances to which plus potential and minus potential are respectively applied are controlled by a common input voltage. The output of the ternary logic circuit assuming one of three possible values in accordance with the value of the input voltage is obtained across a nonlinear load resistance connected across the ground and a junction between the two controllable resistances.

High voltage solid state switches for space applications

Abstract: A considerable saving in satellite weight is available if loads such as ion thrusters can be operated directly from high voltage solar cell supplies. Such operation raises the need for a high voltage switch for changing loads and reconfiguring the array at different stages of the mission, Silicon p-n junctions can theoretically be made with very high breakdown voltages but processing technology limits switching devices to a few thousand volts. It is shown that increasing the blocking voltage leads to a corresponding increase in the on state conduction loss for a given current density and that the most efficient use of silicon is made by blocking the voltage over several reverse-biased junctions in series. For off-on d.c switching capability series transistor configurations are superior to series thyristor configurations. Control electrodes of the series transistors will be at widely separated potentials when the switch ie off leading to the selection of optoelectronic triggering methods. A conceptual switch design based on the study uses thyristors in the transistor bias supply to minimize the number of power supplies required.

Multiple-phase logic circuits

Abstract: A multiple-phase field-effect transistor logic circuit of the type normally capable of indicating the logic function of a plurality of variables during only a single portion of a clock pulse period is controlled in such a way that the same logic function is also produced during a second portion (which may overlap the first) of the same clock period. This is accomplished by placing one circuit node at a voltage level indicative of the desired function of the variables during a first clock pulse, storing this voltage for a given interval of time following the first clock pulse, and during a second clock pulse within this interval of time, charging the distributed capacitance present at a second circuit node to this same voltage level.

R70-15 Realization of Sequential Machines with Threshold Elements

Abstract: This paper deals with the realization of the combinatorial logic network of sequential machines with threshold logic elements, with a view to one- level realization. The state assignment problem is already a difficult one, and here it is further complicated by the restriction that the logical gates to be used are all threshold logic elements. This problem is quite important and is worthy of intensive study because, although threshold logic element as a general gate is well known, its value is not fully appreciated unless its applicability in various situations is demonstrated.

Comment on "A Transform for Logic Networks"

Abstract: The above-mentioned paper by K. S. Menger1 presents a restatement of logic functions in terms of the "macroelements" of Galois field (GF) arithmetic. Against the current background of LSI technology, this high- level hardware is going to be a welcome development.