Showing papers on "Physical design published in 1975"

The modified nodal approach to network analysis

Abstract: The nodal method has been widely used for formulating circuit equations in computer-aided network analysis and design programs. However, several limitations exist in this method including the inability to process voltage sources and current-dependent circuit elements in a simple and efficient manner. A modified nodal analysis (MNA) method is proposed here which retains the simplicity and other advantages of nodal analysis while removing its limitations. A simple and effective pivoting scheme is also given. Numerical examples are used to compare the MNA method with the tableau method. Favorable results are observed for the MNA method in terms of the dimension, number of nonzeros, and fill-ins for comparable circuit matrices.

Capacitance models for integrated circuit metallization wires

Abstract: New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer program for multiconductor geometries. These concepts are applied to the wiring of an integrated circuit chip. Capacitances are found for crossovers, vias, and right angle bends for a realistic geometry.

An artwork design verification system

Abstract: Manual and semi-automatic methods of Integrated circuit layout are prone to errors which are often detected only after a sample chip has been fabricated. This paper describes two design verification programs that detect and identify such errors earlier in the design cycle through comparing a designer's logic description with the finished mask artwork. These programs are part of an integrated CAD system developed at RCA laboratories.

Pre-conditioning circuits for MOS integrated circuits

Abstract: An integrated circuit includes circuitry thereon which includes a sensor circuit which detects a change in one of the plurality of inputs to the integrated circuit and generates one or more pre-conditioning signals which control circuitry to set up voltage at various nodes in the integrated circuit to facilitate fast processing of data signals from inputs of the integrated circuit to outputs thereof. Embodiments of the sensor circuit include integrated memory circuits and integrated micro-processor circuits.

Application of the optimization program AOP to the design of memory circuits

Abstract: The memory cycle time of an IGFET read-only memory cell is designed using AOP, a program for automated and interactive optimization of electrical networks. It is shown how AOP allows the user to specify multiple performance objectives and to request analysis, and/or adjoint sensitivity computation, and/or automated optimization for networks described in the ASTAP input language. A. procedure is given for applying optimization to switching circuit design, and a summary is given of the hard experience gained from applying AOP to a practical problem in LSI design.

An iterative algorithm for placement and assignment of integrated circuits

Abstract: In [1] a physical design automation system with a unified approach to physical layout techniques was presented. This method has been extended so that it now is an iterated, assignment placement algorithm which improves the placements reported last year.The problems to be addressed in this paper are those of assignment, placement, and spanning. Assignment is the process of assigning logical elements to integrated circuit chips. Placement is the process of placing integrated circuits on a board. Spanning is the process of converting a set of points which must be connected, to a wire list specifying the manner of connection. There are a number of criteria used to span. In this application, we have the option to use either Kruskal's spanning algorithm [2] or a chaining spanner [3]. The goal of these two processes is to increase the routability of the resulting board, which is often measured by the overall length of wire required (Manhattan distance).

Digital Multiplier Power Estimates

Abstract: Multiplication is an essential operation in digital signalprocessing algorithms. In such applications the organization of a multiplier typically ranges from parallel array to serial-parallel pipeline, with many intermediate possibilities. In this concise paper, the parallel array and serial-parallel pipeline organizations are compared on the basis of the power dissipation needed to achieve a specified multiplication rate. The first-order comparison is intended to serve as a preliminary aid in the design of custom integrated multiplier circuits. The comparison illuminates the differences in circuit technology appropriate for the two organizations. It also indicates that, insofar as custom integrated circuit design is concerned, design parameters other than power dissipation are likely to be the dominant considerations in choosing a multiplier organization.

Digital data system: Physical design

Abstract: The mechanical design of equipment required to build the Digital Data System is described. Economic and technical constraints influencing partitioning, electrical interconnection, and styling are related. An overview is given of the hardware used for terminating loops, multiplexing data streams, and testing for system performance.

Tools II/Design techniques: Design for production: The computer steps in to automate physical design and testing of computers and other electronic equipment

Abstract: Describes the use of computers to automate physical design and testing of computers and other electronic equipment.

An integrated system for computer design

Abstract: A system for computer aided design of computers is introduced which comprises the features: verification of the logical design, automated physical design, computer aided microprogram design, and test generation. The individual components of the system are in productive use for several years.

An absolute digital positioning numerical control system

Abstract: A module containing all the functional components required for a digital absolute positioning process of one axis of a machine tool has been designed and constructed. Circuit realization makes use of integrated circuit elements.

Computer aided LSI circuit design: A relationship between topology and performance

Abstract: The relationship between topology and performance in LSI cell design requires a corresponding relationship between cell layout and circuit analysis computer programs. A computer aided design system demonstrating this is discussed.

The making of an integrated circuit

Abstract: When integrated circuits came into being some 15 years ago, a chip contained as few as a dozen elements. Today's microprocessor chips contain, in some cases, more than 10 000 elements. This article takes the reader through all aspects of the making of an integrated circuit, it gives details of the updating of production techniques and describes the test procedures needed to obtain a high-reliability device

A new approach to the use of a digital computer in circuit design

Abstract: In the presently available C.A.D. systems the extent to which the computer can assist in the design of a circuit is fundamentally limited by the fact that the potential user generally has to perform the initial d.C. and a.c. design of the circuit before such a system can be used. This paper discusses a new approach whereby the systematic hy-hand design procedure is automated so that the circuit designer is able to use the computer throughout the whole design phase. The problem of selecting the optimum set of preferred values is discussed, although at the time of writing an efficient algorithm to solve this nun-linear optimization problem has yet to be developed.

A tolerancing program for practical circuit design

Abstract: A computer aid for practical tolerance assignment has been developed. Monte Carlo analysis including active and passive device statistics is coupled to an interpreter algorithm to converge on device tolerances which maximize circuit yield.