Showing papers on "Pipeline (computing) published in 2022"

Dynamic behavior and failure of buried gas pipeline considering the pipe connection form subjected to blasting seismic waves

Abstract: To ensure the safety of gas pipelines during tunnel blasting excavation, it is of vital significance to investigate the dynamic response of buried gas pipelines under blasting vibration. Based on a great number of engineering examples, a representative buried gas pipeline with a diameter of 1 m and a wall thickness of 10 cm in the urban area was taken as the research object, and a full-scale buried gas pipeline blasting experiment on basis of vibration monitoring and dynamic strain monitoring was designed and implemented Next, 3D numerical models were established to analyze the response characteristics of the buried gas pipeline based on the field experiment, and the reliability of the numerical model was verified by the field monitoring data. Considering the influence of pipeline connection form, the numerical calculation models of the buried gas pipelines with bolted flange joints were established under different blasting scaled distances to supplement the field experiment. The dynamic response characteristics of the pipeline without interface and pipeline with bolted flange joints were further analyzed, and the dynamic response characteristics of bolted flange joints were discussed emphatically. At last, based on the failure mode of pipeline connection and the results of dynamic strain analysis of pipeline in field experiment, the safety evaluation of pipeline with bolted flange joints and pipeline without interface was comprehensively proposed. By comparing the safety control vibration velocity of pipeline with bolted flange joints and pipeline without interface, it is concluded that the flange bolt connection is vulnerable to the harmful effect of blasting vibration and the safety evaluation of pipeline considering bolted flange connection is more reasonable.

v Pipe : A Virtualized Acceleration System for Achieving Efficient and Scalable Pipeline Parallel DNN Training

Abstract: The increasing computational complexity of DNNs achieved unprecedented successes in various areas such as machine vision and natural language processing (NLP), e.g., the recent advanced Transformer has billions of parameters. However, as large-scale DNNs significantly exceed GPU’s physical memory limit, they cannot be trained by conventional methods such as data parallelism. Pipeline parallelism that partitions a large DNN into small subnets and trains them on different GPUs is a plausible solution. Unfortunately, the layer partitioning and memory management in existing pipeline parallel systems are fixed during training, making them easily impeded by out-of-memory errors and the GPU under-utilization. These drawbacks amplify when performing neural architecture search (NAS) such as the evolved Transformer, where different network architectures of Transformer needed to be trained repeatedly. vPipe is the first system that transparently provides dynamic layer partitioning and memory management for pipeline parallelism. vPipe has two unique contributions, including (1) an online algorithm for searching a near-optimal layer partitioning and memory management plan, and (2) a live layer migration protocol for re-balancing the layer distribution across a training pipeline. vPipe improved the training throughput of two notable baselines (Pipedream and GPipe) by 61.4-463.4 percent and 24.8-291.3 percent on various large DNNs and training settings.

Area and energy efficient shift and accumulator unit for object detection in IoT applications

Abstract: Convolutional Neural Networks (CNNs) exhibit significant performance enhancements in several machine learning tasks such as surveillance, intelligent transportation, smart grids and healthcare systems. With the proliferation of physical things being connected to internet and enabled with sensory capabilities to form an Internet of Thing (IoT) network, it is increasingly important to run CNN inference, a computationally intensive application, on the resource constrained IoT devices. Object detection is a fundamental computer vision problem that provides information for image understanding in several artificial intelligence (AI) applications in smart cities. Among various object detection algorithms, CNN has emerged as a new paradigm to improve the overall performance. The Multiply-accumulate (MAC) operations, which are used repeatedly in the convolution layers of CNN, hold extreme computational complexity. Hence, the overall computational workloads and their respective energy consumption of any CNN applications are on the rise. To overcome these escalating challenges, approximate computing mechanism has played a vital role in reducing power and area of computation intensive CNN applications. In this paper, we have designed an approximate MAC architecture, termed Shift and Accumulator Unit (SAC), for the error-resilient CNN based object detection algorithm targeting embedded platforms. The proposed computing unit deliberately trades accuracy to reduce design complexity and power consumption, thus suiting the resource constrained IoT devices. The pipeline architecture of the SAC unit saves approximately 1.8 × clock cycles than the non-pipeline SAC architecture. The performance evaluation shows that the proposed computing unit has better energy efficiency and resource utilization than the accurate multiplier and state-of-the-art approximate multipliers without noticeable deterioration in overall performance.

Exploring more diverse network architectures for single image super-resolution

Abstract: We propose a plug-and-play neural architecture search (NAS) method to explore diverse architectures for single image super-resolution (SISR). Unlike current NAS-based methods with the single path setting and pipeline setting, our proposed method achieves the trade-off between diverse network architectures and search cost. Our proposed method formulates the task in a differentiable manner, which inherits the architecture parameter optimization method from Discrete Stochastic Neural Architecture Search (DSNAS). Besides the straightforward searching of operations, we also search each node in a cell for the activation function, from-node, and skip-connection node, which diverse the searched architecture topologies. The individually searching of skip-connection node avoids skip-connection excessive phenomenon. Moreover, to alleviate the influence of inconsistent architecture between training and testing periods, we introduce random variables into the architecture parameter as regularization. Benchmark experiments show our state-of-the-art performance under specific parameters and FLOPs constraints. Compared with other NAS-based SISR methods, our proposed methods achieve better performance with less searching time and resources. The superior results further demonstrate the effectiveness of our proposed NAS methods.

Classification of Hydrate Blockage and Pipeline Leakage in Natural Gas Pipelines Based on EMD and SVM

Abstract: In this paper, pipeline abnormal events (hydrate blockage and pipeline leakage) were detected by an active acoustic excitation method based on pulse compression. The positions of pipeline a...

Experimental Investigation on Characteristics of Leak Noise in Gas Pipeline Systems

Abstract: Pipelines are essential elements in the daily operation of modern cities, but significant economic loss and environmental damage commonly occur because of pipeline leakage. The acoustic met...

Modeling of Uplift Resistance of Buried Pipeline by Geogrid and Grid-Anchor System

Abstract: This paper presents an experimental and numerical analysis of the uplift resistance of pipelines buried in reinforced soil. The behavior of the system is studied using a set of laboratory e...

Reducing queuing impact in streaming applications with irregular dataflow

Abstract: Throughput-oriented streaming applications on massive data sets are a prime candidate for parallelization on wide-SIMD platforms, especially when inputs are independent of one another. Many such applications are represented as a pipeline of compute nodes connected by directed edges. Here, we study applications with irregular dataflow, i.e., those where the number of outputs produced per input to a node is data-dependent and unknown a priori. We consider how to implement such applications on wide-SIMD architectures, such as GPUs, where different nodes of the pipeline execute cooperatively on a single processor. To promote greater SIMD parallelism, irregular application pipelines can utilize queues to gather and compact multiple data items between nodes. However, the decision to introduce a queue between two nodes must trade off benefits to occupancy against costs associated with managing the queue and scheduling the nodes at its endpoints. Moreover, once queues are introduced to an application, their relative sizes impact the frequency with which the application switches between nodes, incurring scheduling and context-switching overhead. This work examines two optimization problems associated with queues. First, given a pipeline with queues between each two nodes and a fixed total budget for queue space, we consider how to choose the relative sizes of inter-node queues to minimize the frequency of switching between nodes. Second, we consider which pairs of successive nodes in a pipeline should have queues between them to maximize overall application throughput. We give an empirically useful approximation to the first problem that allows for an analytical solution and formulate a performance model for the second that directs implementation toward higher-performing strategies. We implemented our analyses and resulting optimizations in applications built using Mercator, a framework we designed to support irregular streaming applications on NVIDIA GPUs. We demonstrate that these optimizations yield meaningful performance improvements for several benchmark Mercator applications.

Architecture for Silicon-Based Implementation of Regularized Fast Hartley Transform

Abstract: This chapter introduces a computing architecture, based upon the use of a single processing element, for resource-efficient, scalable and device-independent solutions for the parallel computation of the regularized FHT. The solutions exploit partitioned memory for the storage of both data and trigonometric coefficients and seek to maximize the computational density when implemented with silicon-based parallel computing equipment. A pipelined implementation of the generic double butterfly is discussed which exploits SIMD processing within each stage of the computational pipeline and conflict-free parallel memory addressing schemes for both data and trigonometric coefficients. These features lead to an approximate figure of \( \raisebox{1ex}{$N$}\!\left/ \!\raisebox{-1ex}{$P$}\right..{\log}_4N \) clock cycles for the latency of the regularized FHT, this achieved after taking into account the level of parallelism, P, as introduced via the adoption of the partitioned data memory. Four versions of the PE are discussed that are each a simple variation of the same basic design and each compatible with the single-PE recursive computing architecture, enabling trade-offs to be made of the arithmetic and memory requirements against addressing complexity. An FPGA implementation of the regularized FHT is then discussed and its performance compared with two commercially available FFT solutions. The chapter concludes with a discussion of the results obtained.

Graph-PBN: Graph-based parallel branch network for efficient point cloud learning

Abstract: In recent years, approaches based on graph convolutional networks (GCNs) have achieved state-of-the-art performance in point cloud learning. The typical pipeline of GCNs is modeled as a two-stage learning process: graph construction and feature learning. We argue that such process exhibits low efficiency because a high percentage of the total time is consumed during the graph construction process when a large amount of sparse data are required to be accessed rather than on actual feature learning. To alleviate this problem, we propose a graph-based parallel branch network (Graph-PBN) that introduces a parallel branch structure to point cloud learning in this study. In particular, Graph-PBN is composed of two branches: the PointNet branch and the GCN branch. PointNet exhibits advantages in memory access and computational cost, while GCN behaves better in local context modeling. The two branches are combined in our architecture to utilize the potential of PointNet and GCN fully, facilitating the achievement of efficient and accurate recognition results. To better aggregate the features of each node in GCN, we investigate a novel operator, called EAGConv, to augment their local context by fully utilizing geometric and semantic features in a local graph. We conduct experiments on several benchmark datasets, and experiment results validate the significant performance of our method compared with other state-of-the-art approaches. Our code will be made publicly available at https://github.com/zhangcheng828/Graph-PBN .