Showing papers on "Program counter published in 2001"

Kernel mode protection

Abstract: A kernel mode protection circuit includes a processor, a program counter, a kernel program fetch supervisor circuit, a kernel data fetch supervisor circuit, a program memory, a data memory, a flip-flop circuit and two AND circuits. The data memory includes two user memories, protected registers and random access memory (RAM). The program memory includes two user memories and a kernel read only memory (ROM). The circuit may operate in either a user mode (kernel ROM is not accessible) or a kernel mode (kernel ROM is accessible). When in the kernel mode the kernel RAM and certain protected registers are accessible only by a secure kernel. The kernel mode control circuit will reset the processor should a security violation occur, such as attempting to access the kernel RAM while in the user mode. The kernel program fetch supervisor circuit monitors and compares an address within the program counter to a predetermined address, stored within the kernel program fetch supervisor circuit, to determine if a security violation has occurred. The kernel data fetch supervisor circuit monitors and compares the data address to addresses defining a protected memory area. A security violation will occur if the data address is within the protected memory address range and the processor will be reset. A method of kernel mode protection includes the step of fetching a program opcode. If the program opcode is from the kernel memory, the processor is reset. If the program opcode is from a user memory, then the processor may fetch the data operand. If the data operand is fetched from the kernel memory, the processor is reset. If the data operand is fetched from a user memory, the processor is permitted to enter the kernel memory. If a program opcodes is fetched from the kernel memory the processor may continue to fetch operands from either the kernel memory or the data memory. The processor remains in kernel mode and continues to fetch program opcodes until all of the opcodes have been fetched, or until an opcode fetched is from the user memory. If an opcode fetched is from the user memory, the processor switches back to user mode.

Multi-channel, multi-service debug on a pipelined CPU architecture

Abstract: A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Dynamic selection of a compression algorithm for trace data

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Trace control block implementation and method

Abstract: A system and method for program counter and data tracing is disclosed. A trace interface is provided for communication of trace information between a processor core and a trace control block. The trace interface enables various combinations of processor cores and trace control blocks to be implemented.

Trace control based on a characteristic of a processor's operating state

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Method of testing embedded memory array and embedded memory controller for use therewith

Abstract: A memory test controller comprises a test instruction register array for storing a plurality of test instructions, each register having instruction fields for storing instruction data specifying operations to be performed on the memory array, a repeat module for repeating a group of one or more of the test instructions with modified data, the repeat module including storage means for storing instruction field modification data; and each register of the test instruction register array including an instruction field for enabling or disabling the repeat module.

Central processing unit for easily testing and debugging programs

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.

Instruction translator translating non-native instructions for a processor into native instructions therefor, instruction memory with such translator, and data processing apparatus using them

Abstract: The instruction translator includes a translator for reading out a corresponding instruction from the instruction memory in response to the received address to be executed by the processor and translating the instruction in a second instruction architecture into an instruction in a first instruction architecture, an instruction cache for temporarily holding the instruction in the first instruction architecture after the translation by the translator in association with the address in the instruction memory, and a selector for searching the instruction cache in response to the received address of an instruction to be executed by the processor, and based on a determination result of whether or not an instruction corresponding to the instruction of the address is held in the instruction cache, selectively outputting an instruction output by the translator, and the corresponding instruction in the first instruction architecture which has been held in the instruction cache.

System and method for state restoration in a diagnostic module for a high-speed microprocessor

Abstract: A system and method are presented for saving and restoring the state of a diagnostic module in a microprocessor. The diagnostic module contains a complex break state machine, capable of halting the microprocessor at specified breakpoints. These breakpoints are based on combinations of instruction locations and/or data values, along with previous machine states. A problem occurs with prior art diagnostic modules when the processor returns from an exception occurring during a fix-up cycle inserted to handle a data load miss associated with an instruction located in a branch delay slot (the location immediately following a conditional branch instruction). Under these circumstances, the exception handler restores the program counter to the location of the branch instruction, causing the branch to be re-executed. The prior art state machine erroneously updates its internal state a second time when the branch is re-executed. According to the system and method disclosed herein, at each state change the previous machine state saved. Thus, when a branch instruction is re-executed, the complex break state machine of the present invention is restored to its previous state, thereby correcting the error.

Program development support apparatus

Abstract: A program development support apparatus includes a CPU, event detection section, trace data generation section, and trace memory. The CPU executes a target program and outputs instruction address/instruction code data. The event detection section asserts and outputs a section trace start signal upon detecting that the instruction address/instruction code data matches a predetermined instruction address or instruction code set as an event condition in advance. When an instruction code of the instruction address/instruction code data is a branch instruction, or the section trace start signal is active, the trace data generation section outputs an uncompressed instruction address as trace data. When the instruction address is not the branch instruction, and the section trace start signal is not active, the trace data generation section generates a plurality of compressed instruction addresses by compressing the instruction address and then combines the compressed instruction addresses and outputs them as the trace data. The trace memory stores the trace data from the trace data generation section.

Program counter trace system, program counter trace method, and semiconductor device

Abstract: A program counter trace system in which debugging by operating an external debugger and a processor at the same frequency requires fewer external terminals for the connection from the processor to a debugging tool, the system structure is simple, and the PC tracing is carried out efficiently. A processor of the system has means for creating, at every cycle on the basis of the difference between the program counter counts of the previous and current cycles, trace status information representing one of the status where the count of the program counter is the first part of the serial data, the status where the variation of the count is '0', the status where the variation is '1', and the status where an error has occurred and branch information representing that the count has branched, means for serial-converting the count only when the branch information represents the branch status and outputting the serial-converted count, and the means for outputting a trace clock having the same frequency as that of the operating clock of the processor, wherein a debugging tool receives the trace status information and the trace serial data in synchronism with the trace clock.

Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode

Abstract: A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.

User controlled trace records

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Pipelined processor for examining packet header information

Abstract: A packet processing engine includes multiple microcode instruction memories implemented in parallel. For each cycle of the pipeline, an instruction from each of the memories is retrieved based on a program counter. One of the instructions is selected by a priority encoder that operates on true/false signals generated based on the instructions. The selected instruction is executed to thereby perform the packet processing operations specified by the instruction.

Microprocessor employing branch instruction to set compression mode

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates. The subroutine call instruction within the compressed instruction set includes a compression mode which indicates whether or not the target routine is coded in compressed instructions. The compression mode is stored in the program counter register. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.

Processor capable of collecting trace data

Abstract: PROBLEM TO BE SOLVED: To provide a processor capable of accurately and easily collecting an instruction trace (data). SOLUTION: This processor is provided with a trace buffer 18 for storing and holding trace data of an instruction block of a performed program, a PC 14 for storing and holding a current PC value being a value of a program counter used in an instruction fetch cycle of this time, a preceding PC 15 for storing and holding the preceding PC value being the value of the PC 14 used in the preceding instruction fetch cycle, a branch decision processing part 16 for deciding to be a branch occurrence if the difference between the current PC value and the preceding PC value does not coincide with a fixed instruction length with the instruction fetch of this time as a branch decision trigger and generating a collection trigger signal, and a data collection processing part 17 for receiving the collection trigger signal, collecting the preceding PC value and the current PC value as a branch source address and a branch destination address respectively and storing the preceding PC value and the current PC value in the trace buffer 18, detects a branch occurrence on the basis of change of a value of the PC 14 and collects trace data.

Tracing out-of order load data

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Method for reducing power when fetching instructions in a processor and related apparatus

Abstract: In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The instructions of the instruction loop are fetched from a program memory. The instructions are then stored in a register queue. For example, the register queue can be implemented with a head pointer which is adjusted to select a register in which to write each instruction that is fetched. It is then determined whether the processor requires execution of the instruction loop, for example, by checking a program counter (PC) value corresponding to each instruction. When the processor requires execution of the instruction loop, the instructions are output from the register queue. For example, the register queue can be implemented with an access pointer which is adjusted to select a register from which to output each instruction that is required.

Program counter (PC) relative addressing mode with fast displacement

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

DSTRIDE: data-cache miss-address-based stride prefetching scheme for multimedia processors

Abstract: Prefetching reduces cache miss latency by moving data up in memory hierarchy before they are actually needed. Recent hardware-based stride prefetching techniques mostly rely on the processor pipeline information (e.g. program counter and branch prediction table) for prediction. Continuing developments in processor microarchitecture drastically change core pipeline design and require that existing hardware-based stride prefetching techniques be adapted to the evolving new processor architectures. In this paper we present a new hardware-based stride prefetching technique, called DStride, that is independent of processor pipeline design changes. In this new design, the first-level data cache miss address stream is used for the stride prediction. The miss addresses are separated into load stream and store stream to increase the efficiency of the predictor. They are checked separately against the recent miss address stream to detect the strides. The detected steady strides are maintained in a table that also performs look-ahead stride prefetching when the processor stride reference rate is higher than the prefetch request service rate. We evaluated our design with multimedia workloads using execution-driven simulation with SimpleScalar toolset. Our experiments show that DStride is very effective in reducing overall pipeline stalls due to cache miss latency, especially for stride-intensive applications such as multimedia workloads.

Processors having compressed instructions and methods of compressing instructions for processors

Abstract: Instructions of a program are stored in compressed form in a program memory ( 12 ). In a processor which executes the instructions, a program counter ( 50 ) identifies a position in the program memory. An instruction cache ( 40 ) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit ( 42 ) includes a decompression section ( 44 ) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer ( 52 ) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit ( 46 ) fetches an instruction to be executed from the position identified by the cache pointer. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, the cache loading unit performs such a cache loading operation. An updating unit ( 48 ) updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

Microprocessor including a mode detector for setting compression mode

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates. The subroutine call instruction within the compressed instruction set includes a compression mode which indicates whether or not the target routine is coded in compressed instructions. The compression mode is stored in the program counter register. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.

Accessing diagnostic program counter value data within data processing systems

Abstract: A processing system 2 is described including a processor unit 4 and a memory 6. Diagnostic hardware 10 within the processing system 2 includes a shadow PC register 12 that stores a shadow program counter value following the true program counter value held within a program counter register 8 of the processor unit 4. The diagnostic hardware 10 is responsive to a program counter request signal from an external diagnostic system 14 to transfer a program counter value into a scan chain 16 from where it can be returned to the diagnostic system 14. The operation of the processor unit 4 is independent of any of the diagnostic operations and so true real time operation of the system may be observed and de-bugged.

Apparatus, method and system for fast register renaming using virtual renaming

Abstract: A method for renaming a source for use with a processor, the method including providing an instruction, building instruction dependency information based on the instruction, caching the instruction based on the instruction dependency information to provide a cached instruction, renaming a register based on the cached instruction to provide a renamed register, and multiplexing the instruction dependency information and the renamed register to rename the source.

Microprocessor internally provided with test circuit

Abstract: A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an external bus connected to an external device; a test circuit receiving a program counter value of an instruction to be executed by the processor core for outputting a test event signal for testing the microprocessor in synchronization with an operation timing of the processor core; a test event signal output terminal for outputting the test event signal to an external portion of the microprocessor, and an external event request signal input terminal provided for applying the processor core an external event request signal used by the external device to notify an event request with respect to the processor core.

Correlating on-chip data processor trace information for export

Abstract: In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.

Enhancing instruction execution using built-in macros

Abstract: An instruction execution system using an “on-chip” ROM device to store one or more frequently used MACROs. A MACRO CALL instruction is used to redirect an instruction stream to one or more MACROs stored in the ROM device, and to transfer processing control to a MACRO control unit (MCU) and a MACRO Program Counter (MPC). The MACRO program Counter is used to address memory locations within the ROM device, while the MACRO control unit (MCU) will cause instructions to be fetched from MACRO ROM 100, rather than off-chip memory 10, in accordance with the parameters of the MACRO CALL instruction. The number of instructions retrieved from the ROM device to complete execution of a MACRO is determined by an argument of the MACRO CALL instruction.

SDLcheck: A Model Checking Tool

Abstract: SDLcheck is a verification tool developed to support model checking for asynchronous (concurrent) programs written in SDL 1, 2. Given an SDL program and a specification of a desired behavior of the program, SDLcheck generates a verification model that consists of two .-automata, P and T : P models the program and T the specification. Then, the automaton language containment, L(P) . L(T ), is tested by model checking with Cospan [3].

Microprocessor executing data transfer between memory and register and data transfer between registers in response to single push/pop instruction

Abstract: A microprocessor includes a program control unit controlling fetch of an instruction code, an instruction decode unit decoding the fetched instruction code, an address operation unit operating an address of a memory on the basis of the result of decoding by the instruction decode unit and a data operation unit executing data transfer between a control register and a work register and data transfer between the work register and an X memory in correspondence to a single push instruction. Therefore, data stored in the control register incapable of directly pushing data on the memory can be pushed with a single push instruction.

Semiconductor device having self-test function

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.