Showing papers on "Program counter published in 2007"

Configurable software verification: concretizing the convergence of model checking and program analysis

Abstract: In automatic software verification, we have observed a theoretical convergence of model checking and program analysis In practice, however, model checkers are still mostly concerned with precision, eg, the removal of spurious counterexamples; for this purpose they build and refine reachability trees Lattice-based program analyzers, on the other hand, are primarily concerned with efficiency We designed an algorithm and built a tool that can be configured to perform not only a purely tree-based or a purely lattice-based analysis, but offers many intermediate settings that have not been evaluated before The algorithm and tool take one or more abstract interpreters, such as a predicate abstraction and a shape analysis, and configure their execution and interaction using several parameters Our experiments show that such customization may lead to dramatic improvements in the precision-efficiency spectrum

Error correction method with instruction level rollback

Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Programming environment for heterogeneous processor resource integration

Abstract: Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer having a second instruction set architecture, the source code program having specified therein a region of source code for the first instruction set architecture of the processor and a region of source code for the second instruction set architecture of the processor.

Progressive memory initialization with waitpoints

Abstract: A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.

System and method for instruction-level parallelism in a programmable multiple network processor environment

Abstract: A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.

Reversible machine code and its abstract processor architecture

Abstract: A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper.

Trace control from hardware and software

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Link-time compaction and optimization of ARM executables

Abstract: The overhead in terms of code size, power consumption, and execution time caused by the use of precompiled libraries and separate compilation is often unacceptable in the embedded world, where real-time constraints, battery life-time, and production costs are of critical importance. In this paper, we present our link-time optimizer for the ARM architecture. We discuss how we can deal with the peculiarities of the ARM architecture related to its visible program counter and how the introduced overhead can to a large extent be eliminated. Our link-time optimizer is evaluated with four tool chains, two proprietary ones from ARM and two open ones based on GNU GCC. When used with proprietary tool chains from ARM Ltd., our link-time optimizer achieved average code size reductions of 16.0 and 18.5p, while the programs have become 12.8 and 12.3p faster, and 10.7 to 10.1p more energy efficient. Finally, we show how the incorporation of link-time optimization in tool chains may influence library interface design.

Method and system for restoring register mapper states for an out-of-order microprocessor

Abstract: A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.

Suppressing register renaming for conditional instructions predicted as not executed

Abstract: Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to a single instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Register-based instruction optimization for facilitating efficient emulation of an instruction stream

Abstract: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.

Multi-thread processor with multiple program counters

Abstract: A system, apparatus and method for an interleaving multi-thread processing device are described herein. The multi-thread processing device includes an execution block to execute instructions and a fetch block to fetch and issue instructions, interleavingly, of a first instruction execution thread and at least one other instruction execution thread. The fetch block includes at least one program counter, which is allocable and/or corresponds to each instruction execution thread.

Pre-fetch apparatus

Abstract: Apparatus and computing systems associated with data pre-fetching are described. One embodiment includes a processor that includes a first unit to store data corresponding to a load instruction and an instruction pointer (IP) value associated with the load instruction. The processor also includes a second unit to produce a predicted demand address for a next load instruction, the predicted demand address being based on a constant stride value. The processor also includes a third unit to generate an instruction pointer pre-fetch (IPP) request for the predicted demand address. The processor may also include units to arbitrate between generated IP pre-fetch requests and alternative pre-fetch requests.

Error Rate Prediction of Digital Architectures: Test Methodology and Tools

Abstract: This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in digital processors in order to predict error rates. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.

Multiprocessor system for continuing program execution upon detection of abnormality

Abstract: A multiprocessor system includes a plurality of processors, wherein instruction codes of a program executed by the processors are stored in an internal memory of each of the processors, wherein one of the processors includes a program counter configured to indicate an address of a program instruction being executed in the internal memory and an offset register configured to store a predetermined offset value, and wherein upon detecting abnormality due to execution of an illegal instruction code fetched from the internal memory of the one of the processor, the one of the processor fetches an instruction code for execution from the internal memory of another one of the processors based on an address that is obtained by adding the offset value stored in the offset register to the address of a program instruction being executed stored in the program counter.

Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache

Abstract: Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter.

Operation, Control, Branch VLIW Processor

Abstract: An Operation, Compare, Branch (OCB) VLIW instruction word has a memory address, a respective operation code, a respective comparison and branch code; and at least two respective branch pointers. A plurality of OCB VLIW instructions are contained in memory. The branch pointers of a given instruction word connect to a memory address determined by a comparison analysis. The branch pointers form a linked list structure connecting the OCB instructions together, thus no program counter is required. The OCB instructions can be scrambled to realize a branch obfuscated program with built in software protections in that software protection mechanisms can be placed in the lengths and positions of the pointers. The processor architecture allows multiple branching without branch penalties. Other prior art obfuscation techniques may be applied to software programs for the OCB processor.

Multiple microcontrol system and method of self-controlled

Abstract: The present invention discloses a self-controlled multiple microcontrol system and its control method. It is characterized by that in said multiple microcontrol system any one microcontroller kernel logic can make initial address of one insertion program be directly placed in the program counter of another controlled microcontroller kernel logic, so that the program address when the controlled microcontroller kernel logic is interrupted is temporarily stored in the stack memory indicated by stack indicator of microcontroller kernel logic, so that after the insertion program is executed, the controlled microcontroller kernel logic can start to again execute script program from the interrupted point.

ROM addressing method for an ADPCM decoder implementation

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Trace, debug method and system for a processor

Abstract: The present invention relates to a trace, debug method and system for a processor. The method includes the steps: (A) monitoring a program counter (PC); (B) determining if a processor core executes non-successive instruction in accordance with an address data of the program counter; (C) producing a trace break event in order to set the processor core to enter a debug mode if the processor core executes a non-successive instruction; (D) fetching a value of the program counter and a state of the processor core; and (E) sending the value and the state to a host to accordingly form a trace and debug message with respect to the processor core.

Circuit and method for loop control

Abstract: A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction, an interlock generation circuit for generating an interlock until a pipeline of a loop instruction is completed so as to suspend a pipeline process of the loop end instruction, and a loop end evaluation circuit for setting the program counter to the loop start address according to a result of a comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.

Method and apparatus for instruction trace registers

Abstract: A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register.

Mouse shortcut input system and mouse for implementing same

Abstract: The invention relates to a mouse quick input system and a relative mouse, wherein said system comprises mouse and computer host; said mouse comprises at least one decoder, one program counter, several input devices and communication interfaces; the mouse via communication interface is connected to the computer host, while it can be switched to quick input setting mode; and the relative control command of continuous operation can be input by mouse; and one input device of mouse can be appointed as trigger button, to be stored in program counter via communication interface; when the appointed input device is triggered, said decoder can extract out the instructions of program counter, and output the decoded control instruction via communication interface to the computer host, to automatically execute continuous operation relative to the control instruction. The invention can save time.

Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as a static value. A second field of the save instruction encodes whether a value in a register of a processor is saved as an argument value. A third field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Method for reducing booting time in wireless terminal

Abstract: A method for reducing a booting time of a portable terminal is provided to reduce the booting time by copying only the code required for performing a booting mode to a RAM from a NAND memory. A program counter for a code area of a virtual memory is executed. It is checks whether a physical address of the first physical memory, mapped to a virtual address of the virtual memory located by moving the program counter, is found in a page table(106). If the corresponding physical address is not found in the page table, an abort handler assigns the physical address mapped to the virtual address to the page table(108). If the physical address is assigned to the page table, the code for performing the booting mode of the virtual address is copied to the physical address of the first physical memory(109). The code for performing the booting mode is copied to the first physical memory while repeatedly performing previous steps.

Protected function calling across domains

Abstract: Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form, e.g. a permitted branch target instruction 40. If the instruction within the new domain is not a permitted instruction then an access violation response is triggered 42. To assist with backward compatibility for legacy code the permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry. The memory address space may be a virtual memory address space associated with the memory and may comprise several domains each having respective programmable capabilities.

Single-chip micro computer simulation system of multiple micro-controller and method thereof

Abstract: The invention provides a multi-microcontroller single-chip microcomputer simulation system and method, including a simulation controller, at least two microcontrollers and corresponding program counters in a single-chip microcomputer simulator, each program counter corresponds to at least a breakpoint address and stops executed program at the set breakpoint, able to transmit states of each microcontroller through the simulation controller into a PC so as to make single-chip microcomputer simulation program on the PC read the executing states of each microcontroller program at breakpoint address and make a program designer able to accurately obtain executing conditions of the single-chip microcomputer simulator, effectively completing program development and debugging operations

An anomaly in an interpreter using GCC source-code-level register allocation

Abstract: An anomaly of unexpected performance in an interpreter whose frequently accessed variables are manually assigned to hard registers by GCC source-code-level register allocation is presented. A hard-registered virtual program counter and stack pointer as well as a byte-code translation are experimented on both register-rich PowerPC and register-limited Intel x86. According to the study of the anomaly, a hard register should not be assigned singly to a variable in an interpreter due to higher register pressure.

Design of a 16-bit RISC CPU core in a two phase drive adiabatic dynamic CMOS logic

Abstract: We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35 mum standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU.