Showing papers on "Routing (electronic design automation) published in 1986"

The Torus Routing Chip

Abstract: The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.

A unified approach to approximation algorithms for bottleneck problems

Abstract: In this paper a powerful, and yet simple, technique for devising approximation algorithms for a wide variety of NP-complete problems in routing, location, and communication network design is investigated. Each of the algorithms presented here delivers an approximate solution guaranteed to be within a constant factor of the optimal solution. In addition, for several of these problems we can show that unless P = NP, there does not exist a polynomial-time algorithm that has a better performance guarantee.

TimberWolf3.2: A New Standard Cell Placement and Global Routing Package

Abstract: TimberWolf3.2 is a new standard cell placement and global routing package. The placement and global routing proceed over 3 distinct stages. The general combinatorial optimization technique known as simulated annealing is used during the first two stages of the placement. In the first stage, TimberWolf3.2 places the cells such that the total estimated interconnect cost is minimized. During the second stage, TimberWolf3.2 inserts feed through cells as required and the minimization of the total estimated interconnect cost proceeds again in the manner of simulated annealing. The second stage comes to a close following a global routing step, in which the number of wiring tracks needed is accurately estimated. During the third and final stage, local changes are made to the placement whenever such changes result in a reduction in the number of wiring tracks required. TimberWolf3.2 has achieved area savings ranging from 15 to 75% in experiments on numerous industrial circuits.

Using simulated annealing to solve routing and location problems

Abstract: In recent papers by Kirkpatrick et al., an analogy between the statistical mechanics of large multivariate physical systems and combinatorial optimization has been presented and used to develop a general strategy for solving discrete optimization problems. The method relies on probabilistically accepting intermediate increases in the objective function through a set of user-controlled parameters. It is argued that by taking such controlled uphill steps, from time to time, a high quality solution can eventually be found in a moderate amount of computer time. In this paper, we implement this idea, apply it to the traveling salesman problem and the p-median location problem, and test the approach extensively.

A Local Improvement Heuristic for the Design of Less-than-Truckload Motor Carrier Networks

Abstract: The load planning problem for less-than-truckload motor carriers is formulated as a fixed charge network design problem where level of service constraints are represented heuristically through a set of minimum frequencies on links. If direct service is offered between two terminals, it is required to do so at a given minimum frequency, implying not only a fixed charge from adding direct service but also a link cost function that is then flat until the flow on the link exceeds the minimum frequency. A local improvement heuristic is proposed which adds and drops links to and from the network in an intelligent sequence. After each change, the routing of the freight over the network is approximately reoptimized. Empty balancing of equipment is also handled explicitly. The approach has been applied successfully to a network with over 300 terminals; numerical tests on a 140 terminal network are reported.

Mason: A Global Floorplanning Approach for VLSI Design

Abstract: A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The method allows modules to be specified as having a number of possible dimensions, and considers I/O pads as well as layout constraints. As a global improvement over previous floorplanning efforts, an in-place partitioning scheme is applied in conjunction with a combined exhaustive and heuristic bipartitioning approach. Moreover, a global channel routing and module I/O pin assignment scheme is used for floorplan evaluation, whereby module dimensions are chosen in conjunction with routing area, ensuring compact floorplans. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floorplanning. The performance of the program is discussed in terms of several industrial examples.

Method and apparatus for interconnecting processors in a hyper-dimensional array

Abstract: A massively parallel processor is described comprising 65,534 (=216) individual processors organized so that there are 16 (=24 individual processors on each of 4,096 (=212) integrated circuits. The integrated circuits are interconnected in the form of a Boolean cube of 12 dimensions for routing of message packets. Each circuit board carries 32 (=25) integrated circuits and each backplane carries 16 (=24) circuit boards. There are eight (=23) backplanes advantageously arranged in a cube that is 2x2x2. Each integrated circuit on a circuit board is connected to five integrated circuits on the same board which are its nearest neighbors in the first five dimensions. Further, each integrated circuit is also connected to four other integrated circuits on different circuit boards, but on the same backplane; Finally, each integrated circuit is also connected to three other integrated circuits, each on a different backplane. As a result of this arrangement, all message packets are first routed to nearest neighbor ICs located on the same circuit board; all message packets are then routed to nearest neighbor ICs located on the same backplane; and finally all message packets are then routed to nearest neighbor ICs located on different backplanes.

Configuration of physical distribution networks

Abstract: Distribution problems, including vehicle routing and warehouse location problems, are usually formulated by considering a finite number of possible locations for the customers, the warehouses, and vehicle stops. The question of selecting which of these points are actually used (and how) is a mixed-integer programming problem which is difficult to solve. Thus, such a discrete formulation results in a problem that has to be solved heuristically; it also entails a large data preparation effort each time a solution has to be developed in response to changing world conditions. The continuous approach used in this paper attempts to circumvent some of these drawbacks. We consider one source and its customers in a service area; customer locations are modeled by a density surface over the service area. With this information, and data about the cost of inventory and transportation, we can determine the number of transhipment points, and the frequency and routing of all the distribution vehicles. An example is given. The continuous approach does not yield a solution. It gives design guidelines, which ensure near minimum total cost. These design guidelines are based on general properties of optimal solutions (discussed at the beginning of the paper) and on the specific characteristics of the case at hand. Implementation of the guidelines to obtain a feasible configuration requires human intervention. While the continuous method involves approximations (the real world is discrete and considerably more complicated than in our model), it yields insight into the structure of logistic systems. This insight should not only help in the design process; it may well also lead to improved heuristic solution methods for discrete formulations. Hybrid methods may eventually emerge.

Glitter: A Gridless Variable-Width Channel Router

Abstract: In the traditional approach to channel routing, terminals must be located on grid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Terminals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C language, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

Routing through a rectangle

Abstract: In this paper an O(N log N) algorithm for routing through a rectangle is presented. Consider an n-by-m rectangular grid and a set of N two-terminal nets. A net is a pair of points on the boundary of the rectangle. A layout is a set of edge-disjoint paths, one for each net. Our algorithm constructs a layout, if there is one, in O(N log N) time; this contrasts favorably with the area of the layout that might be as large as N2. The layout constructed can be wired using four layers of interconnect with only O(N) contact cuts. A partial extension to multiterminal nets is also discussed.

Glitter: A Gridless V ariable- Width Channel Router

Abstract: In the traditional approach to channel routing, terminals must be located ogrid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with variable wire width and spacing. Termi­ nals are no longer required to be on grids, and nets may even have different wire widths. The new gridless approach which we propose is based on design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, and cyclic constraints. The algorithm has been implemented in C lan­ guage, and will be integrated into our BBL (Berkeley Building-Block Layout) system.

On Nonblocking Multiconnection Networks

Abstract: In the paper, four theorems describing conditions under which a three-stage multiconnection network is nonblocking for different routing strategies are formulated and proved. These theorems hold for any values of the structural parameters of a network. For some networks having a small number of outer stage switches, these theorems give significantly lower numbers of required middle stage switches than theorems currently known.

Automatic Placement A Review of Current Techniques

Abstract: This review provides an overview of the placement function within automatic layout systems. The automatic placement problem is defined and the data abstractions are described. The discussion divides placement algorithms into two classes: constructive and iterative. Applications of the algorithms within layout systems are described. A large number of references is provided to allow use as a guide to placement literature.

Mighty: a rip-up and reroute detailed router

Abstract: For the macro-cell design style and for routing problems where the routing regions are irregular, two dimensional routers are often necessary. In this paper a new routing technique that can be applied for general two-layer detailed routing problems including switch boxes, channels and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear chains and the pins can be on the boundaries of the region or inside it, the obstructions can be of any shape and size. The technique is based on an algorithm that routes incrementally and intelligently the nets in the routing region and allows modifications and rip-up of nets that may impede the complete routing of other nets. The modification steps (also called weak modification) push some segments of nets already routed to make room for a blocked net. The rip-up and re-route steps (called strong modification), remove segments of nets already routed to make room for a blocked connection and is invoked only if weak modification fails. The algorithm is rigorously proven to complete in finite time and its complexity is analyzed. Many test cases have been run and on all the examples known in the literature the router has performed as well or better than existing algorithms. In particular, the Burstein's difficult switch box example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II in all the channels available to us. REFERENCES

Channel Routing in Knock-Knee Mode: Simplified Algorithms and Proofs

Abstract: We give unified and simplified algorithms and proofs for three results on channel routing in knock-knee mode. LetP be a channel routing problem with densitydmax. (a) [Rivest/Baratz/Miller, Preparata/Lipski]. If all nets inP are two-terminal nets thendmax tracks suffice. (b) [Preparata/Sarrafzadeh]. If all nets inP are two- or three-terminal nets then [3dmax/2] tracks suffice. (c) [Sarrafzadeh/Preparata]. 2dmax-1 tracks always suffice.

RECAL—a new efficient algorithm for the exact analysis of multiple-chain closed queuing networks

Abstract: RECAL, a Recursion by Chain Algorithm for computing the mean performance measures of product-form multiple-chain closed queuing networks, is presented. It is based on a new recursive expression that relates the normalization constant of a network with r closed routing chains to those of a set of networks having (r - 1) chains. It relies on the artifice of breaking down each chain into constituent subchains that each have a population of one. The time and space requirements of the algorithm are shown to be polynomial in the number of chains. When the network contains many routing chains, the proposed algorithm is substantially more efficient than the convolution or mean value analysis algorithms. The algorithm, therefore, extends the range of queuing networks that can be analyzed efficiently by exact means.

Routing method for use in wiring design

Abstract: A method for automatically designing the route of the wiring on printed wiring boards, large scale integrated circuit (LSI) chips or the like which can be used to create the wiring design of wiring boards or the like having a plurality of different wiring pattern densities.

Circuit switching network with routing nodes

Abstract: A communication network, for transmitting message signals, comprising a plurality of routing nodes and a method for routing message signals through the network are disclosed. The network comprises a plurality of the routing nodes interconnected in stages. Each routing node includes a memory for storing a destination portion of a message signal. Upon subsequent recall of the stored destination portion, a previous route can be reestablished and a message signal absent the destination portion transmitted therethrough.

Establishing virtual circuits in large computer networks

Abstract: Network routing algorithms generally attempt to provide communication between two nodes by sending data messages along the best or shortest path between them. Unfortunately, in large networks it is difficult to maintain knowledge of such path due to the cost in storage, computation, and communication bandwidth. In an attempt to solve this problem the technique of clustering has been proposed. Clustering generally reduces the cost of routing of by sacrificing optimality. Kamoun has shown that this sacrifice is asymptotically negligible under certain strong assumptions. In this paper we propose a new clustering technique which permits us to obtain optimal paths. However, determining these paths requires some effort and thus the methodology is appropriate only if the paths are then used for many messages in virtual circuit fashion. An application to planar networks gives a quantitative demonstration of obtaining optimal paths with reduced path determination cost.

Routing of network traffic

Abstract: A method and apparatus for routing traffic in a circuit switched network. A call between two nodes interconnected by a direct link is first offered to the direct route, and if that is blocked it is offered to a currently nominated two-link alternative route between the two nodes. If that route is busy, the call is lost, and a randomly chosen two-link route is assigned to be the new current nominated alternative route. The strategy is particularly effective because it is simple, available routes are quickly located and once one available route is found, that same route is used for rerouting further calls until it is full. Trunk reservation protection is applied on alternative routes.

Stochastic Models for Wireability Analysis of Gate Arrays

Abstract: A stochastic model for estimating measures of placement and routing on gate arrays is presented. Three important problems are addressed: estimating the dimensions of the routing channels, estimating the routability of a channel given the number of tracks, and determining the distribution and moments of wire lengths. In the context of wiring space estimation, exact and asymptotic formulas for the dimensions of routing channels are presented. Next, an expression for the probability that a routing channel with a given number of tracks will be routable is derived, and its asymptotic properties are examined. Finally, a model that characterizes the relationship between wire length distributions and partitioning of logic is developed. The model provides a firm mathematical basis for Rent's rule from which the distribution of wire lengths can be determined. That is, Rent's rule, or in general any similar relation, contains all the information about wire lengths. Based on this, estimates for the average wire length are derived. Numerical results from both simulated and real chips are presented.

Artificial Intelligence Approach to VLSI Routing

Abstract: 1. Introduction.- 1.1. Motivation.- 1.2. Outline.- 2. Detailed Routing.- 2.1. Problem Statement.- 2.2. Important Factors in Routing.- 2.3. Previous Approaches.- 2.3.1. Lee Algorithm.- 2.3.2. Line Routing Algorithms.- 2.3.3. Efficient Algorithms for Channel Routing.- 2.3.4. A "Greedy" Channel Router.- 2.3.5. Hierarchical Wire Routing.- 2.4. Characteristics of Previous Approaches.- 3. WEAVER Approach.- 3.1. Congestion.- 3.2. Wire Length.- 3.3. Rectilinear Steiner Tree.- 3.3.1. Steiner Tree.- 3.3.2. Minimal Rectilinear Steiner Tree for a 2xn Grid.- 3.3.3. Minimal Rectilinear Steiner Tree for A mxn Grid.- 3.4. Merging.- 3.5. Vertical/Horizontal Constraint Graph.- 3.6. Intersection.- 3.7. Conflicting Effects.- 4. Knowledge-Based Expert Systems.- 4.1. Productions Systems.- 4.2. OPS5.- 4.2.1. Working Memory.- 4.2.2. Production Memory.- 4.2.3. Interpreter.- 4.3. Applicability of Knowledge-Based Expert Systems to VLSI Design.- 4.3.1. Detailed Routing of VLSI Chips is Amenable to the Techniques of Applied AI.- 4.3.2. Detailed Routing of VLSI Chips is Important, Difficult and a High-Value Problem.- 4.4. Advantages and Disadvantages of Knowledge-Based Expert Systems.- 5. WEAVER Implementation.- 5.1. Problem State Representation.- 5.2. WEAVER Architecture.- 5.3. Blackboard Organization.- 5.4. WEAVER Experts.- 5.4.1. Wire Length Expert.- 5.4.2. Merging Expert.- 5.4.3. Congestion Expert.- 5.4.4. Vertical/Horizontal Constraint Expert.- 5.4.5. Via Expert.- 5.4.6. Common Sense Expert.- 5.4.7. Pattern Router Expert.- 5.4.8. Constraint Propagation Expert.- 5.4.9. User Expert.- 5.4.10. Minimal Rectilinear Steiner Tree Expert.- 5.5. WEAVER Control Structure.- 5.5.1. Nature of WEAVER Expertise.- 5.5.2. Generality of WEAVER Knowledge.- 5.6. Program Organization.- 6. Experiments and Results.- 6.1. Input/Output.- 6.1.1. Input.- 6.1.2. Output.- 6.2. Step by Step Trace of Routing a Channel.- 6.3. Experiments.- 6.3.1. Comparison with Efficient Algorithms for Channel Routing.- 6.3.2. Comparison with the Greedy Algorithm When Both can Route the Channel.- 6.3.3. WEAVER's Routing of a Channel Unroutable by the Greedy Algorithm.- 6.3.4. WEAVER's Solution to Provably Unroutable Channel and Switch-Box by Traditional Algorithms.- 6.3.5. Comparison with Aker's and Lee Algorithms.- 6.3.6. Comparison with the Minimum-Impact Routing Algorithm.- 6.3.7. Burstein's Difficult Switch-Box.- 6.3.8. Terminal Intensive Example.- 6.3.9. Dense Switch-Box Example.- 6.3.10. Conclusion to the Experiments.- 6.4. WEAVER's Performance Under Conditions of Disabled Experts.- 6.4.1. Merging Expert Disabled.- 6.4.2. Congestion and Merging Experts Disabled.- 6.4.3. Via Expert Disabled.- 6.4.4. Vertical/Horizontal Constraint Expert Partially Disabled.- 6.4.5. Rectilinear Steiner Tree Expert Disabled.- 6.4.6. Summary of the Results of Disabling the Experts.- 6.5. Efficiency Issues.- 6.5.1. Possible Execution Time Improvement.- 6.5.2. Writing Efficient OPS5 Programs.- 7. Conclusions and Future Work.- References.

The distance bound for sorting on mesh-connected processor arrays is tight

Abstract: In this paper, We consider the problem of sorting n2 numbers, initially distributed randomly in an n × n mesh-connected processor array with one element per processor. We show a lower bound, based on distance arguments, of 4n routing steps on mesh-connected processors operating in an SIMD mode with no wraparounds in rows or columns, We present an algorithm using a novel approach, which is optimal upto the conslant of the leading term, and hence, succeed in proving the tightness of the lower bound based on distance. Keeping in mind the practical difficulties in implementation of this algorithm, we also present an extremely practical O(n) algorithm amenable for VLSI implementation and for existing mesh- connected computers. All the results in this paper were derived by using a new method of analysis inspired by the discovery of shear-sort or row-column sort.

Chameleon: A New Multi-Layer Channel Router

Abstract: New techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.

An Efficient Memory System for Image Processing

Abstract: Image processing operations require that an image or partial image be stored in a memory system that permits access to p × q, 1 × pq, and/or pq × 1 subarrays of an image array where p and q are design parameters.

Modular data routing system

Abstract: A modular system for controlling the routing of data through a plurality of data terminals includes a number of modules in a tree structure. Each of the modules has circuitry for receiving a data stream. Each of the modules further has a plurality of ports, each port being suitable for transmitting data to and receiving data from data devices such as data terminals and other modules. Each of the modules includes a routing array connected to the ports for serially connecting the ports for flow of the data stream through the operable data devices connected to the ports. The routing array is internally controllable to open a selected one of a plurality of data paths between the ports. At least some of the ports have driver circuits associated therewith for regenerating and converting the data stream as it passes between ports in the selected data path. Each module has an output for supplying the data stream from the module to a destination device. Detecting circuitry is included in each module for automatically detecting a fault between the input and output of that module. The detecting circuitry is responsive to the detection of such a fault to control the routing array to open a fault-free data path between the input and output of the module if any such path exists.