Showing papers on "Sense amplifier published in 1991"

A high-speed clamped bit-line current-mode sense amplifier

Abstract: A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling. >

A sense amplifier with an integral logic function

Abstract: A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.

Semiconductor memory device having block write function

Abstract: A color data transferring circuit, a color data storing circuit, and a block selecting circuit 1020 are provided separately from an input/output buffer circuit, in order to transmit data stored in a color register to a memory cell block. In a block write mode, data applied to a data input/output terminal is stored in the color data storing circuit through color register and the color data transferring circuit. One block selecting gate is selected in response to a block selecting signal from a block decoder, and data stored in each storage element in the color data storing circuit is transmitted to a corresponding memory cell block. Input/output buffer circuit performs normal data writing only through a sense amplifier +I/O block. A semiconductor memory device capable of easily extending the number of bits of block write with a simple circuit configuration is implemented.

Integrating photosensor and imaging system having wide dynamic range with varactors

Abstract: A bipolar phototransistor comprises both an integrating photosensor and a switching element. The base terminal of the bipolar phototransistor is utilized as the switch-control node for the pixel and its emitter is the output node of the integrating photosensor. A plurality of integrating photosensors may be placed in an array of rows and columns, wherein the bases of all bipolar phototransistors in a row are capacitively coupled together to a common row-select line, and the emitters of all bipolar phototransistors in a column are connected together to a column sense line. The input of a sense amplifier is connected to the sense line of each column of integrating photosensors. An integrating sense amplifier according to the present invention includes an amplifying element having an inverting input connected to the sense line. A capacitor, preferably a varactor, is also connected between the inverting input and output of the amplifying element. An exponential feedback element may be provided in the sense amplifiers for signal compression at high light levels.

Multi-level memory cell with increased read-out margin

Abstract: A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.

Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

Abstract: A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.

Read only memory for storing multi-data

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Method and apparatus for substituting spare memory chip for malfunctioning memory chip with scrubbing

Abstract: A computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.

Memory controller with integrated delay line circuitry

Abstract: A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals. The memory state circuitry is clocked by the memory timing control signals. A method of generating memory timing control signals in a memory controller apparatus is also described.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a sufficient element isolation characteristic and a stable device characteristic by a method wherein a higher-concentration channel stop implantation operation is executed for an element isolation region formed by a minimum design rule as compared with an element isolation region whose design rule is not strict CONSTITUTION:A pad oxide film 2 is formed on a P-type silicon substrate 1; in addition, a nitride film 3 is deposited; after that, an opening part of, eg 05mum is formed in a part to be used as an element isolation region of a memory cell part, a sense amplifier part and a decoder part A region other than the memory cell part, the sense amplifier part and the decoder part is 10mum which is thicken than 09mum by a design rule Then, a resist is removed; after that, only a region with an opening width of 05mum is opened; other regions are masked with a resist 4; borons are implanted by using the resist as a mask under conditions of an accelerating voltage of 25keV and a dose of 7X10 cm Then, the resist is removed; after that, only the region with the opening width of 05mum is masked with the resist 4; borons are implanted under conditions of an accelerating voltage of 25keV and a dose of 4X10 cm

Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

Abstract: Derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic-RAMs (DRAMs), to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into the DRAM sensing operation. The authors derive a sensitivity formula for this sensing scheme, using perturbation theory. The perturbation approach is rigorous: it avoids most approximations and ad-hoc assumptions, it introduces no free constants to be determined from simulations, and it yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design. >

Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts

Abstract: A method for maintaining optimum biasing voltage and standby current levels in a dynamic random access memory array, in which row-to-column shorts have been repaired by redirecting the addresses of shorted rows and columns to spare rows and columns. The method partly consists of placing a current limiting device in series with the bias voltage generator output and the nodes between the equilibration transistors of small groups of digit line pairs. The current limiting devices may be either long-L transistors that are in an always-on state, or they may be merely resistive elements, such as strips of lightly-doped polysilicon. The invention effectively isolates the effect of row-to-column shorts in a portion of a DRAM array from the remainder of the array. All digit line pairs tied to a single current limiting device are replaced as a unit if any one or more of the digit lines among the tied pairs is shorted to a word line. The method further consists of holding the common node of each P-type sense amplifiers at no more than a threshold voltage above ground potential during digit line equilibration, rather than at half of power supply voltage, in order to eliminate an unwanted current path from an off-chip power supply, through sundry intervening circuitry, to the common node of a P-type sense amplifier, through the transistors of the P-type sense amplifier, to a bitline which is shorted to one of the rowlines, which are normally held at ground potential during the same period.

Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected

Abstract: A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.

Electronic still camera including an EEPROM memory card and having a continuous shoot mode

Abstract: An electronic still camera using a memory card as a picture recording medium, and a memory card applicable thereto and implemented by an EEPROM (Electrically Erasable Programmable Read Only Memory). A picture signal generated by a CCD array and representative of a picture is routed through an amplifier and an analog-to-digital converter to a signal processing circuit. The picture signal is subjected to interpolation and other similar processing by the signal processing circuit, coded by a compressing circuit, and then written to a buffer memory. These steps proceed on a real time basis. The buffer memory is constituted by a storage device having a reading speed and a writing speed which are different from each other. A memory card controller reads data out of the buffer memory and writes them in the memory card at a low speed matching the memory card.

Apparatus for providing multi-level potentials at a sense node

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage. The initial momentary discharge of the sense node to the first potential allows a sense amplifier to behave like a conventional sense amplifier during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground. Decreasing the second potential to a third potential at the initiation of the precharge cycle effects a decrease in the equilibrate potential of the digit lines, thereby increasing the "high logic window" as reflected in an increase in cell margin and a decrease in soft error rate (SER).

Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Abstract: A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells. Performance is improved in at least three ways, including improved write speed, decreased SER by reducing subthreshold leakage, and reduced power consumption.

Semiconductor integrated circuit device including a plurality of cell array blocks

Abstract: A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.

Floating gate non-volatile memory with deep power down and write lock-out

Abstract: A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.

Method and apparatus for testing the continuity of static random access memory cells

Abstract: The method of testing a memory array of SRAM cells each of which includes memory transistors, bit and bit# lines, precharge circuitry, and an output test terminal involving the steps of connecting selected bit and bit# lines of selected SRAM cells to the output test terminal, disconnecting the memory transistors of the selected SRAM cells from the bit and bit# lines, disconnecting the bit and bit# lines from the precharge circuitry, enabling the column select circuitry to select the columns of the selected SRAM cells, applying a preselected level voltage to the output test terminal, and measuring any current which flows.

Semiconductor memory unit having redundant structure

Abstract: A semiconductor memory unit comprising a plurality of main memory blocks formed on a chip and respectively having redundant cells, a plurality of auxiliary memory blocks formed on the chip and having substantially the same structure as the main memory block, a memory circuit for storing the address of a main memory block having a defect which cannot be restored by redundant cells, and a redundant control circuit for selecting an auxiliary memory block when a defective main memory block is selected.

Method of manufacturing logic semiconductor device having non-volatile memory

Abstract: The present invention discloses a logic semiconductor device having a non-volatile memory in which a memory cell portion and a logic circuit portion are formed on a single semiconductor substrate, and a floating gate of the memory cell portion and a gate of the logic circuit portion are made of different materials, and a method of manufacturing the same.

Semiconductor memory device having a testing function and method of testing the same

Abstract: A semiconductor memory device is provided with a plurality of bit lines, a plurality of word lines, a memory cell array including a plurality of memory cells each coupled to one bit line and one word line, and a varying part for varying a capacitance of at least a selected one of the bit lines in response to a predetermined signal which indicates a test mode in which an operation of the semiconductor memory device is tested

Memory IC testing apparatus with redundancy circuit

Abstract: A testing apparatus for a memory IC with a redundancy circuit includes a first memory, a counter, a second memory and a comparator. The first memory has a memory area for row addresses or column addresses of a target memory with a redundancy circuit, and stores row addresses or column addresses of defective bits of the target memory. The counter counts the number of defective-bit containing rows or columns of the target memory. The second memory stores a number of rows or columns of spare memory cells provided in the redundancy circuit. The comparator compares a count value of the counter with the number stored in the second memory. When the count value of the counter exceeds the number of rows or columns of spare memory cells stored in the second memory, it is considered unrepairable and test is terminated. When the former value does not exceed the latter, memory cells in a defective-bit containing row or column in the target memory are replaced with memory cells in an associated row or column in the redundancy circuit based on the row addresses or column addresses stored in the first memory.

Semiconductor memory device having cross-point DRAM cell structure

Abstract: For providing a semiconductor memory device that includes a plurality of cross-point memory cells each having a fine device structure and a high capacitance, a bit line is formed on an insulating substrate, and a word line is disposed above the substrate so as to cross the bit line. A MOS transistor with a vertical structure, whose gate electrode is used as the word line, is provided on the bit line. A MIM (Metal-Insulator-Metal) capacitor is provided on the MOS transistor.

Nonvolatile semiconductor memory device including access code circuitry

Abstract: In a nonvolatile semiconductor memory device having a plurality of word lines, bit lines, sense lines, nonvolatile semiconductor memory cells, column selecting transistors, a page buffer circuit, data lines, an input driver/sense amplifier, an input buffer an input/output register and a comparator, a secret access code is defined in such a manner that a first secret access code is latched in the page buffer circuit, a second secret access code inputted by the input buffer is compared with the first secret access code read by the input/output register by bytes in the comparator, and if the first and second access codes match, the first secret access code latched in the page buffer is written in the cells of the row line designated in advance among the nonvolatile memory cells.

Security circuit for protecting data stored in an internal memory of a microcomputer

Abstract: A security circuit for protecting data stored in an internal memory of a microcomputer has a first memory for storing an externally applied security code and a latch circuit for latching a key code in order to read data stored in the internal memory A comparator determines whether or not the security code in the first memory and the key code in the latch circuit are in agreement and outputs comparison results for storage in a second memory A read control circuit uses the comparison results stored in the second memory as the basis for prohibiting reading of data in the internal memory when the security code and the key code are not in agreement, and for using an externally applied output control signal as the basis to control reading of data stored in the internal memory when there is agreement

Pipelined, time-sharing access technique for an integrated multiport memory

Abstract: A pipelined, time-sharing access (PTA) technique that realizes an integrated multiport memory for high-speed signal processing is described. N/2-port memory cells, with less area and a wider operating margin, are used for the N-port memory function. Memory cell access for multiple ports is performed serially within one cycle, instead of being an ordinary parallel operation. Memory operation is divided into three pipeline cycles-address selection, memory cell access, and data I/O operation-to reduce the cycle time. A 64-kb four-port memory was fabricated with conventional two-port memory cells to verify the effectiveness of this technique. A 16 ns memory operation with a wide margin was observed under a 3 V supply voltage. >

Serially accessible semiconductor memory with multiple level storage cells

Abstract: According to this invention, in a data bit array for storing data, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A check bit array for storing check data has a number of bits smaller than that of the data bit array. In the check bit array, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A row address decoder selects one row from the check bit array and the data bit array in accordance with address data. Three sense amplifiers are connected to one column of the check bit array and the data bit array. The three sense amplifiers detect levels of data read from a memory cell in accordance with different reference levels in data read access, receive a plurality of precharge levels corresponding to 4-level write data, and write one of the precharged levels in the corresponding memory cell in accordance with write data. A data converter converts levels of data detected by the sense amplifiers into 2-bit data in data read access and selects a sense amplifier in accordance with write data having a plurality of bits in data write access. An input/output circuit serially outputs data supplied from the data converter in data read access and supplies external write data to the data converter in data write access.

A semiconductor memory with multiplexed redundancy

Abstract: An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.

Apparatus for generating test signals

Abstract: An apparatus for generating test signals, preferably for use in an integrated circuit tester, comprises a sequencer, a Vector Memory and a Waveform Memory. The Vector Memory is addressed by the sequencer and contains coded waveform information, which is, in turn, decoded into control information by the Waveform Memory. For this purpose, the data outputs of the Vector Memory control the address inputs of the Waveform Memory. The data outputs of the Waveform Memory control circuitry like a formatter or a comparator which link the waveform information with timing information from one or more edge generators. The formatters, comparators etc. are, in turn, in connection with a device under test. The present apparatus provides full flexibility in the generation of formats and waveforms and, in particular, timing and format changes "on the fly", i.e. without additional delay. Flexibility may be increased if the Waveform Memory is reprogammable.