Showing papers on "Sequential logic published in 1982"

Hardware Specification with Temporal Logic: An Example

Abstract: The use of temporal logic for the specification of hardware modules is explored. Temporal logic is an extension of conventional logic. While traditional logic is useful for specifying combinational circuits, it is shown how the extensions of temporal logic apply to the specification of memory, as well as the safeness and liveness properties of active circuits representing processes. These ideas are demonstrated by the example of a self-timed arbiter. An implementation of the arbiter is also given, and its formal verification by a kind of reachability analysis is discussed. This verification approach is also useful for finding design errors, as demonstrated by an example.

A unified switching theory with applications to VLSI design

Abstract: Classical switching theory is shown to have deficiencies when applied to the analysis and design of MOS VLSI circuits. A new logic design methodology called CSA theory is described here which overcomes many of these deficiencies. It is based on three primitive component types: connectors that perform wired-logic operations, switches representing controlled connectors, and attenuators representing resistive load devices. Four basic types of logic values are recognized: Boolean 0 and 1 values, unknown or indeterminate U values, and the high-impedance state Z. The number of logic values can be increased systematically to improve modeling accuracy using a concept of logical strength, which corresponds to current drive capability in analog circuits. It is shown that both the behavior and layout of most types of MOS logic circuits, including contact, gate, and nonclassical mixed circuits, can be treated in a uniform and rigorous manner using CSA network models with either four or seven logic values. The use of a digital charge-storage element called a well to represent sequential behavior is examined. CSA theory is applied to two VLSI design issues, inverter synthesis and fault simulation.

Configurable logic gate array

Abstract: An integrated circuit having an array of logic gates adapted to provide predetermined logic functions on a plurality of input logic signals fed to the gate array and produce such predetermined logic functions as output signals at a plurality of array output terminals. A plurality of output buffer circuits are coupled between the outputs of an interconnected gate and the array output terminals. A circuit is provided for electrically decoupling each one of the plurality of logic output buffer circuits from the plurality of array output terminals in response to a common control signal. In a preferred embodiment, the control signal is fed to a single one of the plurality of array output terminals. With such arrangement, in response to the control signal, all logic outputs of the gate array are electrically isolated from other components wired to the gate array thereby allowing diagnostic testing of these other components in spite of the fact that they are wired to the gate array. It also allows parametric testing of three-state condition of the buffers required to be three-state buffers by the customer for normal device operation.

A Comparison of Universal-Logic-Module Realizations and Their Application in the Synthesis of Combinatorial and Sequential Logic Networks

Abstract: This paper surveys the six possible variants of the basic universal-logic-module, ULM.2, and considers possible circuit realizations for each. A comparison of these variants in terms of circuit complexity, propagation delay, and total number of input/output connections is pursued, and detailed statistics generated to compare with previously published optimum data using conventional NAND and NOR gates.

Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis

Abstract: In this paper we present a new approach to fault diagnosis in sequential circuits based on an effect–cause analysis. This represents an extension of our previous work dealing with combinational circuits [1]. The main tool of our approach is the Deduction Algorithm, which deduces internal values in the circuit under test based upon the test results. The deduced values are used for fault diagnosis, which encompasses both fault detection and location.

Multi-level logic circuit

Abstract: A Multi-Level Logic Circuit is described, with the hardware of the circuit capable of being constructed to operate in a chosen base. The circuit includes at least: (a) One input level detector which can receive one or more multi-level inputs, (b) Control switching means, and (c) An output level generator delivering a single multi-level output. Various logic gates operating in any base can be derived from the generalized circuit of this invention. Basic multi-level logic gates include an (n-1) complementer, where an output of (n-1-a) is generated from a discrete input "a" where n is the base for which the circuit is constructed. A complementary maximum gate is also described in which the circuit provides the (n-1) complement of the highest logic level detected on input lines to the input level detector. Various other multi-level logic circuits can be constructed by combining the multi-level complementer, and multi-level complementary maximum gates. Circuits are also described where there are more than one input level detector or control switching means to provide binary operations on inputs to the multi-level logic circuits, e.g. addition, multiplication, in any desired base. Circuits are illustrated, constructed to operate in base 10. The multi-level logic circuit is similar to a binary circuit in that it operates on discrete logic levels. It is not an analog circuit.

Method and apparatus of compensating for variations in signal propagation time existing within the channels of a multi-channel device

Abstract: An input apparatus for a logic analyzer is disclosed which receives a plurality of logic signals from a probe, the plurality of logic signals being received at different points in time, the input apparatus being capable of generating a corresponding plurality of logic signals in response thereto, the time of generation of the corresponding plurality of logic signals substantially coinciding with the time of generation of a corresponding reference logic signal. The input apparatus comprises a plurality of tapped delay lines corresponding to the plurality of received logic signals. A controller controls the amount of time delay for each delay line associated with each received logic signal. The controller continues this control function until the time of generation of the corresponding plurality of logic signals substantially coincides with the time of generation of the corresponding reference logic signal. The controller provides the control function by comparing the time of receipt of one of the plurality of logic signals with the time of receipt of a reference logic signal and controlling the amount of time delay of the associated delay line until the time of generation of the corresponding logic signal substantially coincides with the time of generation of the corresponding reference logic signal.

Protection circuit for memory programming system

Abstract: A protection circuit inhibits the generation of a write-erase signal to an E2 PROM when the logic supply voltage falls below a predetermined threshold level. A differential-input amplifier compares the logic supply voltage with a fixed potential and when the logic voltage drops below the threshold, a transistor coupled to the write-erase signal generator switches to its conductive state inhibiting further occurrences of the signal.

Masked arithmetic logic unit

Abstract: An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.

High speed-low power gallium arsenide basic logic circuit

Abstract: The present invention provides a high-speed low-power gallium arsenide basic logic circuit which is capable of being driven by either emitter coupled logic or gallium arsenide logic level signals to provide combinational logic gating such as OR-AND, OR-NAND, OR-AND-OR and OR-AND-NOR capable of driving directly either emitter coupled logic or gallium arsenide logic circuits. The combinational logic gating is basically accomplished by diode logic which performs other functions and which requires less area on an integrated circuit chip than active switching transistors.

Digital data synchronizing circuit

Abstract: A circuit for reproducing a signal associated with synchronization with a digital data signal. The digital data signal includes a combination of a plurality of pulses each having a predetermined pulse width. The reproducing circuit comprises a logic circuit for discriminating the pulse width of at least one of the plurality of pulses, an oscillator and a frequency divider connected with the oscillator and responsive to the output of the logic circuit to generate a clock signal timed with the output of the logic circuit.

A Fault Simulation Methodology for VLSI

Abstract: Some deficiencies of existing simulators in the context of VLSI design and testing are considered. A fault simulation approach based on CSA (connector-switch-attenuator) theory is defined which overcomes many of these deficiencies. The CSA circuit elements and logic values needed to model combinational circuits are described and applied to the analysis of various types of MOS circuits. A charge-storage element called a well is introduced to simulate sequential behavior. It is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner.

MOS logic circuit responsive to an irreversible control voltage for permanently varying its signal transfer characteristic

Abstract: A MOS logic circuit including a known MOS logic circuit arrangement having a particular input/output signal transfer characteristic and a control gating circuit including an FET connected to the known MOS logic circuit arrangement, the gate of which gating circuit receives a control voltage derived from an irreversible control voltage generator utilizing a fuse. Under the control of the irreversible control voltage, the MOS logic circuit can permanently change the known logic circuit arrangement's signal transfer characteristic without varying its logic function.

Apparatus including a programmable set-up and hold feature

Abstract: An input apparatus for a multi-channel device, such as a logic analyzer, is disclosed, the input apparatus providing the multi-channel device with a programmable set-up and hold feature. The multi-channel device acquires a logic signal from a product under test, the logic signal having associated therewith an actual set-up and hold time with respect to an external clock signal. The actual set-up and hold times are entered into the multi-channel device via a keyboard and a display. The device has stored therein a desired set-up and hold time required by the logic signal relative to the external clock signal. In accordance with the actual and the desired set-up and hold times, the multi-channel device changes the relative orientation of the acquired logic signal with respect to the external clock signal, along the time axis until the set-up and hold times of the acquired logic signal are changed from the actual value to the desired value. As a result, the multi-channel device can be used to troubleshoot any product under test regardless of the set-up and hold times of the generated logic signals, relative to an external clock signal, associated therewith.

Computing system with multifunctional arithmetic logic unit in single integrated circuit

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.

High speed low power MOS buffer circuit for converting TTL logic signal levels to MOS logic signal levels

Abstract: MOS semiconductor address buffer for converting TTL logic states to a MOS logic state requiring only a single clock and having improved power efficiency. The address buffer operates in response to the single clock pulse to set a latch and connect the latch to output drives for providing complementary MOS logic levels.

Full adder using complementary MOSFETs

Abstract: The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry output signal C in response to three input signals X, Y and Z.

A New Method for Improved Delay Characterization of VLSI Logic

Abstract: A new method is described which allows determination of Ton and Toff delays of logic gates on VLSI chips as function of load by frequency measurements, that means with automatic testsystems and computer aided evaluation

Binary logic structure employing programmable logic arrays and useful in microword generation apparatus

Abstract: Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occupied by the encode programmable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups. When used to provide microword generation apparatus for a microprogrammed digital system, the encode programmable logic array is responsive to a plural-bit system instruction for producing a plural-bit instruction identification signal uniquely representative of such system instruction but having a smaller number of bits than the system instruction. In such case, the decode programmable logic array is responsive to the instruction identification signal and to number signals produced by a sequence counter for producing a sequence of microwords needed to execute the system instruction.

Integrated circuit having a plurality of current mode logic gates

Abstract: An integrated circuit employing a plurality of current mode logic gates operable with a low power consumption and at a high speed is disclosed. The integrated circuit comprises a terminal for receiving a reference signal from the outside, an input stage current mode logic gate supplied with an input signal from the outside and the reference signal, an internal reference voltage generator circuit for generating an internal reference voltage having an intermediate value of binary logic levels of the output signals of the input stage current mode logic gate, and an internal stage current mode logic gate supplied with the output signal from the input stage logic gate and the internal reference voltage.

Digital supervisory circuit for a telephone system

Abstract: The digital supervisory circuit comprises an amplitude comparator and EXCLUSIVE-OR gate to provide an output signal indicating the difference in time an input signal is above and below a predetermined reference potential. This output signal is integrated in an up-down binary counter and also is coupled to a first logic circuit under control of the counter which provides a ring present supervisory signal when a first threshold is exceeded and a second logic circuit under control of the counter which provides a switch hook detection supervisory signal when a second threshold is exceeded. A hit-timing circuit is provided coupled to the counter and the first and second logic circuits to prevent response of the counter and second logic circuit to line transients.

A Logic Minimizer for VLSI PLA Design

Abstract: This paper describes LOGMIN, a new, interactive computer aided logic design tool. LOGMIN automates the increasingly complex problems of VLSI PLA design which has made the specification, manipulation, minimization and generation of PLAs difficult to do by hand. LOGMIN allows the specification of both combinational functions and sequential machines. Combinational functions may be described using a variety of operators, intermediate variables or PLA code. A State Machine Description Language (SMDL) was developed for the specification of sequential machines. This paper describes the background and motivation for LOGMIN, the algorithms used and the grammar for SMDL. Several examples are provided.

Low power consuming decoder circuit for a semiconductor memory device

Abstract: The present invention is directed to a decoder circuit for a semiconductor memory device including a logic circuit for receiving an address signal as an input thereto and selecting an address in response thereto and a load in the logic circuit. The load comprises a pair of transistors connected in parallel, wherein one of the pair of transistors turns ON for a specified period in synchronization with the address signal, and the other of the pair of transistors turns ON when the logic circuit is in a selected condition and turns OFF when the logic circuit is in a non-selected condition.

Integrated circuit including logic array with distributed ground connections

Abstract: Logic arrays which apply outputs to logic circuitry are made to exhibit improved noise characteristics which, in turn, improve performance of the logic circuitry. The improvement is achieved by providing a distributed ground throughout the logic array to provide local closed loop paths for discharge currents generated in the array. In this manner, discharge currents are not allowed to flow in ground or power BUSES and so do not affect the driven logic circuitry.

NAND Logic gate circuit having improved response time

Abstract: A NAND logic gate circuit having a first input circuit receiving a first input signal, an inverter circuit for inverting the output of the first input circuit, a second input circuit for receiving a second input signal, an AND gate circuit for producing a logical AND output signal in response to the outputs of the inverter circuit and the second input circuit, and a PNP transistor responsive to the second input signal having a low value for controlling the value of the output signal of the first input circuit independent of the value of the first input signal. The NAND gate circuit has a faster response time to changes in the value of the first input signal than comparable prior art circuits and reduces the current flow to the second input terminal when the first input signal is high and the second input signal is low.

Memory circuit for producing analog output

Abstract: H and L logic signals are written in a memory in a ratio between the numbers of the H and L logic signals corresponding to the magnitude of an analog signal. The memory is cyclically read out and the output therefrom is smoothed by a smoothing circuit to provide an analog output.