Showing papers on "Sequential logic published in 1989"

Combinational profiles of sequential benchmark circuits

Abstract: A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed. >

Digital Design: Principles and Practices

Abstract: From the Publisher: This popular volume provides a solid foundation in the elements of basic digital electronics and switching theory that are used in most practical digital design today -- and builds on that theory with discussions of real-world digital components, design methodologies, and tools. Covers a full range of topics -- number systems and codes, digital circuits, combinational logic design principles and practices, combinational logic design with PLDs, sequential logic design principles and practices, sequential logic design with PLDs, memory, and additional real-world topics (e.g., computer-aided engineering tools, design for testability, estimating digital system reliability, and transmission lines, reflections, and termination). This edition introduces PLDs as soon as possible, emphasizes CMOS logic families and introduces digital circuits in a strongly technology-independent fashion, covers the latest Generic Array Logic (GAL) devices, offers expanded coverage of ROM and RAM system-level design, and provides additional design examples. For those needing a solid introduction or review of the principles and practices of modern digital design. Previously announced in Oct. 1992 PTR Catalogue.

Gentest: an automatic test-generation system for sequential circuits

Abstract: A description is given of Gentest, with emphasis on STG2, a sequential test generator that uses the Back test-generation algorithm and the Split value model. The performance of STG2 on a Convex C-1 computer is compared with that of its predecessor, STG1 and STG1.5. Results are also presented for another set of experiments for Gentest on a Sun 3/60 workstation. >

On path selection in combinational logic circuits

Abstract: In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates, it is verified that signal propagation delays along a set of selected paths fall within allowed limits by applying appropriate stimuli. It has previously been suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. Here, algorithms to select such sets of paths with minimum cardinality are given. >

Estimate of signal probability in combinational logic networks

Abstract: Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency. >

Frequency multiplier with programmable order of multiplication

Abstract: This frequency multiplier circuit with variable multiplication order is of the type comprising a comb generator that receives, at input, a signal at the base frequency to be multiplied, and gives, at output, a composite pulse signal having a plurality of harmonic lines of the base frequency, said comb generator being followed by a pass-band filter that can be tuned selectively to one of these harmonic lines. The comb generator is formed by logic means having two complemented outputs, a synchronous input, the actuation of which controls the changing of these outputs from one logic state to the other, and a asynchronous input, the actuation of which controls, independently of the state of the synchronous input, the changing of these outputs to the states complementary to those generated by the actuation of the synchronous input. The base frequency signal is biased beforehand so that its excursion takes place around the transition voltage controlling the change from one logic state to the other, said signal being applied to the synchronous input of the logic means, and a first output of these means is connected to asynchronous input and the second output delivers said composite pulse signal to the the pass-band filter.

An economical scan design for sequential logic test generation

Abstract: A method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit is presented. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles to reduce sequential depth. Tests for the resulting circuit can be efficiently generated by a sequential logic test generator. An independent control of the scan clock allows the insertion of scan sequences within the vector sequence produced by the test generator. Experimental results on a 5000 gate circuit show that a test coverage above 98% could be obtained by scanning just 5% of the flip-flops. In addition, the authors give the design of a scan flip-flop to reduce the input pin and signal routing overheads in a single-clock design. >

Functional comparison of logic designs for VLSI circuits

Abstract: A method is described for circuit equivalence which proceeds by reducing the question of whether two circuits are equivalent to a number of a more easily answered questions concerning the equivalence of smaller, related circuits. The primary technical contribution is a technique for discovering internal equivalences and using them to show the equivalence of the outputs. The method involves the use of signatures to reduce the number of potentially equivalent signals, and the use of the min-cut algorithm to reduce the original problem to related problems with fewer independent inputs. The method can be used to extend the power of any given equivalence checking algorithm. The authors report the result of experiments evaluating their technique. >

A directed search method for test generation using a concurrent simulator

Abstract: A description is given of the application of a concurrent fault simulator to automatic test vector generation. As faults are simulated in the fault simulator a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. Experimental results are presented showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, it has been possible to generate: (1) initialization sequences; (2) tests for a group of faults; and (3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach. >

A synthesis and optimization procedure for fully and easily testable sequential machines

Abstract: The authors outline a synthesis procedure which beginning from a state transition graph (STG) description of a sequential machine produces an optimized fully and easily testable logic implementation. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic and the test sequences for these faults can be obtained using combinational test generation techniques alone. The sequential machine is assumed to have a reset state and be R-reachable. All single stuck-at faults in the combinational logic and the input and output stuck-at faults of the memory elements in the synthesized logic-level automaton can be tested without access to the memory elements using these test sequences. Thus this procedure represents an alternative to a scan design methodology. The area penalty incurred due to the constraints on the optimization are small. The performance of the synthesized design is usually better than that of an unconstrained design optimized for area alone. The authors show that an intimate relationship exists between state assignment and the testability of a sequential machine. They propose a procedure of constrained state assignment and logic optimization which guarantees testability for both Moore and Mealy machines. >

NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations

Abstract: The problem of encoding the states of a synchronous Finite State Machine (FSM), so that the area of a two-level implementation of the combinational logic is minimized, is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible boolean representation. In this paper we present algorithms for their solution, based on a new theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solutions have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained.

BALLAST: a methodology for partial scan design

Abstract: In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation. >

Fast test generation for sequential circuits

Abstract: An efficient sequential circuit test generation algorithm is presented. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of an initial time-frame algorithm and correct implementation of a solution to the previous state information problem. The initial time-frame algorithm determines the number of time-frames required to excite the fault under test and the number of time-frames required to observe the excited fault. This step saves the test generator from doing unnecessary search in the input space. Test generation is done strictly in forward time. The algorithm saves good machine circuit state after test generation to aid in future test generation. Faulty machine state is set to unknown whenever test generation for a fault is begun. This solves the previous state information problem, which has often been ignored by existing test generators. >

Test generation for highly sequential circuits

Abstract: The authors address the problem of generating test sequences for stuck-at faults in nonscan synchronous sequential circuits. They present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, the authors decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification, and fault-free state differentiation. They describe fast algorithms for state justification and state differentiation using the ON sets and OFF sets of flip-flop inputs and primary outputs. The decomposition of the testing problem into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault-free rather than the faulty machine, and the use of efficient techniques for cube intersection result in significant performance improvements over previous approaches. >

Massively distributed simulation engine

Abstract: A simulation engine for logically simulating a logic network, which is divided into several levels of hierarchy. At the lowest level is a logic chip which has stored in an instruction memory a sequentially executed program of logical operators and operand addresses. The operand addresses refer to an input memory of the chip. The next highest level is the logic unit, on one circuit board, comprising a plurality of such logic chips. Each of the logic chips of the unit has its input memory receiving the same data from an input bus and a local bus and provides as its output one of the bits of an output bus and one of the bits of the local bus. At the next level, called a cluster, several logic units have their input and output buses interconnected by a plurality of switch units. All the logic chips of the several logic units operate in parallel with the exchange of data through the switch units. Several clusters can be combined into a super cluster by connecting together two or more sets of switch units.

Sequential Circuit Test Generator (STG) benchmark results

Abstract: The authors report on the results of running a version of the Sequential Circuit Test Generator (STG3) on the ISCAS-89 sequential circuit benchmarks. First, they present a brief history of STG and briefly describe the algorithms used. They then describe the conditions under which the experiments were run and give the benchmark results. No particular problems were encountered when running STG3 on the benchmark circuits, except for those circuits with many untestable faults. STG3 determines that faults are undetectable fairly quickly, taking only 0.98 s on a totally untestable circuit. The major problem with the circuits considered untestable was in initializing the circuit state. >

Multi-level logic optimization using binary decision diagrams

Abstract: A multilevel logic optimizer, which is based on the transduction method, is introduced. The original transduction method is good for optimization, but its calculation time and storage area increase exponentially with the number of inputs because of the use of truth tables. To save CPU time and memory space, the authors implemented this algorithm using ordered binary decision diagrams (OBDD) as the data structure for representing logic functions. Since OBDD does not become as large as other representations, it can handle large circuits without partitioning. >

ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits

Abstract: The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the proposed test generation approach fully exploits the beneficial techniques that have successfully been used for combinational circuits by the automatic test pattern generation system SOCRATES. In particular, the authors discuss a learning procedure for global implications not only over reconvergent fanout, but also over time frames as well as static and dynamic unique sensitization techniques. After introducing a couple of intelligent heuristics employed for guiding and supporting the decision-making process, the authors report some preliminary but encouraging experimental results. >

Synthesis of delay fault testable combinational logic

Abstract: The synthesis of combinational logic which is robust delay fault testable is developed. In a circuit, any reconvergent fanout may result in the presence of blocked paths and/or paths which can be sensitized only if some other path is also sensitized. Implicit don't care terms are used to detect these problems and a local transformation at the reconvergence point is used to upgrade the delay fault testability of the circuit. The sharing of terms in a multilevel circuit is preserved to the greatest extent possible. Good results have been obtained based on an implementation of the algorithm in the LISP programming language on a TI Explorer machine. >

Delay test generation for synchronous sequential circuits

Abstract: The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

Delay test generation for synchronous sequential circuits

Abstract: The author presents a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at-fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. Faults for which no delay test sequence exists are termed sequentially delay redundant. The author describes means of eliminating sequential delay redundancies in logic circuits. He presents a partial-scan methodology for enhancing the testability of difficult-to-test or untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. It is shown that an intimate relationship exists between state assignment and delay testability of a sequential machine. A state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability is described. Preliminary experimental results using the test generation, partial-scan, and synthesis algorithms are presented. >

Built-in-test by signature inspection (bitsi)

Abstract: A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

Flexible imbedded test system for VLSI circuits

Abstract: A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip flop ranks, or it can go serially through the flip flop components of a given rank.

The effect of logic block complexity on area of programmable gate arrays

Abstract: The authors explore the tradeoff between the area of a programmable gate array (PGA) and the functionality of its logic block. A set of industrial circuits is implemented as PGAs using tools for technology mapping, placement, and routing. A simple model allows the exploration of a range of programming technologies and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology

Multi-Level Logic Simplification Using Don't Cares and Filters

Abstract: Simplification of a multi-level network is used to perform form transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time. In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.

Test circuit and scan tested logic device with isolated data lines during testing

Abstract: A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test. A third interface circuit is provided for an asynchronous input of data from the logic device to the coupling circuit except during test wherein the asynchronous input is isolated from the coupling circuit. A control circuit controls the third interface and the coupling circuit during test in response to an external test enable signal. In this way, the second interface is operable during test to store data in the storing circuit for input to the logic device, and the first interface transfers test results from the logic device to the storing circuit for extraction through the serial scan path.

An approach to functional level testability analysis

Abstract: The authors present an approach to testability analysis applicable to circuits containing functional modules described behaviorally. They consider two types of modules-combinational modules described by binary decision diagrams and sequential modules defined by state tables. Controllability and observability measures for such modules are defined, and algorithms are developed for computing them. The method has been applied to a few small modules and circuits, and appears to be feasible. The combinational measures, applicable to both combinational and sequential modules, indicate the probability of setting a lead to a particular value or observing the effect of a signal change at an output. The sequential measures, also applicable to both types of modules, give estimates of sequence lengths needed for controlling and observing any lead in the circuit. These two measures together give an indication of not only the difficulty in deriving tests for a circuit but also the length of test sequences that may be needed. >

The design of random-testable sequential circuits

Abstract: A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns. >

Cascadable optical combinatorial logic gates

Abstract: Combinatorial logic devices are presented in which data signals interact with an enable signal in the device to move the enable signal outside its prescribed time slot when one or both of the data signals are present. Data signals are discarded within the device to avoid propagation through subsequent logic device stages. Such logic devices are particularly well suited to all-optical realizations in which soliton pulse signals are used. These devices exhibit high gain, cascadability and potentially large fanout capability.

The essence of logic circuits

Abstract: Introduction boolean algebra applied to logic circuits designing combinational logic circuits combinational logic circuits in regular forms symmetric and iterative circuits sequential logic circuits software tools. Appendices.