Showing papers on "Silicon oxide published in 1979"

Process for making large area isolation trenches utilizing a two-step selective etching technique

Abstract: A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask. The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.

Silicon nitride and silicon oxide etchant

Abstract: An etching solution for etching composite structures of silicon nitride on silicon oxide on silicon substrates which etches the silicon nitride at a rate equal to or faster than the silicon oxide which comprises concentrated aqueous hydrogen fluoride in a high boiling, organic solvent.

Reactive ion etching

Abstract: A silicon oxide, nitride, and/or oxynitride surface on a substrate is selectively etched at a rate greater than that of the substrate by a reactive ion etching employing a gaseous mixture containing a fluorocarbon and a second gas capable of supplying hydrogen.

Method for fabricating a semiconductor device by controlled diffusion between adjacent layers

Abstract: A method for fabricating a semiconductor device is disclosed, which comprises forming a first polycrystalline silicon film containing an impurity such as phosphorus or boron on the surface of a silicon oxide film, forming an impurity-free second polycrystalline silicon film contiguous to the first polycrystalline silicon film, diffusing the impurity contained in the first polycrystalline silicon film into the second polycrystalline silicon film to form an impurity-containing region, and oxidizing the impurity-containing region to electrically separate the first and second polycrystalline silicon films from each other by the resulting oxide.

An electron diffraction study of amorphous silicon oxide films

Abstract: Amorphous silicon oxide films have been examined by high energy electron diffraction using the sector-microphotometer method of data collection common to gas phase electron diffraction. This data was analyzed with a least-squares procedure that is designed to minimize extraneous detail in the radial distribution function obtained by the Fourier sine transform of the interference function. The results of this analysis for thin film SiO 2 show that the overall bonding topology of the thin film agress well with that of bulk (vitreous) SiO 2 examined by X-ray diffraction. The experimental short distance parameters for the films whose composition was determined to be ∼SiO 1.3 , SiO, and SiO 0.8 are found to be consistent with those expected for a mixture of tetrahedrally bonded amorphous Si and SiO 2 phases in which the scale of the Si-like and SiO 2 -like regions is of the order of a few basic tetrahedral units. This result is in agreement with previous examinations of SiO powder by X-rays and a previous examination of thin silicon oxide films by electron diffraction.

Barium titanate series ceramics having a positive temperature coefficient of electric resistance

Abstract: Barium titanate series semiconductive ceramics having a positive temperature coefficient of electric resistance are disclosed. The ceramics consist mainly of a barium titanate series compound and contain specifically limited small amounts of titanium dioxide, silicon oxide, aluminum oxide, at least one element selected from the group consisting of rare earth elements, yttrium, bismuth, antimony, niobium, tantalum and tungsten, at least one element selected from the group consisting of manganese, copper, iron and chromium, and zinc oxide. The ceramics are low in the variance of electric resistance values and have a low water absorption and hence are low in the change of electric properties due to the lapse of time.

Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide

Abstract: A process for making dielectrically isolated silicon integrated circuits which use silicon oxide filled trenches to provide isolation is described. To minimize damage to the silicon, the trenches are filled by sequentially annealed oxidation process which involves alternately growing some oxide and then annealing to relieve stresses before growing more oxide.

Methods for minimizing silicon regrowth in aluminum films

Abstract: The transport of polycrystalline silicon into an overlying aluminum film and silicon regrowth in the metal medium under heating at 500 °C was examined as a function of doping level and grain size of the silicon. Such regrowth was eliminated through phosphorus doping and was substantially reduced for increased grain size. These results are consistent with a mechanism of silicon grain‐boundary transport in the films. The necessity for a silicon oxide layer at the aluminum‐silicon interface, if regrowth is to occur, is also indicated.

Mos semiconductor device and fabricating method of the same

Abstract: PURPOSE:To prevent the increase of a threshold voltage and an irregularity thereof in a MOS semiconductor device by forming the same conducting type high impurity density buried layer as the substrate at the deep position in either one side of source or drain region side in a channel region. CONSTITUTION:An n -type source region 21 and a drain region 22 are formed on a p-type silicon substrate 11, a polycrystalline silicon oxide film 18 as the gate electrode is formed through a silicon oxide film 17 as a gate insulating film on the channel region between the regions 21 and 22, and the same conducting type high impurity density p -type buried layer 10 as the substrate 11 is formed at deep position at the drain region 22 side in the channel region. Further, a field oxide film 16 and a p -type channel stopper are formed thereon.

Sos cmos semiconductor device and its manufacture

Abstract: PURPOSE:To reduce the area necessary for isolation between a region becoming a p- type region and a region becoming an n-type region and obtain a flat and smooth surface thereof by forming a groove having extremely narrow and abrupt edge in the boundary between the portion becoming a p-type region and the region becoming an n-type region by a dry etching technique. CONSTITUTION:A thermal oxidation film 3, a silicon oxide film 4 and an oxide film 5 including phosphorus are sequentially accumulated on the surface of an SOS substrate having an n-type epitaxial silicon 2 on a sapphire 1. Then, grooves A are formed, and the oxide film 5 and the film 4 are removed between the grooves A and A subsequently. Then, boron ion is implanted thereto to obtain a thermal oxidation film 7 having a flat and smooth surface. Thereafter, high density n-type region 8, a high density p-type region 9 and a gate oxide film 10 are formed thereon. Thereafter, an opening is perforated at the contact portion, and necessary wire 11 is formed with aluminum.

The effects of oxygen doping and subsequent annealing in nitrogen on the structure of polycrystalline silicon

Abstract: We have used reflection high‐energy electron diffraction (RHEED) to study (i) the structure (surface crystallinity) of semi‐insulating polycrystalline silicon (SIPOS) layers having a wide range of oxygen doping and (ii) the effect of subsequent annealing on that structure. Our results are consistent with a model in which (i) excess O exists in the form of silicon oxide at the intergrain boundaries, (ii) the presence of this intergrain oxide tends to prevent grain growth during annealing, and (iii) sufficiently large O doping completely suppresses observable grain growth during annealing.

Aluminum metaphosphate optical fibers

Abstract: Aluminum metaphosphate optical fibers are disclosed. In a specific embodiment, aluminum metaphosphate, doped with from 10 to 30 mole percent of diboron trioxide, is found to yield an optical fiber which combines the desirable properties of both high numerical aperture and low material dispersion. The fiber is nonhygroscopic and has a high melting temperature. The index of refraction of the glass may be lowered by doping with silicon dioxide. Consequently, a graded fiber may be made by increasing the concentration of silicon oxide from the core to the cladding.

Preparation of plastic antireflection film

Abstract: PURPOSE: To obtain an antireflection film having improved adhesion, resistance to boiling water and scuffing, by evaporating silicon monoxide and zirconium in the presence of oxygen, and by forming an oxide layer of higher degree than said compound on a plastic base board. CONSTITUTION: A gas containing oxygen is introduced to evaporate silicon monoxide (which may contain a high-degree silicon oxide) and zirconium or its monoxide in a vacuum system. The vapor is then deposited on a plastic base board, if necessary ion bombarded, by radiofrequency ion plating or vacuum deposition in combination, to form a film of higher degree than said compound. A combination of the compounds provides an antireflection film comprising, e.g. films of silicon oxide of refractive index (RI) about 1.7, zirconium oxide of RI 1.2, and silicon dioxide of RI l.5 on the base film of silicon dioxide. COPYRIGHT: (C)1980,JPO&Japio

The effect of heat treatment on unpassivated and passivated gallium arsenide surfaces

Abstract: The effects of various heat treatments on the surface of GaAs crystals have been studied using Rutherford scattering and channelling of alpha particles. The heat treatment was in the form of isochronal anneals in the temperature range 350–750°C. The crystals were heated in both flowing dry nitrogen and in vacuum (∼ 10−6 torr). The changes in surface-stoichiometry and surface disorder were measured and the results, for both free and silicon oxide passivated surfaces, are discussed. It is shown that preferential loss of As occurs for the unpassivated surfaces heated in nitrogen. However, the unpassivated surfaces heated in vacuum show no degradation, even up to 750°C. The behaviour of the passivated surfaces was dominated by the mechanical properties of the silicon oxide layer, which suffered from adhesion and blistering problems. Only for annealing in nitrogen at 550°C did the silicon oxide behave successfully as a passivating layer and prevent the out-diffusion of Ga and the evaporation of As.

Method of manufacturing a semiconductor device using different etch rates

Abstract: A method of manufacturing a semiconductor device is disclosed in which a surface of a silicon body is provided successively with a silicon oxide layer and silicon nitride layer. Parts of the surface are exposed and are subjected to an oxidation treatment so as to obtain a sunken oxide pattern, during which treatment an undesired small silicon nitride strip or "white ribbon" is formed, and remaining parts of the silicon nitride layer and the underlying silicon oxide layer are then etched away. In the etching treatment, silicon nitride is etched more rapidly than silicon oxide and silicon, while silicon nitride is etched at approximately the same rate as silicon, so that the undesired "white ribbon" is removed.

Production of semiconductor device

Abstract: PURPOSE:To obtain a process for production of the semiconductor device having shallow junctions with good accuracy by forming N type phosphorus doped layers in the shallow surface regions of P type base regions, then forming polycrystalline silicon layers thereafter diffusion-forming emitter regions to a required depth CONSTITUTION:The P type base region 2 covered with a silicon oxide layer 1 is provided with an emitter diffusing opening 3 by opening the hole in the insulator layer 1 being a thermally oxidized film in its slallow region 21 In this state the substrate is exposed to an oxidative atomosphere 4 to be deposited with phosphours in the opening, whereby an extremely shallow phosphorus doped layer 5 is formed Next, a polycrystalline silicon layer 10 without cotaining any impurity is formed through vapor growth, after which the substrate is exposed to a phosphorus oxychloride atmosphere, whereby a phosphorus doped layer 7 is deposited Next, getter process is sufficiently accomplished, after which an alkali metal getter layer 7 is removed and an emitter region 8 is provided through diffusion Thereafter, the polycrystalline silicone layer 10' is left part of electrodes

Interface and dielectric properties of the n-indium-phosphide silicon-oxide system

Abstract: The small signal conductance and capacitance of metal/silicon oxide/n‐indium‐phosphide structures have been measured as a function of bias voltage at various frequencies from 1 to 100 kHz. The conductance method has been used to determine the surface state density, which rises as the conduction band is approached, passing through 3×1012 cm−2 eV−1 at an energy 30 meV below the conduction band edge. The data display a strong frequency and temperature dependence as the semiconductor approaches accumulation. The dispersion in this region fits a Maxwell–Wagner model suggesting that such effects are caused by the inhomogeneous nature of the dielectric in our samples.

Method for Preparing An Abrasive Silicon Oxide Layer

Abstract: An abrasive coating of silicon oxide is prepared by subjecting silane and an oxygen-containing gaseous compound such as N2O, CO2 or H2O to glow discharge. The coating may be used to lap submicron articles, e.g. for making video disc style from diamond.

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

Abstract: Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300° C. to about 400° C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250° C. Preferably the insulating layer is naturally grown silicon oxide layer.

Roduction of liquid crystal display element

Abstract: PURPOSE:To obtain a substrate for production of liquid crystal elements of good adhesiveness of transparent conductive films by providing an electric insulation type metal oxide film on glass substrate then coating and baking an indium compound solution thereon. CONSTITUTION:A film of an electric insulation type metal oxide such as silicon oxide, titanium oxide or other is provided by such a method as vapor deposition, coating and baking of metal alcoholate solution or other on a glass substrate to provide an underlying layer, on which a solution of an indium compound, e.g., a solution obtained by dissolving indium nitrate in acetyl acetone and diluting this with ethyl alcohol is coated and baked. The use of the abovementioned solution by adding a tin compound as activating agent for the purpose of improving the conductivity of the transparent conductive film will give equally good results.

Formation of fine pattern

Abstract: PURPOSE:To simplify the formation of a pattern by a method wherein ions are implanted in accordance with a prescribed pattern in the surface layer parts of a film to be processed being formed on the surface of a substrate or of a film on the substrate to form quality changed layers, and the film to be processed is etched using the layers as masks CONSTITUTION:After a silicon oxide film 2 and a polycrystalline silicon film 3 are stacked in order on a silicon semiconductor substrate 1, ions of oxygen, etc, are implanted in the surface layer of the polycrystalline silicon film to form locally quality changed layers 8 Using the quality changed layers 8 as masks, plasma etching is performed in CF4 gas plasma 6, for example, to form a fine pattern of polycrystalline silicon Accordingly, because the fine pattern can be formed directly without necessitating a photo-etching process, the manufacturing process is shortened and the defect of pattern generating by the adhesion of foreign material and refuse can be reduced

Mosfet transistor mfg. process - by depositing polycrystalline silicon layer over gate oxide layer and forming silicon nitride mask before ion implanting source and drain

Abstract: The MOSFET transistor is made along with others by depositing a layer (5) of polycrystalline silicon onto the surface of the s-c substrate (1) covered by a first insulating layer (2) with a window corresponding to the FET area and by the gate oxide layer (4). A second insulating layer (silicon nitride) is then deposited on the polycrystalline silicon. This layer is structured so that it does not cover those regions where the source (11) drain (12) and gate contacts will be. The source and drain zones are then formed by ion implantation. The exposed polycrystalline layer is converted into silicon oxide, the second insulating layer removed and source and drain contact zones formed.

LVV Spectra of Si, SiO2 and Si3N4

Abstract: LVV Auger spectra of Si, SiO2 and Si3N4 are discussed in terms of features of PES spectra and X-ray emission spectra of these materials. We show how the p-predominance in the valence bands contributes to the L2, 3VV spectra of the respective materials. We also show how departure from ideal stoichiometry in SiO2 and Si3N4 can be easily detected by the additional structure arising from free silicon in evaporated silicon oxide and CVD-nitrides.

Monolithic distributed resistor-capacitor device utilizing polycrystalline semiconductor material

Abstract: A distributed resistor-capacitor device which is highly reproducible with near ideal electrical characteristics comprises a doped semiconductor body forming a substrate (10), an insulating layer (12) on a major surface of the substrate, and a doped polycrystalline semiconductor material (14) on the insulating layer. The polycrystalline layer (14) is the resistor and cooperates with the substrate as the capacitor. Fabrication of the device is compatible with integrated circuitfabri- cation and can be used with field-effect and bi-polar junction transistors. The body may comprise a single crystalline silicon substrate with the layer (12) comprising silicon oxide. The semiconductor material (14) may be polycrystalline silicon.

Pattern forming method

Abstract: PURPOSE:To form the pattern in an extermely simple and precise way by providing the organic substance thin film on the substrate surface from which the oxide is to be removed and then coating the oxide forming material on the substrate surface including the thin film with the heating process. CONSTITUTION:Organic material film 3 such as ethyl cellulose or the like is screen- printed into a frame form to, for example, tin oxide film 2 on transparent glass substrate 1, and then dried for 10 minutes at 150 deg.C to form a thin film. After this, the oxide forming material such as coating film 4 of ethyl silicate or the like is formed on the entire surface of film 2 of thin film 3, and a high-temperature heat treatment is given in the air to obtain the element substrate containing silicon oxide film 5. Thus, the pattern can be formed in an extremely simple and precise way.

Semiconductor integrated circuit

Abstract: PURPOSE:To provide a trench type element isolation region which has excellent thermal stress resistant properties and dielectric strength by a method wherein insulating films are formed on the surfaces of trenches for element isolation and polycrystalline or amorphous silicon films containing oxygen atoms or nitrogen atoms are buried at least in the lower parts of the trenches. CONSTITUTION:Trenches 15 for element isolation is provided so as to reach the inside of a P-type silicon substrate 1 from an epitaxial layer 3. Polycrystalline silicon films 5 are buried in the trenches 15 with silicon oxide films 4 which are formed on the surfaces of the trenches 15 between. Especially, oxygen atoms are introduced into the polycrystalline silicon films 5 to maintain their specific resistivity at about 10 OMEGA-cm. A bipolar transistor composed of a collector drawing-out region 7, a collector electrode 8, a graft base region 9, a base electrode 10, an emitter region 11 and an emitter electrode 12 is provided between the two element isolation trenches 15 as a semiconductor element. As the material buried in the trench 15 is insulating polycrystalline silicon, charges such as electrons and positive holes are not stored and crystal defects are not introduced into the silicon substrate.