Showing papers on "State (computer science) published in 1970"

A Method for the Design of Fault Detection Experiments

Abstract: A methodical procedure for organization of fault detection experiments for synchronous sequential machines possessing distinguishing sequences (DS) is given. The organization is based on the transition checking approach. The checking experiment is considered in three concatenative parts: 1) the initial sequence which brings the machine under test into a specific state, 2) the α-sequence to recognize all the states and to establish the information about the next states under the input DS, and 3) the β-sequence to check all the individual transitions in the state table.

State Estimation in Power Systems Part I: Theory and Feasibility

Abstract: State estimation is a digital processing scheme which provides a real-time data base for many of the central control and dispatch functions in a power system. The estimator processes the imperfect information available and produces the best possible estimate of the true state of the system. The basic theory and computational requirements of static state estimation are presented, and their impact on the evolution of the data-acquisition, data- processing, and control subsystems are discussed. The feasibility of this technique is demonstrated on network examples.

Program execution tracing system improvements

Abstract: A tracing program method that copies into an area within a tracing program each instruction to be executed and traced in a manner which makes each traced instruction subservient to the tracing program. A hardware instruction counter of the computer system addresses the tracing program, rather than the program being traced. A programmed instruction counter controlled by the tracing program maintains the address within the traced program of its next instruction to be executed and traced. While being traced, the traced program is effectively executing its data using the same instruction sequence that it would use on the same data as if the tracing program was not in the system and as if the traced program was alone operating on its data. The tracing method can control the entire computer system while tracing the programs that are being executed by the system. The tracing method can wholly or partially trace a program by sampling it over a cycle determined by time or by instruction count, or by an overriding manual control. When not tracing, the tracing program can go into a quiescence state, therein it retains control of the system in preparation for later tracing, but permits a speedup in the execution of subservient instructions. The tracing method requires neither machine interrupts, nor modifications to the hardware or to the traced program code, for control of the computer system. The tracing method provides data for each traced instruction in a form that can be subsequently analyzed by a disclosed trace analysis program so that the output from a single run of the tracing method can be used any number of times for varying types of analyses.

Multiprogrammable, multiprocessor computer system

Abstract: A multiprogrammable, multiprocessor computer system is disclosed including at least one central processor for performing arithmetic and logic operations, at least one input/output processor for performing input and output operations, storage means connected with each of the processors and adapted for storing central processor programs associated with the central processor and channel programs associated with the input/output processor, and a multiprocess controller connected to each of the processors for accepting control of a program from a processor in response to an interrupt and providing control of another program to that particular processor in accordance with a predetermined priority arrangement including a plurality of activity state indicators, one associated with each of the programs in the storage means, each of the activity state indicators representing the activity state of its respective program.

Segmentized memory module and method of making same

Abstract: A method of utilizing a memory array or module containing inoperative memory cells or bits is accomplished by electrically segmentizing the memory module and then permanently isolating the segment(s) containing inoperative bits to form a segmentized but functional memory module. This is accomplished by forcing the address means associated with the segment(s) containing inoperative bits to a permanent, single binary state which is inconsistent with the binary address codes for the memory cells in the segment(s) containing the inoperative bits.

Asynchronous circuit and system

Abstract: An asynchronous logic circuit is provided having three stable states, namely two information states and a neutral state. Information is transferred between cacaded such circuits wholly under the control of such circuits and at a rate determined by the delay times through various gates. Feedback is employed between each circuit so that for any two given circuits the transfer logic is IN -> NI, I representing an information state and N representing the neutral state. Reversible cascaded chains are discussed as well as parallel feed-in and feed-out of information, and fan-in, fan-out and recirculating loops of information. The cascaded circuits (nets) employ interface circuits comprising in most instances a specified part of the basic net circuit.

Finite state automation: definition of data communication line control procedures

Abstract: The notions of finite state automata, state transition graphs and tables and the set of regular languages being accepted (generated) by such automata are well known. But for some reason these notions have not been rigorously applied in the definition of data communication line control procedures. It is the objective of this paper to do so and to show the naturalness of this approach. We claim that we thereby arrive at a complete, precise and unambiguous definition. Others have attempted this before us. They have, however, not used the descriptional tool of finite state automata. Any one or all of these references thus form the basis on which we will compete and we shall use essentially the line control procedures which these documents set out to define.

Remote computer control of an industrial process

Abstract: The development of a nonlinear dynamic model of an industrial process is summarized. The model includes additive stochastic terms and not all the state variables were accessible. Nonlinear state estimation was approximated by a linearized Kalman filter and the control algorithm was from dynamic programming. The development of software and hardware for a remote on-line computer control experiment is then described, in which the industrial plant was connected to a process control computer some 130 miles away by a regular telephone channel.

Phase detection circuit

Abstract: Apparatus for detecting the phase relationship and potential difference between the phases of a polyphase electrical circuit and for interrupting the circuit if a shift in phase or a decrease in potential difference occurs beyond acceptable limits. The current-passing terminals of a controlled switching device such as a silicon controlled rectifier are coupled in series with a control device across two phases of the polyphase circuit, while the control electrode such as the gate of the silicon controlled rectifier is coupled to a third phase. So long as the proper phase relationship and potential difference are maintained, current through the circuit is sufficient to maintain the control device in a first state. Should a phase shift or a decrease in potential difference, or a combination thereof, in excess of the allowable limits occur, current through the circuit is insufficient to maintain the control device in that first state, and the power applied from the polyphase source to its load is interrupted.

Buffered analog converter

Abstract: A converter for converting a binary digital code into an analog representation. The converter includes a timing system which is operated by a clock signal to produce a synchronized timing pulse. The digital information is fed into a holding register, and such is gated through a plurality of gates that feeds the complement of the digital code into a counter. The relative duration of the output signal of the last state of the counter in a logic "one" state corresponds to the weight of the digital code being fed into the holding register.

Distributed logic memory cell for parallel cellular-logic processor

Abstract: In a parallel cellular logic processor including a program control unit and a plurality of logic memory cells, all data inputs, except intercell inputs, for any cell are channeled through common input coupling logic to a one-bit intracell bus. The coupling logic is enabled or disabled in accordance with predetermined combinations of states of program control signals and of a plurality of control flip-flop circuits within the cell. Those flip-flop circuits receive data signal inputs from the bus. The same bus also provides data inputs for a data flip-flop circuit and for a data store within the cell. Data input to the bus is provided by way of the coupling logic from a program-selected one of the data flip-flop circuit, the store, an external source, or from program. Additional logic allows communication among cells by way of selective interconnection of their respective intracell buses as determined by further program control signals.

The Administrative Foundations of the Chinese Fiscal State

Abstract: On subjects ranging from trade to democratization, there has lately been a wave of laments about China's development belying Western expectations. Yet these disappointments often come with misunderstandings of the very institutions that China was expected to adopt. Chinese taxation offers a sharp illustration. When China introduced a tax system suited for the market economy, it fully intended tax collection to rely on self-assessment, audits, and the rule of law. But this Western approach was quickly jettisoned in favour of one that emphasized monitoring of taxpayers and ex ante interventions, at the expense of deterrence and truthful reporting norms. The Chinese approach surprisingly matches recommendations made by recent economic scholarship on tax compliance and state capacity. China's massive but little-known explorations in taxation highlight the distinct types of modern state capacity, and raise challenging questions about the future of taxation and the superiority of institutions based on rule of law.

Stochastic Computing Arrangement.

Abstract: 1,184,652. Stochastic computation. STANDARD TELEPHONES & CABLES Ltd. 3 March, 1967 [7 March, 1966], No. 9871/66. Headings G4A, G4D and G4G. [Also in Divisions G1 and G3] General.-A computer assembly comprises one or more digital computing elements, means for representing input information stochastically by the probability that a level in a clocked sequence of logic levels will be ON, means for applying the so represented information to the computing element(s) performing digital computation, and means for converting the stochastically represented outputs of the computation into analogue or digital information valves. Theory.-Analogue variables are presented as probabilities that a specific binary or multilevel event will occur (or generally the probability that a specific configuration representing one of several possible events will occur), and a quantity or event may be scaled as a probability 1 > P > 0, and represented by a sequence of logic levels or states of the inputs and outputs of the computer elements; which representation, e.g. by the adaptive device of Specification 1,099,574, is stochastic since the event or quantity is defined by the statistical properties of a sequence as to the probability that it represents a given event or quantity. In affine symmetric binary representation, analogue quantity -E 0, the states being permanently on or off for maximum or minimum values of V and randomly fluctuating therebetween (or OPEN) for zero. Thus V = [p (ON) - p (OFF)] E 9/ for a sequence in a ternary device wherein p (on) and p (off) are the relative frequencies of on and off conditions and for 0 0 is a scaling factor; Zero being represented by "OFF" and infinity by "ON" and extensible to negative quantities by multiplication by (- 1). In symmetric projective ternary representation, when V#0 and when V 1 = E - V for affine asymmetric binary representation, V 1 = - V for affine symmetric binary and ternary, projective symmetric ternary, hyperbolic ternary, and trigonometric 1 binary V 1 = - for projective binary represen- V tation. Fig. 6 shows a multiplication circuit for afline symmetric binary representation. If + denotes OR switching and juxtaposition indicates AND switching, while a superposed bar indicates a Boolean inverse so that a = 0 if and only if a = 1 a = 1 if and only if a = 0, the levels a, b as shown are applied through inverters to AND gate 1 as #a #b and directly to AND gate 2 as a, b, so that output of OR gate 3 is #a #b + ab which represents the scaled products of the variables represented by the sequences of a and b; the multiplier being an equality gate giving ON output if and only if its inputs are identical. For multiplication of further quantities, such multipliers are cascaded. An affine ternary representation multiplier is identical logically with that of Fig. 6 and (Fig. 1, o, p, not shown). For a multiplier in projective binary representation, a cross coupled flip flop FF (Fig. 3) receiving inputs X, Y is clocked to change over to a value dependent on its prior state and preceding inputs X, Y; the output Z from an OR gate energized from two AND gates receiving X, Y and the flip flop outputs being equal to a new input X if the flip flop output Q is ON, and equal to the complemented new input #Y if the Q input is ON. The device realizes the transformation For multiplication in projective binary representation (Fig. 4) a clocked cross coupled flip flop CCFF receives inputs AB, #AB from AND gates respectively energized from inputs A, B; directly and through inverters in synchronous logic, while in asynchronous logic the clock pulses may be obtained from a local oscillator, or triggered from a change of output if the inputs are mutually exclusive. A further delay flip flop in one input acts as correlation isolator (Fig. 7, not shown). For evaluation of squares and higher powers utilizing plural multipliers, input isolators utilizing clock pulse delay flip flops (Figs. 7, 8, not shown) are inserted to avoid autocorrelation of the inputs, whenever identical signals are applied to multiple paths, in stochastic computation. Autocorrelated sequences may be de-correlated (Fig. 21) by introducing random delays whose maximum delay # autocorrelated depth from noise sources changing over triggers at random intervals to randomize the clock pulses of flip flops FF1, FF2 when the noise exceeds a predetermined level. The random states are transferred to flip flops FF3, FF4. Flip flops FF5, FF6, FF7 connected as a shift register to the direct inverted input hold previous input states at unit, two, and three delay intervals respectively, and flip flops FF3, FF4 gate one of these delayed inputs through three input AND gates and a common OR gate to the output line, so that at each clock pulse a random delayed replication of the input appears on the output. In an adder for symmetric and asymmetric binary affine representation (Fig. 9), a first flip flop FF is triggered from a noise source with grounded inputs, and its output is applied to a second flip flop FF emitting an ON level to AND gate 4 and an OFF level to AND gate 5, or vice versa with equal probability, so that the probability p (Z) of output from OR gate 6 is ¢ (PA + PB) from gates 4, 5. It is shown that the output is 1/k the sum of the inputs for a k input adder, and for 2 inputs a trigger pulse is applied to clock input of a first flip flop when signal from random noise source exceeds a preset threshold, to change its state, since its inputs are in a random condition at the instant of a clock pulse. Random sequences carrying information are generated in a comparator with binary output having a random first input and a fixed or variable second input responsive to input voltage or digital code; the random input containing all levels with equal probability. Fig. 10 shows analogue/stochastic converter generating random sequences comprising a comparator receiving an analogue input and an input from a digital to analogue converter triggered at T by a series of flip flops FF, each in turn triggered on its clock line from a random noise source exceeding a predetermined threshold. The flip flops are in random state so that the D/A converter feeds a random level to the comparator. If at a clock pulse applied to an output flip flop fed from the converter, the analogue input exceeds the random input, the output flip flop is ON and otherwise it is off, so that the output sequence is an affine binary stochastic representation of the analogue input if the D/A conversion is linear. Alternatively (Fig. 11, not shown) for digital input the latter is applied directly to a digital comparator also receiving the random digital output of a series of flip flops

Circuit network including integrated circuit flip-flops for digital data processing systems

Abstract: An integrated circuit flip-flop with master and slave portions. The slave portions being conventional cross coupled NOR gates, the master portion constructed for set over ride reset response to input signals and having two outputs, only one output changes with the other clock pulse phase. Determination as to which output changes is made during the clock pulse phase when both outputs are similar and in dependence upon set and/or reset inputs then received. The state of the slave portion is determined by which one of the master outputs changes with the clock. The integrated circuit flip-flop is operated at a supply voltage lower than the voltage used for biasing discrete circuit logic and flip-flop input and output, with noise rejection diodes connected at the input.

High speed associative memory circuits

Abstract: A high-speed associative memory circuit is disclosed comprising a flip-flop operating as a memory storage circuit, and a pair of switching transistors connected to the "true" and "not" output terminals of the flip-flop. The latter transistor pair thus defines a circuit for detecting the state of the flip-flop transistors.

Apparatus for identifying those means of a plurality of means which have changed state

Abstract: Apparatus for identifying those means of a plurality of means which have changed their binary state. A reference is sequentially obtained to only those means which have changed their state without spending unnecessary work sifting off the remaining means. The arrangement is particularly applicable in telecommunication systems, more especially such systems which have a central control, e.g., program store controlled systems in which the arrangement makes it possible to reduce considerably the idle load of a controlling computer.

Information filter and steering circuit

Abstract: A program arrangement for a telephone system is disclosed in which operator position key action signals are rehoppered for a call whenever the signals are received by the base level processor during short real time breaks of a priorly initiated base level key action program that has not yet completed its work function for the same call. When the program takes a real time break of a significantly longer duration, such as queuing for an available facility, the rehoppered key signals and any newly arrived key signals for the same call are analyzed to determine whether they represent logical or illogical service requests. Illogical requests are disregarded. Logical requests are used to change the state or progress of the call.

Apparatus for converting a cyclic analog signal to a digital signal

Abstract: The specification and drawings disclose 10 photocells arranged to view a full cycle of a space distributed analog signal. Each photocell is coupled to the input of an amplifier whose output rests in one binary state if the input exceeds one level and rests in another binary state if its input falls below another level. Of the large number of combinations in which the binary outputs of the amplifiers can exist, logic circuitry responsive to certain combinations only produces one unique output for each incremental displacement of the periodically varying signal.

A linear algorithm for determining relative orbital state using angle data

Abstract: Linear algorithms for determining spacecraft relative orbital state using angle data with digital computer

Sequential-state binary parallel adder

Abstract: The process of binary addition is examined in the context of the construction of a large parallel digital computer, in which it is desired to perform fixed-point additions as rapidly as possible using current i.c. technology. The block-carry adder is shown to be the fastest method of addition previously available. Two addition algorithms are then presented, both of which involve the sum register in the addition process and allow the addition and cycle times to be significantly reduced. An adder design based on one of these algorithms is partitioned into two standard logic groups suitable for production as l.s.i. units, and reults are presented of an experimental 64-bit adder cycling every 30ns.

An Investigation of the Relationship Between Level of Need for Achievement and Employment Intentions Among College Juniors and Seniors at Louisiana State University.

Abstract: There is little factual information about whether the people attracted to business employment have rela­ tively strong or weak common motives. In an attempt to provide more information on this question, a primary research project was undertaken to test the following hypotheses: Hypothesis One; College juniors and seniorswho intend to become employees of business firms have significantly higher levels of need for achievement than those who intend to enter other types of employment. Hypothesis Two: College juniors and seniors who intend to become business employees have stronger and more favorable attitudes toward certain aspects of busi­ ness employment than those who intend to enter other types of employment. The data used to test the above hypotheses were gathered from 300 students (100 in each of the academic areas of business administration, engineering, and social sciences) at Louisiana State University in the fall semester of 1969. The three part questionnaire included questions designed to reveal employment intentions and selected biographical information, a modified thematic apperception test to measure the relative level of subjects' xxii needs for achievement, and a semantic differential test to gather attitudinal data on the achievement aspects of business employment. Data on attitudes toward the taskrelated, self-related, and other-related aspects of business employment were collected. To test the first hypothesis, all subjects were divided into a high need achiever group and a low need achiever group by dividing the distribution of achievement scores at the median. The employment intentions of both groups were compared for significant differences through the use of a chi-square test of independence. The analysis indicated that there were no significant differ­ ences in the employment intentions of high and low need achievers at the .05 level. The subjects who intended to become business employees did not have significantly higher levels of need for achievement than the subjects who intend to enter other types of employment. Because it was felt that subjects' grade-point average might influence the relationship in question, subjects were divided into a high grade-point group and a low grade-point group, and the employment intentions in the need achiever groups were compared for significant differences. Again chi-square analysis indicated no significant differences. The same result was obtained within each of the academic sub-groups. No substantial evidence was found which supported the first hypothesis. xxiii The test of the second hypothesis was conducted by comparing the attitudes of the subjects who intended to enter business employment with the subjects who in­ tended to enter other types of employment. The compari­ sons were in terms of a "t" test of significant differences in means. The results indicated that the subjects who intended to enter business employment did have more favorable and stronger attitudes than the subjects who intended to enter other types of employment. These significant differences continued when subjects were classified by level of need for achievement, grade-point average, and a combination of level of need for achieve­ ment and grade-point average. The analysis indicated that neither grade-point average nor level of need for achieve­ ment had a substantial influence on the attitudes in question. In almost all cases there were differences in attitudes in the predicted direction which were significant at the .05 level. This hypothesis was supported. However," neither level of need for achievement nor grade-point average seemed to exert a substantial influence on attitudes. In summary, the analyses indicated that there were probably other variables which exerted more influence on both attitudes toward business employment and business employment intentions than the level of need for achieve­ ment, grade-point average or a combination of the two variables. xxiv

Medical Education and the State

Abstract: SIR,-A recent report compares the serological characteristics of the viruses obtained from human genital warts and common skin warts using immune electron-microscopy and complement fixation techniques.' The authors suggest the existence of a one-way antigenic cross between the two viruses on the basis of their finding that sera from patients with skin warts reacted with the viruses from both skin and genital warts, whereas sera from those with genital warts reacted with genital wart virus only. This interesting problem regarding the antigenic identity of the virus in genital warts has also been studied in this department since it was demonstrated that genital warts contained virus particles morphologically identical to those in skin warts but present in very small numbers.2 As insufficient amounts of genital wart virus were available here for use in standard precipitation and complement fixation tests, other methods for identifying the virus had to be pursued. A rabbit inoculated with a suspension of genital wart material was found after the third inoculation to have developed precipitating antibody to virus from skin warts-in fact simple plantar warts. The precipitin line formed by this rabbit's serum gave a reaction of identity with precipitin lines formed against the same virus by serum from a patient with a simple plantar wart and serum from another rabbit immunized with virus from simple plantar warts. These lines are illustrated in the accompanying drawing made from the photographic record of this test (see Fig.).

A strategy for detecting faults in sequential machines not possessing distinguishing sequences

Abstract: The problem treated here is that of detecting faults in digital equipment by applying input sequences at the input terminals and observing output sequences at the output terminals. The checking of digital equipment by input/output tests applied at the terminals is motivated by current and future usage of large-scale integration techniques which make internal test points generally inaccessible for testing purposes. The modeling of digital equipment by finite-state sequential machines and then designing fault-detection tests based on the state table is a general approach. The difficulty is that it results in very long experiments for large state tables, particularly for the case in which the state table does not possess a distinguishing sequence. that is, an input sequence for which the response uniquely identifies the initial state. This paper presents a strategy for designing more efficient fault-detection tests for machines not possessing distinguishing sequences.

Improvements in or relating to logic circuits

Abstract: 1,217,502. Bi-stable circuits. PLESSEY CO. Ltd. 17 Jan., 1968 [18 Jan., 1967], No. 2577/67. Heading H3T. [Also in Division G4] A logic circuit comprises two tiers and two ranks and is driven by out-of-phase clock pulses to two inputs to adopt four stable conditions sequentially. True and inverse clock pulses CP, CP are applied to VT21, VT22 to control transistor circuits VT5, VT6 and VT15, VT16 which constitute the lower tier, and VT1-VT4, VT7, VT8, VT11-VT14, VT17, VT18 constituting the upper tier. The lefthand of two like bi-stable circuits comprises crosscoupled pair VT1, VT2 with level-shifting coupling transistors VT3, VT4. Switching is dependent on a long-tailed pair VT5, VT6 and gating transistors VT7, VT8 controlled by the state of the right-hand bi-stable element via leads D 2 1 , #D 2 1. If the potentials on leads D 1 , D 1 , D 2 , D 2 initially correspond to logic states 0101 then four successive pulses CP, CP, CP, CP change the states to 1001, 1010, 0110, 0101. Outputs can be taken from either bi-stable element to a similar circuit forming the next stage of a binary counter.

Control System Design And Analysis Package

Abstract: A control system design and analysis package, developed recently by the authors, is described. The entire package fits on a 3.5-inch high density floppy disk, and runs on any IBM compatible personal computer equipped with a numeric co-processor. The package allows the analysis and design of singleinput single-output systems using transfer functions or state equations. It is suitable for use by students in an undergraduate engineering program as well as for practising engineers, and runs well under DOS, Windows, and OS/2 Warp. It is very user-friendly and provides information and on-line help in each of the programs.

High-speed sense latch circuit

Abstract: A sense latch circuit having a short access time. The latch output switches state rapidly due to the incorporation of a minimum number of logic stages between the sense inputs and the output drive stage, thereby introducing a minimum number of delays. Nonsaturable logic circuits are utilized to allow fast switching. At the inputs of the sense latch circuit, the high DC levels of the sense signals are reduced in magnitude for application to an ECL circuit switch with the use of diodes and resistor dividers. This arrangement allows for large temperature variations without saturating any of the logic stages.