Showing papers on "Static induction transistor published in 1972"

Fundamental limitations in microelectronics—I. MOS technology

Abstract: The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2.

GaAsGaAlAs heterojunction transistor for high frequency operation

Abstract: A bipolar transistor structure is proposed having application for either high frequency operation or integration with certain types of light emitting devices. The structure involves liquid phase epitaxially grown layers of GaAs for the collector and base regions, and of Ga1−xAlxAs for the heterojunction emitter. The high frequency potential of this device results primarily from the high electron mobility in GaAs and the ability to heavily dope the base region with slowly diffusing acceptors. The Ga1−xAlxAs emitter region provides a favorable injection efficiency and, because it is etched preferentially relative to GaAs, access to the base layer for making contact. Transistor action with d.c. common emitter current gains of 25 have been thus for observed. Calculations of the high speed capability of this transistor are presented.

A semi-insulated gate gallium-arsenide field-effect transistor

Abstract: Proton bombardment has been used to make a semi-insulated gate gallium-arsenide field-effect transistor. This technique combines the simplicity of the metal semiconductor FET technique, the advantage of operating the device using positive as well as negative bias on the gate, and the possible use of higher conductivity material for the channel, which may result in a higher transconductance and a higher saturated current density.

Regulated short circuit protected power supply

Abstract: A voltage regulated power supply utilizing a small series resistance to sense load current and a circuit including a normally "off" trigger transistor having its base connected to the load side of the series resistor for actuation to "on" condition responsive to voltage drop in the resistor and a series switching transistor having its base connected to the output of the trigger transistor to shut off the series switching transistor in an overload condition which in turn interrupts operation of a series transistor by interrupting base current thereto. The circuit also includes a latching zener diode connected to the base of the trigger transistor to maintain its "on" condition after overload to maintain the power supply inoperative until the fault is removed and the supply is recycled.

Double-clamped schottky transistor logic gate circuit

Abstract: A double-clamped Schottky transistor logic gate circuit which includes a totem pole output with Schottky clamp transistors with the pull-down transistor supplying a stable low output level and the pull-up transistor provides a high stable output level voltage by use of a negative feedback arrangement which includes level shifting Schottky diodes and a second Schottky clamp transistor to control the current to the pull-up transistor. An output gating arrangement utilizing Schottky diodes provides reduced capacitances and chip area by placing the cathode of the diode in the same isolated integrated semiconductor regions as the collector of the pull-down transistor. In addition, temperature compensation is provided and noise immunity is improved by integrating a voltage regulator into the same integrated circuit.

Foldback current control circuit

Abstract: In a foldback current control circuit, a sensing resistor is connected in series between a source and an output transistor. The sensing resistor biases the emitter of a first transistor of a matched pair included in a comparison circuit. The emitter of the second transistor of the pair is biased by a reference resistor which provides a reference voltage in response to load voltage. When a fault in the load circuit of the output transistor occurs, the reference voltage exceeds a threshold, and the potential at the collector of the second transistor exceeds that of the first in order to turn on a third transistor. The third transistor shunts base drive from the output transistor to prevent damage to the output transistor and load. Selfcompensation of the circuit for temperature is achieved through use of the matched transistors in the comparison circuit and by maintaining nearly equal collector currents in the matched pair during an overload condition.

Power supply including inverter having multiple-winding transformer and control transistor for controlling main switching transistors and providing overcurrent protection

Abstract: A power supply includes a high frequency inverter comprising a pair of main switching transistors for alternately conducting current from a d.c. source through different winding halves of a multi-winding transformer. A starting resistor, connected between the source and the base of a selected one of the main transistors, initiates base-emitter current flow to make the transistor conductive. A control transistor turns the then conducting main transistor ''''off'''' in response to a predetermined current level through the conducting main transistor; the predetermined current level having been reached in response to the onset of magnetic saturation of the core of the transformer. Subsequently, a voltage induced in a third transformer winding initiates base-emitter current flow in the other main transistor thereby turning it ''''on''''. Also, the control transistor serves to turn either main switching transistor ''''off'''' when the current therethrough is excessive, (e.g., overload or short-circuit condition).

Circuit for minimizing the signal currents drawn by the input stage of an amplifier

Abstract: A CIRCUIT FOR REDUCING THE SIGNAL CURRENT FLOWING INTO THE BASE OF A BIPOLAR INPUT TRANSISTOR AND WHICH DISSIPATES RELATIVELY LITTLE POWER. THE COLLECTOR CURRENT OF THE INPUT TRANSISTOR IS PASSED THROUGH THE COLLECTOR-TOEMITTER PATH OF A SECOND TRANSISTOR. A CURRENT MIRROR, COMPRISING A THIRD TRANSISTOR CONNECTED AT ITS COLLECTOR TO THE BASE OF THE SECOND TRANSISTOR AND A FOURTH TRANSISTOR CONNECTED AT ITS COLLECTOR TO THE INPUT TRANSISTOR, CONDUCTS THE BASE CURRENT OF THE SECOND TRANSISTOR AND IN RESPONSE THERETO CAUSES AN APPROXIMATELY EQUAL CURRENT TO FLOW TO THE BASE OF THE INPUT TRANSISTOR.

Multiemitter coupled logic gate

Abstract: The emitters and bases of two transistors, at least one of which has more than one emitter, are used as inputs, while the collectors and emitters are used as outputs. The collector of the first transistor is connected to the base of the second transistor. The collectors of both transistors are electrically biased. A resistor is connected between the bias source and the collector of the first transistor. A third transistor, connected as a diode, clamps the voltage across the resistor to a selected value even if more than one input to the first transistor is low. With changes in inputs and outputs, the circuit can function as a basic AND-OR gate, a trigger circuit for pulse shaping, an R-S latch, and a gated latch. By combination of basic gates, more complex logic functions can be achieved.

Current translating circuits

Abstract: An amplifier suitable for integrated circuit construction including an active device current repeater load arrangement having relatively high output impedance, good frequency response, temperature stability and signal handling capabilities. The current repeater load arrangement includes a diode connected transistor and a further transistor having proportionally related conduction characteristics. A current amplifier comprising cascaded transistors is connected between the collector of the further transistor and the bases of the further transistor and the diode connected transistor. An additional, unidirectionally conducting device, poled to conduct as the first one of the cascaded transistors ceases conduction, is coupled from the collector of the further transistor to the input of one of the cascaded transistors following the first.

Apparatus for non-destructively testing a forwardly biased transistor for second breakdown

Abstract: To non-destructively test a transistor for second breakdown a high power signal is applied across the collector and emitter of a forwardly biased transistor. The apparatus is responsive to a voltage transient which appears should second breakdown occur to cut off the test signal prior to the actual destruction of the transistor under test by the second breakdown.

A novel saturation control in TTL circuits

Abstract: A novel technique of saturation control in TTL and other saturated logic circuits is described and analyzed. The approach is not only fully compatible with standard bipolar transistor technology, but lends itself to integration. The device parameter tracking on a chip is utilized to suitably bias a feedback saturation control transistor so that the stored charge of a TTL gate output transistor is reduced by typically two orders of magnitude. Thus, the turn-off switching time is significantly decreased without noticeably affecting the turn-on delay time. The performance improvement is close to that achieved by the well-known Schottky diode clamp approach; however, the novel technique offers advantages in noise margin, control of down-level output voltage, and processing. The effectiveness of the proposed technique has been verified theoretically by computer circuit analysis and experimentally by bench setup measurements.

Nonvolatile random access memory cell using an alterable threshold field effect write transistor

Abstract: The present invention relates to a nonvolatile random access memory cell having a fixed threshold field effect read transistor, a fixed threshold field effect storage transistor and an alterable threshold field effect write transistor in it. The source electrode of the read transistor is connected to the drain electrode of the storage transistor to sense when the latter transistor is holding a volatile charge on its gate electrode, and the gate electrode of the read transistor and the gate electrode of the write transistor are connected together to consolidate read and write select lines. The drain electrodes of the read transistor and the write transistor are connected together to consolidate read and write lines. The source electrode of the write transistor and the gate electrode of the read transistor are connected together to allow for storage of information on the gate electrode of the latter transistor through the former transistor and to allow for nonvolatile storage into the former transistor of the volatile information in the latter transistor by channel shielding as power is lost to the cell. Storage means is connected to the gate electrode of the write transistor to non-volatilely store the volatile information which is held as a charge or no charge on the gate electrode of the storage transistor, as power is removed from the nonvolatile random access memory cell.

Encoder circuit to reduce pin count for data entry into insulated gate field effect transistor integrated circuits

Abstract: An insulated gate field effect transistor compatible encoder circuit employs a field effect transistor and a lateral bipolar transistor to reduce the number of transmission lines or pins necessary to transmit information to an insulated gate field effect transistor integrated circuit employing such encoder circuit as its input The input to the encoder circuit is coupled to both the gate of a field effect transistor and the emitter of a bipolar transistor When a negative voltage is transmitted to the input, the field effect transistor turns on; when a positive voltage is transmitted to the input, the bipolar transistor is turned on; and when no voltage is transmitted to the input, neither transistor is turned on The outputs of the transistors are then gated to provide three distinct logic inputs, from the single input, for the insulated gate field effect transistor integrated circuit

Ultra-stable oscillator with complementary transistors

Abstract: A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bipolar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form as the first bi-polar transistor circuit, with the piezoelectric crystal being common to both circuits. By this configuration, variations in the input impedance of the first bi-polar transistor, resulting from changes in the transitional frequency due to small changes in quiescent current, are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Microwave power transistor

Abstract: A microwave power transistor system using diamond-shaped emitter and base regions to maximize the ratio of emitter periphery to base area and thereby maximize the gain of the device within manufacturing constraints. A plurality of transistor cells are arranged in a symmetrical array to facilitate both heat flow and ease of interconnection. A transistor phased array radar system has improved phase shift stability and does not require feedback correction.

Memory circuit using variable threshold level field-effect device

Abstract: A memory circuit using a variable threshold level field-effect device, such as a metal-silicon nitride-silicon dioxide-semiconductor field-effect transistor (MNOS FET) or a metal-aluminum oxide-silicon dioxide-semiconductor (MAOS) FET, as the memory transistor connected in series with at least one metal-insulator-silicon (MIS) FET. An addressing signal is supplied to the MIS FET to address the particular memory transistor connected thereto. In this condition, a signal for reading or writing information by changing the characteristics of the memory transistor can be applied to the gate of the latter transistor.

Drive circuit for conducting devices

Abstract: A drive circuit for effecting current flow in an inductive circuit comprising a coil the circuit including a power transistor having its emitter collector circuit connected in series with the coil, an input transistor for controlling the power transistor and a resistor for providing a signal representative of the current flowing in the coil. A feed back transistor is supplied with the signal developed across the resistor and provides feed back to the input transistor whereby the mean value of current flowing in the coil will depend upon the magnitude of the input signal applied to the input transistor.

High-voltage integrated driver circuit and memory embodying same

Abstract: A high-voltage integrated driver circuit for driving the word lines of a digital computer memory array of floating-gate avalanche-injection transistor memory cells, and for other applications where a high driving voltage is required. The disclosed driver circuit comprises a field-effect output transistor having a source electrode connected to a respective word line, a drain electrode adapted to have a chip select pulse signal applied thereto, and a gate electrode connected to selectably operable circuitry which may be conditioned either to a first state for clamping the voltage of the gate to cut off the output transistor and thereby maintain the output and the word line at a first voltage level, or to a second state for unclamping the voltage of the gate of the output transistor to permit the voltage of the output and the respective word line to swing with a high amplitude so as to cause the selected memory cell transistor to go into avalanche breakdown and thereby charge its floating gate so as to store a bit of information in the selected cell.

A low impedance field effect transistor

Abstract: A junction field effect transistor having non-saturation characteristics like a vacuum tride has been successfully developed. Its output impedance can be decreased to 8 ohms so that it will serve in audio applications or as an impedance transformer. The geometrical structure of this FET is analogous to that of a triode tube and is based on the idea of controlling the resistance between drain and source by a potential applied to a grid-like gate structure. Design considerations that avoid saturation of the drain current will be discussed.

Miniature, low voltage, low current receiver front end

Abstract: A receiver RF section or front end is provided with a mixer stage and an RF amplifier stage connected in series with one another for direct current energization from a power source. The mixer stage includes a transistor, the base and emitter electrodes of which constitute the inputs of the mixer stage, and a control transistor has its base-emitter junction connected in parallel with the base-emitter junction of the transistor in the mixer stage. The DC voltage drop across the base-emitter junctions of these transistors is used to control the output of an oscillator transistor. The oscillator transistor has an output electrode thereof direct current coupled to the base electrode of the mixer transistor and the base electrode of the oscillator transistor is direct current coupled to an output electrode of the control transistor.

Emitter coupled sync separator

Abstract: An emitter coupled sync separator for a television receiver comprising a pair of transistors connected together with the first transistor receiving the composite video signal and gated to the on condition at a level which is approximately 50% of the height of the sync pulse and remains on until it is turned off at a time t2 when the signal drops down to the same level again. The second transistor is coupled to the first transistor such that it is turned off when the first transistor is turned on. The input signal is coupled to the base of the first transistor through a parallel resistor and capacitor which determines the level at which the first transistor turns on and off. The circuit provides extremely fast response and is inherently immune to noise due to the very small window of the horizontal pulse. The circuit is capable of use over a wide range of amplitude of the composite video.

Gain controlled high-frequency input stage having a pin-diode network

Abstract: To decrease cross modulation in strong signal areas in TV tuners, a PIN-diode network is connected to the automatic gain control voltage and to a source, the PIN-diode network being connected with the d-c circuit of a pre-amplifier transistor in such a manner that the reference voltage for the PIN-diode network is stabilized by the transistor itself, derived from the emitter of the high-frequency, high-current transistor.

Radiation triggered disconnect means

Abstract: In conjunction with a circuit, such as an IC circuit or the like, which is sensitive to radiation, a high speed switching transistor normally biased in a saturation mode of operation connected between the circuit and a suitable power source with a semiconductor diode sensitive to the radiation connected to the transistor for providing a reverse bias to the transistor when radiation impinges upon the diode to cut off conduction of the transistor and prevent damaging currents to the circuit.

High frequency transistor fabrication

Abstract: IN THE FABRICATION OF HIGH FREQUENCY NPN TRANSISTORS IN INTEGERATED CIRCUITS, A DOPED OXIDE LAYER IS FORMED ON THE SURFACE OF THE WATER AFTER DIFFUSION OF THE BASE REGION AND PRIOR TO OPENING THE EMITTER DIFFUSION WINDOW. THEREAFTER, REMOVAL OF OXIDE REGROWN IN THE EMITTER DIFFUSION WINDOW TO FORM AN EMITTER CONTACT WINDOW, AND SIMULTANEOUS REMOVAL OF OTHER SURFACE OXIDE CONCURRENTLY GROWTH THEREWITH, LEAVES INTACT THE DOPED OXIDE LAYER TO PREVENT SURFACE INVERSION.

Adaptive transistor switch

Abstract: A transistor switch connecting a load to a suitable source of power with amplifying means supplying base current to the transistor switch with a voltage sensitive device, such as a diode or a transistor, connected to sense the voltage across the transistor switch and provide an alternate path for driving current to the amplifier to maintain base current into the transistor switch at a predetermined ratio relative to current flowing through the transistor switch and the load.

Rf transistor carrier

Abstract: An RF bipolar transistor and carrier which reduces inductance of the common lead of the transistor thereby increasing operational bandwidth and transistor gain especially in VHF-UHF applications. The carrier includes bonding pads for receiving the transistor and a low ohmage resistor and whereby wire bonds connected to the emitter and base regions of the transistor may be interlaced.

Electronic switch for timepieces

Abstract: An electronic switch to provide a long storage life for the battery used in timepieces such as quartz watches is disclosed. The switch includes a transistor connected between the oscillator divider and power supply and a delay circuit coupled across the output from the oscillator-divider and controlling the aforesaid transistor. When the balance wheel is held off normal, the delay circuit opens the series switch transistor after a predetermined time interval to minimize battery drain. In a second embodiment, a shunt mode of operation is provided wherein the output driver transistor is controlled by a second transistor from the delay circuit. A third transistor in the oscillator input is similarly controlled by the delay circuit. When the balance wheel is held off normal, the delay circuit turns on the second and third transistors thereby minimizing battery drain.

Transistor amplifier stage with device in its temperature compensated bias network used as preliminary amplifier

Abstract: A collector-loaded grounded-emitter transistor amplifier output stage employs a temperature-compensated bias network with an auxiliary transistor having its base electrode supplied quiescent current exclusively through a resistive element connecting the base and collector electrodes. A source of input signal is coupled to the base electrode of the auxiliary transistor by capacitative means and decoupled by resistive means from the collector electrode thereof. The temperature stabilizing auxiliary transistor accordingly provides a preliminary amplification of input signals for application to the base electrode of the output stage amplifier transistor, without use of additional active devices.

Technique for deriving a regulated d-c source for low-level logic circuits from high d-c voltage source

Abstract: A Zener diode, a voltage dropping resistor, and a first transistor are connected in series across a primary d-c source. The emitter-collector junction is in the series path of the diode and resistor. A second transistor has one side of its emitter-collector junction connected to the junction of the Zener diode and resistor, and the other side connected both to the base of the first transistor and to one side of the load. The other side of the load is connected to one side of said source. A control signal applied to the base of the second transistor turns the transistor on or off. When the second transistor is turned off, the first transistor is turned on and the voltage dropping resistor is in the circuit. When the second transistor is on, the first transistor is turned off and the load replaces the voltage dropping resistor in the regulation circuit.