Showing papers on "Stuck-at fault published in 2021"

Data-Driven Model-Free Adaptive Fault-Tolerant Control for a Class of Discrete-Time Systems

Abstract: The fault-tolerant control problem is studied for a class of discrete-time systems subjected to sensor fault. The data-based fault detection method is constructed to detect sensor fault, which avoids obtaining residual signal by designing fault detection observer. When the fault is detected, a discrete-time observer is built for estimating sensor fault. The fault estimation is employed to realize controller reconstruction. For the purpose of obtaining better control performance, a model-free adaptive fault-tolerant controller is developed by employing more past control information. Accordingly, the flexibility and adaptability of the fault-tolerant controller are improved by introducing more adjustable parameters. Finally, the developed method is validated to be effective by a simulation example.

Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators

Abstract: Resistive RAMs can implement extremely efficient matrix vector multiplication, drawing much attention for deep learning accelerator research. However, high fault rate is one of the fundamental challenges of ReRAM crossbar array-based deep learning accelerators. In this paper we propose a dataset-free, cost-free method to mitigate the impact of stuck-at faults in ReRAM crossbar arrays for deep learning applications. Our technique exploits the statistical properties of deep learning applications, hence complementary to previous hardware or algorithmic methods. Our experimental results using MNIST and CIFAR-10 datasets in binary networks demonstrate that our technique is very effective, both alone and together with previous methods, up to 20 % fault rate, which is higher than the previous remapping methods. We also evaluate our method in the presence of other non-idealities such as variability and IR drop.

Fast fault identification in bipolar HVDC grids: a fault parameter estimation approach

Abstract: The protection of meshed HVDC grids requires the fast identification of faults affecting the transmission lines Communication-based methods are thus not suited due to the transmission delays Many approaches involving a model of the transient behavior of the faulty line have recently been proposed Nevertheless, an accurate description of the traveling wave phenomenon in multi-conductor lines such as overhead lines requires complex computations ill-suited for fast fault identification This paper presents a single-ended fault identification algorithm using a closed-form parametric model of the fault transient behavior The model combines physical and behavioral parts and depends explicitly on the parameters that characterize the fault, namely the fault distance and impedance When a fault is suspected, the fault parameters are estimated so that the model fits best the received measurements The confidence region of the estimated fault parameters is used to decide whether the protected line is actually faulty or not The proposed algorithm is tested on a 4 station grid simulated with EMTP-RV software The method is able to identify the faulty line using a measurement window of less than 05 ms This allows ultra-fast fault clearing and can hence improve the overall reliability of future HVDC grids

Assessment and improvement of the pattern recognition performance of memdiode-based cross-point arrays with randomly distributed stuck-at-faults

Abstract: In this work, the effect of randomly distributed stuck-at faults (SAFs) in memristive cross-point array (CPA)-based single and multi-layer perceptrons (SLPs and MLPs, respectively) intended for pattern recognition tasks is investigated by means of realistic SPICE simulations. The quasi-static memdiode model (QMM) is considered here for the modelling of the synaptic weights implemented with memristors. Following the standard memristive approach, the QMM comprises two coupled equations, one for the electron transport based on the double-diode equation with a single series resistance and a second equation for the internal memory state of the device based on the so-called logistic hysteron. By modifying the state parameter in the current-voltage characteristic, SAFs of different severeness are simulated and the final outcome is analysed. Supervised ex-situ training and two well-known image datasets involving hand-written digits and human faces are employed to assess the inference accuracy of the SLP as a function of the faulty device ratio. The roles played by the memristor’s electrical parameters, line resistance, mapping strategy, image pixelation, and fault type (stuck-at-ON or stuck-at-OFF) on the CPA performance are statistically analysed following a Monte-Carlo approach. Three different re-mapping schemes to help mitigate the effect of the SAFs in the SLP inference phase are thoroughly investigated.

Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits

Abstract: An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An ( $$n+1$$ ) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to $$25.0\%$$ in gate cost and $$35.8\%$$ in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.

Advancement in Onchip Clocking to Improve ATPG Coverage Between Clock Domains

Abstract: Using multi-clock domain is much needed nowadays to lighten the complexity of System On Chip (SoC). To deliver high quality for a design testing is very much necessary to achieve higher test coverage for stuck at fault model as well as transition delay fault model. Things are not tough when we have to deal with flops driven with same clock domain. However, achieving good test coverage for TDF fault model when flops are driven by two different clock domain is a challenge. This paper proposes usage of synchronous On Chip Clock controller (OCC) to cover faults between two different synchronous clock domains and ensure high quality pattern generation for Transition Delay Fault (TDF). A sync OCC techniques that helps to improve ATPG coverage for by ~3% and pattern count reduction due to same in critical transition mode testing.

Stuck-at Fault Diagnosis of Four-bit Carry Look-ahead Adder by Shannon Expansion via Semi-tensor Product

Abstract: In this paper, a stuck-at fault diagnosis algorithm is proposed for the four-bit carry look-ahead adder based on Shannon expansion and semi-tensor product. First, the algebraic representation of Shannon expansion is introduced via the semi-tensor product. Second, a sum-of-product four-bit carry look-ahead adder is given by a Python library for electronic design automation through fixing the order of input signals. Third, by the definition of stuck-at faults, the problem of stuck-at fault diagnosis is transformed into solving the system of linear equations based on the algebraic representation of Shannon expansion. Finally, the fault diagnosis of four-bit carry look-ahead adder is carried out for a special stuck-at fault case to validate the proposed algorithm.

Test Coverage Analysis of DFT with EDT and without EDT Architecture

Abstract: ATPG is one of the well-defined technique for generating test patterns for testing the chips. Today's world of SOC design environment, designs are complex so that the number of test patterns required for testing the chips increases. EDT (Embedded deterministic testing) is employed in order to reduce the test volume and reduced ATE memory usage due to large number of test patterns. This paper aims to determine, how well the EDT architecture performs in a DFT environment in terms of coverage for atspeed and stuck at fault model.

Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping

Abstract: There is an increasing demand for running neural network inference on edge devices. Memristor crossbar array (MCA) based accelerators can be used to accelerate neural networks on edge devices. However, reliability issues in memristors, such as stuck-at faults (SAF) and variations, lead to weight deviation of neural networks and therefore have severe influence on inference accuracy. In this work, we focus on reliability issues for edge devices. We formulate the reliability problem as a 0-1 programming problem, based on the analysis of sum weight variation (SWV). In order to solve the problem, we simplify the problem with an approximation - different columns have the same weights - based on our observation of the weight distribution. Then we propose an effective mapping method to solve the simplified problem. The experimental results show that our proposed method can recover 95% accuracy considering SAF defects and can increase by up to 60% accuracy in variation σ=0.4.