Showing papers on "Topology (electrical circuits) published in 1980"

A fundamental result concerning the topology of transistor circuits with multiple equilibria

Abstract: It is shown that a necessary and sufficient condition for a transistor network to possess more than one solution to its dc equations, for some choice of network parameter values, is that a certain simple set of connections, involving some pair of transistors, is present in the circuit's topological structure The presence of this set of connections, prescribing the presence of a certain special two-transistor substructure, referred to as a feedback structure, is thus a necessary condition that any transistor network must satisfy in order to possess the property of bistability The proof of this result is based upon a consideration of two topological properties of transistor networks possessing unique solutions to their dc equations In addition, it is shown how the amount of computation required to verify a certain well-known set of necessary and sufficient conditions which guarantees the uniqueness of solutions to the dc equations of transistor networks can be reduced by determining the location of all feedback structures

Macro assembler process for automated circuit design

Abstract: A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.

On the spatial capacity of packet radio networks

Abstract: Pacing Control, Mischa Schwartz (on leave from Columbia University). In this paper a model and analysis is provided of the IBM SN.' virtual route pacing control umd to control congestion in SNA networks. The model is appropriate to single virtual routes only. The analysts uses a Norton equivalent of the virtual route queueing model. Similar analyses of two other end-to-end window control mechanisms are carried out; one a .~liding window with each message individually acknowledged, the other a fixed window control with the final message in the window only producing an acknowledgement, enabling comparisons to be made between all three. The SNA pacing control procedure, in which the first message in a given window induces an acknowledg,~'ment, is found to perform within 4% of the sliding window mechanism. Simulation results validate the analysis and performance curves obtained. The third wh~dow scheme, with the final message in the window generating an acknowledgement, is found to result in considerable reduction in throughput, as expected. [IBM Research Report RC 8490, September 1980; IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598).

On the topology of FET circuits and the uniqueness of their dc operating points

Abstract: We show here how to prove several results which make it possible to deduce whether or not many common FET circuits can possess more than one, or only one, dc operating point, as a consequence of their topological structure alone. These results extend to FET circuits some similar results which have recently been proved for circuits containing bipolar transistors.

A Hierarchical Approach for Layout Versus Circuit Consistency Check

Abstract: This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.

Strays-insensitive active switched-capacitor biquad

Abstract: A general active switched-capacitor biquad is introduced. The circuit is immune to the various parasitic capacitances and is based on the two-integrator-loop topology. It implements the noninverting forward-Euler and the inverting backward-Euler discrete integrators. The circuit is the most general of its kind and all published biquads and many others can be generated from it.

Computer-Aided Analysis and Design of Networks Containing Commensurate and Noncommensurate Delay Lines

Abstract: Several computer programs are described for the analysis and synthesis of networks containing transmision lines, lumped resistors, voltage sources and current sources. There are no restrictions on the topology of the networks and degenerate elements can also be included. In the noncommensurate case the transmission lines could have different delays and thus the degree of freedom for each network is doubled. State-space techniques are used to formulate the solution to the problem and the high degree of generality was achieved by using topological methods to derive the state equations. Several examples are given.

Correction to "A fundamental result concerning the topology of transistor circuits with multiple equilibria"

Abstract: It is shown that a necessary and sufficient condition for a transistor network to possess more than one solution to its dc equations, for some choice of network parameter values, is that a certain simple set of connections, involving some pair of transistors, is present in the circuit's topological structure. The presence of this set of connections, prescribing the presence of a certain special two-transistor substructure, referred to as a feedback structure, is thus a necessary condition that any transistor network must satisfy in order to possess the property of bistability. The proof of this result is based upon a consideration of two topological properties of transistor networks possessing unique solutions to their dc equations. In addition, it is shown how the amount of computation required to verify a certain well-known set of necessary and sufficient conditions which guarantees the uniqueness of solutions to the dc equations of transistor networks can be reduced by determining the location of all feedback structures.

Sensitivity minimization of networks with operational amplifiers and parasitics

Abstract: A computational method is described which calculates network sensitivity to the influence of parasitics by simulating only the ideal network. For active networks, a similar sensitivity is defined with respect to the deviations from ideal behavior of operational amplifiers. It is shown that this sensitivity is equivalent to the gain-sensitivity product and depends only on the passive elements and the topology. The procedure was applied to known active networks and, in every case considered, minimization resulted in networks with smaller sensitivities. Compensation for nonideal behavior of the operational amplifiers is outlined. A Monte Carlo simulation is performed on the well-known STAR network and it is shown that optimization can lead to considerable improvement, even in the case of well-designed networks.

Comparison of dynamic range properties of high-order active bandpass filters

Abstract: The design procedures necessary for maximising dynamic range of cascade, f.l.f., i.f.l.f. and m.l.f. active-filter topologies, are presented and equations are derived for computing the total output-noise voltage contributed by internal-noise sources. Further, it is shown that the equivalent input noise of a second-order biquad section is dependent not only on circuit configuration and pole-Q, but in some cases also on the section gain. As a result, the total output noise of high-order filters may or may not be a function of the overall filter gain, depending on whether the equivalent input noise of the second-order section used as building block is not or is, respectively, a function of section gain. A comparison of the different topologies indicates that in addition to the advantage of being easy to design, the f.l.f. filter is the only topology whose output noise can remain constant regardless of the overall filter gain and the type of second-order used.

Design of minimum sensitivity multiple loop feedback bandpass active filters

Abstract: A method is described for determining multiple loop feedback topologies which yield minimum sensitivities for symmetrical, all-pole bandpass filters. The procedure begins with a follow-the-leader feedback (FLF) topology and additional feedback loops are constructed until minimum sensitivity is achieved. Filters comprised of identical second-order sections and non-identical sections, respectively, are considered.

Modelling a dual converter/dc motor drive

Abstract: This paper describes a matrix method to simulate a variable speed DC drive with fully-controlled three-phase thyristor bridges in a dual-converter system. The basic approach affords a simple and elegant procedure by which the dynamic equations of the system are automatically assembled to deal with the periodically varying topology of the bridge converter and also the source impedances on the AC side. A digital computer program, capable of predetermining the steady-state as well as dynamic performance of the drive system under certain practically important conditions is developed and the results of simulations of typical drive system are presented.

Ka-band, multibeam, contiguous coverage satellite antenna for the USA

Abstract: The behavior of a multibeam antenna is determined by three major characteristics: beam topology, realizable radiation characteristics, and realizable beamforming network architecture. Eight canonical topology plans have been developed and analyzed: angular separation between identical frequency cells, angular separation between orthogonally polarized identical frequency cells, number and configuration of cells forming coverage areas, and crossover level between nonidentical frequency band cells. A general topology plan is developed for the continental United States for 100-deg W synchronous satellite longitude.

Computer‐aided design of the norton transformation on reactance bandpass ladder filters

Abstract: The CAD method for Norton transformation is presented. Norton transformation has been considered as an important process in the reactance bandpass filter design. It is an equivalence transformation process for easy realization of the element of practical filter. The previous method requires certain designer experience and determines the optional element values by iteration and human interaction. This paper presents a method in which the research method is done by random number and no designer experience is ever required. This method conducts Norton transformation automatically. It has made it possible to automate the complete engineering design of the filter. First, the Norton transformation is outlined, the method giving the circuit topology convenient for program is discussed, and based on the method for topology the algorithm is presented. Finally, how to choose several parameters will be investigated for the search method for several examples. Also given is the design example presented in the computer output.

Sparsity considerations in power system equivalents

Abstract: It is shown that for practical power system applications the amount of network reduction to be performed is a function of both the topology of the network and the impedance of the equivalent branches. It is also shown that it is not sufficient to consider only the topological characteristics of the network to be equivalized in deciding about the nodes that should be eliminated.