Showing papers on "VHDL published in 2010"

A mathematical approach towards hardware design

Abstract: Today the hardware for embedded systems is often specified in VHDL However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications There is a need of higher level abstraction mechanisms In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core The main line in this approach is to start with a straightforward (often mathematical) specification of the problem The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward Besides, the Haskell code is executable, so one immediately has a simulation of the intended system Next, the resulting Haskell specification is given to a compiler, called CeaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis In this work we primarily focus on streaming applications: ie applications that can be modeled as data-flow graphs At the moment the CeaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used In these examples it will be shown that the specification code is clear and concise Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, eg, automatic parallelization of nested for-loops in C-programs

Designing Modular Hardware Accelerators in C with ROCCC 2.0

Abstract: While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers. These platforms are typically programmed in a low level hardware description language, a skill not common among application developers and a process that is often tedious and error-prone. Programming FPGAs from high level languages would provide easier integration with software systems as well as open up hardware accelerators to a wider spectrum of application developers. In this paper, we present a major revision to the Riverside Optimizing Compiler for Configurable Circuits (ROCCC) designed to create hardware accelerators from C programs. Novel additions to ROCCC include (1) intuitive modular bottom-up design of circuits from C, and (2) separation of code generation from specific FPGA platforms. The additions we make do not introduce any new syntax to the C code and maintain the high level optimizations from the ROCCC system that generate efficient code. The modular code we support functions identically as software or hardware. Additionally, we enable user control of hardware optimizations such as systolic array generation and temporal common subexpression elimination. We evaluate the quality of the ROCCC 2.0 tool by comparing it to hand-written VHDL code. We show comparable clock frequencies and a 18% higher throughput. The productivity advantages of ROCCC 2.0 is evaluated using the metrics of lines of code and programming time showing an average of 15x improvement over hand-written VHDL.

C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

Abstract: CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages. Circuit descriptions can be translated to synthesizable VHDL using the prototype CλaSH compiler. As the circuit descriptions, simulation code, and test input are also valid Haskell, complete simulations can be done by a Haskell compiler or interpreter, allowing high-speed simulation and analysis.

Applications of Field-Programmable Gate Arrays in Scientific Research

Abstract: Focusing on resource awareness in field-programmable gate array (FPGA) design, Applications of Field-Programmable Gate Arrays in Scientific Research covers the principle of FPGAs and their functionality. It explores a host of applications, ranging from small one-chip laboratory systems to large-scale applications in "big science." The book first describes various FPGA resources, including logic elements, RAM, multipliers, microprocessors, and content-addressable memory. It then presents principles and methods for controlling resources, such as process sequencing, location constraints, and intellectual property cores. The remainder of the book illustrates examples of applications in high-energy physics, space, and radiobiology. Throughout the text, the authors remind designers to pay attention to resources at the planning, design, and implementation stages of an FPGA application, in order to reduce the use of limited silicon resources and thereby reduce system cost. Supplying practical know-how on an array of FPGA application examples, this book provides an accessible overview of the use of FPGAs in data acquisition, signal processing, and transmission. It shows how FPGAs are employed in laboratory applications and how they are flexible, low-cost alternatives to commercial data acquisition systems. Web Resource A supporting website at http://scipp.ucsc.edu/~hartmut/FPGA offers more details on FPGA programming and usage. The site contains design elements of the case studies from the book, including VHDL code, detailed schematics of selected projects, photographs, and screen shots.

Circuit Design and Simulation with VHDL

Abstract: This text offers a comprehensive treatment of VHDL and its applications to the design and simulation of real, industry-standard circuits. It focuses on the use of VHDL rather than solely on the language, showing why and how certain types of circuits are inferred from the language constructs and how any of the four simulation categories can be implemented. It makes a rigorous distinction between VHDL for synthesis and VHDL for simulation. The VHDL codes in all design examples are complete, and circuit diagrams, physical synthesis in FPGAs, simulation results, and explanatory comments are included with the designs. The text reviews fundamental concepts of digital electronics and design and includes a series of appendixes that offer tutorials on important design tools including ISE, Quartus II, and ModelSim, as well as descriptions of programmable logic devices in which the designs are implemented, the DE2 development board, standard VHDL packages, and other features. All four VHDL editions (1987, 1993, 2002, and 2008) are covered. This expanded second edition is the first textbook on VHDL to include a detailed analysis of circuit simulation with VHDL testbenches in all four categories (nonautomated, fully automated, functional, and timing simulations), accompanied by complete practical examples. Chapters 1--9 have been updated, with new design examples and new details on such topics as data types and code statements. Chapter 10 is entirely new and deals exclusively with simulation. Chapters 11--17 are also entirely new, presenting extended and advanced designs with theoretical and practical coverage of serial data communications circuits, video circuits, and other topics. There are many more illustrations, and the exercises have been updated and their number more than doubled.

Digital Design with RTL Design, Verilog and VHDL

Abstract: An eagerly anticipated, up-to-date guide to essential digital design fundamentals Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization You begin with an examination of the low-levels of design, noting a clear distinction between design and gate-level minimization The author then progresses to the key uses of digital design today, and how it is used to build high-performance alternatives to software Offers a fresh, up-to-date approach to digital design, whereas most literature available is sorely outdated Progresses though low levels of design, making a clear distinction between design and gate-level minimization Addresses the various uses of digital design today Enables you to gain a clearer understanding of applying digital design to your life With this book by your side, you'll gain a better understanding of how to apply the material in the book to real-world scenarios

Impulse C vs. VHDL for Accelerating Tomographic Reconstruction

Abstract: While traditional methods of designing FPGA applications have relied on schematics or HDL, much interest has been shown in C-to-FPGA tool flows that allow users to design FPGA hardware in C. We evaluate a C-to-FPGA tool flow (Impulse C) by analyzing the performance of three independent implementations of the Computed tomography (CT) filtered backprojection (FBP) algorithm developed using C, Impulse C, and VHDL respectively. In the process, we compare the design process of Impulse C versus HDL, and discuss the benefits and challenges of using Impulse C. In addition, we explore the benefits of tightly-coupled FPGA acceleration offered by the XtremeData XD1000. The results of this paper demonstrate that Impulse C designs can achieve over 61x improvement over multi-threaded software (8 threads), and close to the same performance as VHDL, while significantly reducing the design effort, and that tightly-coupled FPGA coprocessors like the XD1000 effectively overcomes the traditional communication bottleneck between CPU and FPGA.

vMAGIC – Automatic Code Generation for VHDL

Abstract: Automatic code generation is a standard method in software engineering, improving the code reliability as well as reducing the overall development time. In hardware engineering, automatic code generation is utilized within a number of development tools, the integrated code generation functionality, however, is not exposed to developers wishing to implement their own generators. In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented. The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC. Two real-world examples demonstrate the power of code generation in hardware engineering.

A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking

Abstract: Wireless Sensor Networks (WSN) are a new and very challenging research field for embedded system design automation, as their design must enforce stringent constraints in terms of power and cost. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the wide-spreading of this new technology. In this paper, we propose a new architectural model for WSN nodes (and its complete design-flow from C downto synthesizable VHDL) based on the notion of micro-tasks. Our approach combines hardware specialization and power-gating so as to provide an ultra low-power solution for WSN node design. Our first estimates show that power savings by one to two orders of magnitude are possible w.r.t. MCU-based implementations.

IP-cores design for the kNN classifier

Abstract: We present the systematic design of two linear array IP cores for the k-nearest neighbor (k-NN) benchmark classifier. The need for real-time classification of data vectors with possibly thousands of features (dimensions) motivates the implementation of this widely used algorithm in hardware in order to achieve very high performance by exploiting block pipelining and parallel processing. The two linear array architectures that we designed have been described as soft IP cores in fully parameterizable VHDL that can be used to synthesize effortlessly different k-NN parallel architectures for any desirable combination of the problem size parameters. They have been evaluated for a large variety of parameter combinations and Xilinx FPGAs. It is shown that they can be used to solve efficiently very large size k-NN classification problems, even with thousands of training vectors or vector dimensions, using a single, moderate size FPGA device. Furthermore the FPGA implementations exceed by a factor of two the performance of optimized NVIDIA CUDA API software implementations for the powerful GeForce 8800GTX GPU.

FPGA‐based implementation of a real time photovoltaic module simulator

Abstract: An implementation of an intelligent photovoltaic module on reconfigurable Field Programmable Gate Array (FPGA) is described in this paper. An experimental database of meteorological data (irradiation and temperature) and output electrical generation data of a Photovoltaic (PV) module (current and voltage) under variable climate condition is used in this study. Initially, an Artificial Neural Network (ANN) is developed under Matlab/Similuk, environment for modeling the PV module. The inputs of the ANN–PV module are the global solar irradiation and temperature while the outputs are the current and voltage generated from the PV-module. Subsequently, the optimal configuration of the ANN model (ANN–PV module) is written and simulated under the Very High Description Language (VHDL) and ModelSim. The synthesized architecture by ModelSim is then implemented on an FPGA device. The designed MLP-photovoltaic module permits the evaluation of performance of the PV module using only environmental parameters and involves less computational effort. The device can also be used for predicting the output electrical energy from the PV module and for a real time simulation in specific climatic conditions. Copyright © 2010 John Wiley & Sons, Ltd.

Design Artificial Neural Network Using FPGA

Abstract: In the last few years, the electronic devices production field has witness a great revolution by having the new birth of the extraordinary FPGA (Field Programmable Gate Array) family platforms. These platforms are the optimum and best choice for the modern digital systems now a day. The parallel structure of a neural network makes it potentially fast for the computation of certain tasks. The same feature makes a neural network well suited for implementation in VLSI technology. Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. In this paper a hardware design of an artificial neural network on Field Programmable Gate Arrays (FPGA) is presented. A digital system architecture is designed to realize a feedforward multilayer neural network. The designed architecture is described using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

Novel design of Address Generator for WiMAX multimode interleaver using FPGA based finite state machine

Abstract: Wireless technology is the fastest growing segment of the modern communication industry. The IEEE 802.16e standard, commonly known as mobile WiMAX, is the latest wireless technology that has promised to offer Broadband Wireless Access over long distance. The concept of OFDM is used in WiMAX to obtain high data rate in addition to reducing the effects like inter symbol interference and inter channel interference. It has proved to be the air interface for next generation Broadband Wireless System. In this paper, we present a finite state machine based novel technique to model the Address Generation circuitry of WiMAX multimode interleaver using VHDL on FPGA platform with all code rates and modulation schemes of IEEE 802.16e standard. Our approach provides better performance in terms of maximum operating frequency, use of flip-flops with negligible loss in terms of logic cells utilized compared to existing FPGA based implementations. Measured circuit parameters and software simulation of this model are also provided.

FPGA-based implementation of an intelligent simulator for stand-alone photovoltaic system

Abstract: Modelling and simulation of stand-alone photovoltaic (SAPV) systems (PV module, battery, regulator, etc.) in real time is crucial for the control, the supervision, the diagnosis and for studying their performances. In this paper, an intelligent simulator for stand-alone PV system was developed. Firstly, a multilayer perceptron (MLP) has been used for modelling and simulating each component of the system, after that the optimal architecture for each component has been implemented and simulated by using the very high-speed description language (VHDL) and the ModelSim. Subsequently, the developed architectures for each component have been implemented under the Xilinx(R) Virtex-II Pro FPGA (XC2V1000) (field programmable gate array). The obtained results showed that good accuracy is found between predicted and experimental data (signal) in a specific location (south of Algeria). The designed intelligent components (PV-MLP generator, MLP-battery and MLP-regulator) of the SAPV system can be used with success for simulating the system in real time (under a specific climatic condition) by predicting the different output signals for each component constituting the system.

VHDL observers for clock constraint checking

Abstract: Logical time has proved very useful to model heterogeneous and concurrent systems at various abstraction levels. The Clock Constraint Specification Language (CCSL) uses logical clocks as first-class citizens and supports a set of (logical) time patterns to specify the time behavior of systems. We promote here the use of CCSL to express and verify safety properties of VHDL designs. Our proposal relies on an automatic transformation of a CCSL specification into VHDL code that checks the expected properties. Being written in VHDL this code can be integrated in a classical VHDL design and verification flow. Our proposed structural transformation assembles instances of pre-built VHDL components while preserving the polychronous semantics of CCSL. This is not trivial due to major differences between the discrete-time delta cycle based semantics of VHDL and the fixed point semantics of CCSL. This paper describes these differences and proposes solutions to deal with them so as to build VHDL observers for the kernel CCSL constraints. We illustrate the approach by verifying an open-source implementation of the AMBA AHB-to-ABP bridge.

Digital Design with RTL Design, VHDL, and Verilog,

Abstract: Preface. To Students About To Study Digital Design. To Instructors of Digital Design. How to Use This Book. RTL-Focused Approach. Traditional Approach with Some Reordering. Traditional Approach. Acknowledgements. About the Cover. About the Author. Reviewers and Evaluators. CHAPTER 1 Introduction. 1.1 Digital Systems in the World Around Us. 1.2 The World of Digital Systems. 1.3 Implementing Digital Systems: Microprocessors versus DigitalCircuits. 1.4 About this Book. 1.5 Exercises. CHAPTER 2 Combinational Logic Design. 2.1 Introduction. 2.2 Switches. 2.3 The CMOS Transistor. 2.4 Boolean Logic Gates Building Blocks for DigitalCircuits. 2.5 Boolean Algebra. 2.6 Representations of Boolean Functions. 2.7 Combinational Logic Design Process. 2.8 More Gates. 2.9 Decoders and Muxes. 2.10 Additional Considerations. 2.11 Combinational Logic Optimizations and Tradeoffs (SeeSection 6.2). 2.12 Combinational Logic Description Using Hardware DescriptionLanguages (See Section 9.2). 2.13 Chapter Summary. 2.14 Exercises. CHAPTER 3 Sequential Logic Design: Controllers. 3.1 Introduction. 3.2 Storing One Bit Flip-Flops. 3.3 Finite-State Machines (FSMs). 3.4 Controller Design. 3.5 More on Flip-Flops and Controllers. 3.6 Sequential Logic Optimizations and Tradeoffs (See Section6.3). 3.7 Sequential Logic Description Using. 3.8 Product Profile Pacemaker. 3.9 Chapter Summary. 3.10 Exercises. CHAPTER 4 Datapath Components. 4.1 Introduction. 4.2 Registers. 4.3 Adders. 4.4 Comparators. 4.5 Multiplier Array-Style. 4.6 Subtractors and Signed Numbers. 4.7 Arithmetic-Logic Units ALUs. 4.8 Shifters. 4.9 Counters and Timers. 4.10 Register Files. 4.11 Datapath Component Tradeoffs (See Section 6.4). 4.12 Datapath Component Description Using Hardware DescriptionLanguages (See Section 9.4). 4.13 Product Profile: An Ultrasound Machine. 4.14 Chapter Summary. 4.15 Exercises. CHAPTER 5 Register-Transfer Level (RTL) Design. 5.1 Introduction. 5.2 High-Level State Machines. 5.3 RTL Design Process. 5.4 More RTL Design. 5.5 Determining Clock Frequency. 5.6 Behavioral-Level Design: C to Gates (Optional). 5.7 Memory Components. 5.8 Queues (FIFOs). 5.9 Multiple Processors. 5.10 Hierarchy A Key Design Concept. 5.11 RTL Design Optimizations and Tradeoffs (See Section6.5). 5.12 RTL Design Using Hardware Description Languages (SeeSection 9.5). 5.13 Product Profile: Cell Phone. 5.14 Chapter Summary. 5.15 Exercises. CHAPTER 6 Optimizations and Tradeoffs. 6.1 Introduction. 6.2 Combinational Logic Optimizations and Tradeoffs. 6.3 Sequential Logic Optimizations and Tradeoffs. 6.4 Datapath Component Tradeoffs. 6.5 RTL Design Optimizations and Tradeoffs. 6.6 More on Optimizations and Tradeoffs. 6.7 Product Profile: Digital Video Player/Recorder. 6.8 Chapter Summary. 6.9 Exercises. CHAPTER 7 Physical Implementation on ICs. 7.1 Introduction. 7.2 Manufactured IC Types. 7.3 Off-the-Shelf Programmable IC Type FPGA. 7.4 Other Off-the-Shelf IC Types. 7.5 IC Tradeoffs, Trends, and Comparisons. 7.6 Product Profile: Giant LED-Based Video. 7.7 Chapter Summary. 7.8 Exercises. CHAPTER 8 Programmable Processors. 8.1 Introduction. 8.2 Basic Architecture. 8.3 A Three-Instruction Programmable Processor. 8.4 A Six-Instruction Programmable Processor. 8.5 Example Assembly and Machine Programs 8.6 Further Extensions to the Programmable Processor. 8.7 Chapter Summary. 8.8 Exercises. CHAPTER 9 Hardware Description Languages. 9.1 Introduction. 9.2 Combinational Logic Description Using Hardware DescriptionLanguages. 9.3 Sequential Logic Description Using Hardware DescriptionLanguages. 9.4 Datapath Component Description. 9.5 RTL Design Using Hardware Description Languages. 9.6 Chapter Summary. 9.7 Exercises. APPENDIX A Boolean Algebras. A.1 Boolean Algebra. A.2 Switching Algebra. A.3 Important Theorems in Boolean Algebra. A.4 Other Examples of Boolean Algebras. A.5 Further Readings. APPENDIX B Additional Topics in Binary NumberSystems. B.1 Introduction. B.2 Real Number Representation. B.3 Fixed Point Arithmetic. B.4 Floating Point Representation. The IEEE 754-1985 Standard. B.5 Exercises. APPENDIX C Extended RTL Design Example. C.1 Introduction. C.2 Designing the Soda Dispenser Controller. C.3 Understanding the Behavior of the Soda Dispenser Controllerand Datapath.

Building blocks for spikes signals processing

Abstract: Neuromorphic engineers study models and implementations of systems that mimic neurons behavior in the brain. Neuro-inspired systems commonly use spikes to represent information. This representation has several advantages: its robustness to noise thanks to repetition, its continuous and analog information representation using digital pulses, its capacity of pre-processing during transmission time, …, Furthermore, spikes is an efficient way, found by nature, to codify, transmit and process information. In this paper we propose, design, and analyze neuro-inspired building blocks that can perform spike-based analog filters used in signal processing. We present a VHDL implementation for FPGA. Presented building blocks take advantages of the spike rate coded representation to perform a massively parallel processing without complex hardware units, like floating point arithmetic units, or a large memory. Those low requirements of hardware allow the integration of a high number of blocks inside a FPGA, allowing to process fully in parallel several spikes coded signals.

FPGA Implementation of a Reconfigurable Viterbi Decoder for WiMAX Receiver

Abstract: Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reconfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

The use of FPGA in field-oriented control of an induction machine

Abstract: In this study, the feasibility of embedding the field oriented control (FOC) of an induction machine into field programmable gate arrays (FPGA) is investigated. An indirect FOC of an induction machine is simulated in a Matlab Simulink environment using a Xilinx System Generator implemented in a Xilinx Spartan-3 XC3S200 FPGA board. Design of the developed controller for the induction machine is simulated via a Simulink full digital platform. The resulting design has a flexible and modular structure where the designer can customize the hardware blocks by changing the number of inputs, outputs, and algorithm when it is compared to the designs implemented using classical microcontrollers and digital signal processors. With its flexibility, other control algorithms can easily be programmed and embedded into the FPGA. The controller developed can be imbedded and implemented on the Digilab S3 Spartan-3 XC3S200 FPGA development board produced by the Digilent Company. Performance of the developed system has been tested at different load torques and various induction machine speeds.

FPGA-based PID controller for DC-DC converter

Abstract: Proportional Integral Derivative (PID) controller is the most preferable controller in industries that does not require precise analytical model of the system to be controlled. This paper presents a design and implementation of PID (Proportional-Integral-Derivative) controller based on FPGA (Field-Programmable Gate Arrays) for low voltage synchronous buck Converter. Matlab/Simulink environment is used for the PID controller design to generate a set of coefficients associated with the desired controller characteristics. These controller coefficients are then included in VHDL that implements the PID controller on to FPGA. The two architectures of PID controller are considered with their device utilization and power dissipation reports to show the resource utilization and power dissipation of selected FPGA. The architectures are implemented in FPGA Virtex-5(ML505) XC5VLX50T-1FF1136 (-1 speed grade) device.

Semi-automatic derivation of timing models for WCET analysis

Abstract: Embedded systems are widely used for supporting our every day life. In the area of safety-critical systems human life often depends on the system's correct behavior. Many of such systems are hard real-time systems, so that the notion of correctness not only means functional correctness. They additionally have to obey stringent timing constraints, i.e. timely task completion under all circumstances is essential. An example for such a safety-critical system is the flight control computer in an airplane, which is responsible for stability, attitude and path control.In order to derive guarantees on the timing behavior of hard real-time systems, the worst-case execution time (WCET) of each task in the system has to be determined. Saarland University and AbsInt GmbH have successfully developed the aiT WCET analyzer for computing safe upper bounds on the WCET of a task. The computation is mainly based on abstract interpretation of timing models of the processor and its periphery. Such timing models are currently hand-crafted by human experts. Therefore their implementation is a time-consuming and error-prone process.Modern processors or system controllers are automatically synthesized out of formal hardware specifications like VHDL or Verilog. Besides the system' functional behavior, such specifications provide all information needed for the creation of a timing model. But due to their size and complexity, manually examining the sources is even more complex than only looking at the processor manuals. Moreover, this would not reduce the effort nor the probability of implementation errors.To face this problem, this paper proposes a method for semi-automatically deriving suitable timing models out of formal hardware specifications in VHDL that fit to the tool chain of the aiT WCET analyzer. By this, we reduce the creation time of timing models from months to weeks.

LabVIEW FPGA implementation of a PID controller for D.C. motor speed control

Abstract: This Paper presents a novel hardware design methodology of digital control systems. For this, instead of synthesizing the control system using Very high speed integration circuit Hardware Description Language (VHDL), LabVIEW FPGA module from National Instrument (NI) is used to design the whole system that include analog capture circuit to take out the analog signals (set point and process variable) from the real world, PID controller module, and PWM signal generator module to drive the motor. The physical implementation of the digital system is based on Spartan-3E FPGA from Xilinx. Simulation studies of speed control of a D.C. motor are conducted and the effect of a sudden change in reference speed and load are also included.

Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology

Abstract: Data encryption process can easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation, Virtex-6 Field Programmable Gate Array technology. Finite state machine is used only in non-pipelined implementation, and it is not implemented for the pipelined approach. The testing of the implemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. When pipelined approach is employed on the other hand, 17 clock signals are required for the initial phase only, and one clock signal is sufficient afterwards for each data generation cycle. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to program the design.

I2C Protocol Design for Reusability

Abstract: One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the duration of every mode. Interface level is more complicated for reusability because different device has different number of operation mode. For low power reason, not all functions of I2C were designed. This design method was design in VHDL, implementation in FPGA and applied in bio-logging design for RTC and light sensor which are based on I2C protocol. The data acquired by light sensor were transferred through RS232 to PC and stored into text file. The file was shown into graph by using Matlab. The data acquired by RTC were shown by RS232 tool. The correctness efficiency can be confirmed by simulation results.

Analysis and Performance Evaluation of PD-like Fuzzy Logic Controller Design Based on Matlab and FPGA

Abstract: This paper presents an analysis and performance evaluation of the proportional-derivative (PD) fuzzy logic controller design by using Matlab and field programmable gate array (FPGA). The fuzzy logic controller consists of a Fuzzifier, inference engine and Defuzzifier; the Fuzzifier block accepts two PD inputs. Two types of controller are designed; the first one is using fuzzy logic toolbox in Matlab. The second type is designed using VHDL language for implementation on FPGA. Mathematical models of robot arm and bench-top helicopter are used for the purpose of simulation with the first type. This controller is used with a unity feedback control system in Matlab Simulink, in order to control these systems and to generate the simulation results. The best response with the robot arm has 0.02 errors and zero overshot, and the best response with the bench-top helicopter has 0.01 error with 0.001 overshot. Altera Quartus II and ModelSim simulation program are used to generate the simulation results of the second type. A mathematical model that represents industrial processes, such as temperature, pressure, pH, and fluid-level controls with unity feedback control systems and subjected to 0.2 step input is used to generate these results. This FPGA-based controller is able to produce a fast response ranging from 0.3 μs, even with time delay added with the plant model.

FPGA implementation of a Bartlett direction of arrival algorithm for a 5.8ghz circular antenna array

Abstract: This paper presents the design and prototyping of a Bartlett direction of arrival algorithm for an adaptive array antenna system using a Xilinx Virtex-5 FX70 FPGA. The algorithm was prototyped in both full custom VHDL hardware and in a Xilinx MicroBlaze soft processor to analyze the performance tradeoffs between hardware and software implementations. The design was tested using an 8-element circular antenna testbed. The implementation and analysis presented in this work will aid system designers to understand the tradeoffs between implementing algorithms in custom hardware versus in an embedded system and when a hybrid approach is more advantageous. 1 2

Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler

Abstract: A novel technique for the generation of complex and lengthy code sequences using low- length linear feedback shift registers (LFSRs) for data scrambling and descrambling is proposed. The scheme has been implemented using VHSIC hardware description language (VHDL) approach which allows the reconfigurability of the proposed system such that the length of the generated sequences can be changed as per the security requirements. In the present design consideration the power consumption and chip area requirements are small and the operating speed is high compared to conventional discrete I.C. design, which is a pre-requisite for any system designer. The design has been synthesised on device EP2S15F484C3 of Straitx II FPGA family, using Quarts Altera version 8.1. The simulation results have been found satisfactory and are in conformity with the theoretical observations.