Showing papers on "Wafer published in 1991"

Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers

Abstract: A method of providing a conformal layer of TiSix atop a semiconductor wafer within a chemical vapor deposition reactor includes the following steps: a) positioning a wafer within the reactor; b) injecting selected quantities of gaseous Ti(NR2)4 precursor, gaseous silane and a carrier gas to within the reactor, where R is selected from the group consisting of H and a carbon containing radical, the quantities of Ti(NR2)4 precursor and silane being provided in a volumetric ratio of Ti(NR2)4 to silane of from 1:300 to 1:10, the quantity of carrier gas being from about 50 sccm to about 2000 sccm and comprising at least one noble gas; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the precursor and silane to deposit a film on the wafer, the film comprising a mixture of TiSix and TiN, the selected temperature being from about 100° C. to about 500° C., and the selected pressure being from about 150 mTorr to about 100 Torr.

Making and testing an integrated circuit using high density probe points

Abstract: Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.

Stress and plastic flow in silicon during amorphization by ion bombardment

Abstract: In situ wafer curvature measurements were performed during amorphization of silicon by MeV ion implantation. These measurements provide information about density changes and plastic phenomena in the implanted region. Experiments were performed for a variety of ions, a range of fluxes, and for temperatures between −175 and 200 °C. In all cases, the implanted region expanded due to the creation of damaged crystal, creating compressive stress in the implanted region on the order of 108 N/m2. Once heavily damaged or amorphous regions were formed, radiation‐enhanced plastic flow of material out of the plane of the wafer occurred in order to relieve the stress created by the expansion. The value of the shear viscosity responsible for this phenomena could be measured by comparing samples with the same history but different stresses. For 2‐MeV Xe implantation at room temperature and 1011 ions/cm2 s, the radiation‐enhanced shear viscosity is ∼ 1013 Ns/m2, which is at least four orders of magnitude smaller than the thermally activated shear viscosity. Possible contributions to flow from a homogeneous distribution of broken bonds and from fluid‐like collision cascade regions are discussed.

Gas-based substrate protection during processing

Abstract: A suitable inert gas such as argon or a mixture of inert and reactive gases such as argon and hydrogen is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals, metal nitrides and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. A vacuum chuck including a number of radial and circular vacuum grooves in the top surface of the platen is provided for holding the wafer in place. A platen heater is provided under the platen. Backside gas is heated in and about the bottom of the platen, and introduced through a circular groove in the peripheral region outside of the outermost vacuum groove of the vacuum chuck. Backside gas pressure is maintained in this peripheral region at a level greater than the CVD chamber pressure. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gas from contacting the wafer backside. If the process gas is also to be prevented from contacting the periphery of the wafer frontside, a shroud is urged against the platen to direct the backside gas into a cavity formed between the shroud and the platen. This cavity contains the wafer frontside periphery, so that backside gas venting from between the shroud and the wafer frontside periphery excludes the process gas.

Efficient pulsed laser removal of 0.2 μm sized particles from a solid surface

Abstract: Laser cleaning with pulsed ultraviolet and infrared lasers is successfully employed to remove particulate contamination from silicon wafer surfaces and from delicate lithography membrane masks. Particulate material investigated include latex, alumina, silicon, and gold. Gold particles as small as 0.2 μm can be effectively removed. This new and highly efficient laser cleaning is achieved by choosing a pulsed laser with short pulse duration (without causing substrate damage), and a wavelength that is strongly absorbed by the surface; the removal efficiency is further enhanced by depositing a liquid film of thickness on the order of micron on the surface just before the pulsed laser irradiation.

Chemical mechanical planarization (CMP) of a semiconductor wafer using acoustical waves for in-situ end point detection

Abstract: A method and apparatus for chemically mechanically planarizing (CMP) a semiconductor wafer includes directing acoustic waves at the wafer and receiving reflected acoustic waves from the wafer during the (CMP) process. By analyzing the acoustic waves and reflected acoustic waves a thickness of the wafer can be determined and an endpoint and thickness of films formed on the wafer can be monitored in real time during the (CMP) process. The process parameters of the (CMP) process can then be adjusted as required to improve the uniformity of the process.

High throughput interlevel dielectric gap filling process

Abstract: Interlevel gaps between closely spaced circuit elements, such as closely spaced metal interconnect lines, are filed using a biased electron cyclotron resonance (ECR) deposition process. The gaps between circuit elements may be separated by distances of less than 0.6 microns and the gaps can have aspect rations in excess of 2.0. To fill such gaps between the circuit elements on a semiconductor wafer, the wafer is mounted in an ECR reaction chamber. A continuing flow of oxygen (O2) and silane (SiH4) gas is introduced into the ECR system's plasma and reaction chambers, respectively, while applying a microwave excitation so as to generate a plasma. High deposition rates and low film stress are achieved by controlling the flow of oxygen and silane so as to maintain an oxygen to silane gas flow ratio of less than 1.5. In addition, the wafer is cooled, typically using helium, so as to maintain wafer temperature below 300 degrees Celsius, because maintaining low temperatures during ECR deposition has been found to both increase the oxide deposition rate and to reduce the deposited film's compressive stress. This method makes it possible to achieve oxide deposition rates of 6000 Angstroms and above, with film stress below 1.5×109 dynes/cm2. Furthermore, these deposition rates and film stresses are obtained with a high degree of uniformity from wafer to wafer.

Wafer polisher head having floating retainer ring

Abstract: A polishing head for polishing a semiconductor wafer is described. The head design enables a wafer retainer to float during polishing and yet extend beyond a wafer carrier to define a pocket for the wafer and thereby facilitate wafer changing. The head construction also enables the carrier to be selectively projected beyond the retainer so that the surface of the carrier is easily accessible for changing an insert or the like. The head uses a positive air pressure to press the wafer against the polishing pad and the head includes interfering mechanical constructions which provide the positions mentioned above.

Apparatus for heat-treating wafer by light-irradiation and device for measuring temperature of substrate used in such apparatus

Abstract: A temperature measuring device for measuring the temperature of a wafer heated by light irradiation includes: a sheath thermocouple for detecting the temperature of a wafer to be measured by contacting the wafer to be measured; and a covering member for covering the surface of the sheath thermocouple. The surface of the covering member is flat in a predetermined region, and the part in the region can plane-contact the surface of the wafer. Thus, the temperature of the wafer can be measured accurately and in a stable manner, and the wafer surface is free from contamination with adhesives or the metal of the thermocouple.

In situ monitoring technique and apparatus for chemical/mechanical planarization endpoint detection

Abstract: This invention provides an in situ monitoring technique and apparatus for chemical/mechanical planarization end point detection in the process of fabricating semiconductor or optical devices. Fabrication of semiconductor or optical devices often requires smooth planar surfaces, either on the surface of a wafer being processed or at some intermediate stage e.g. a surface of an interleaved layer. The detection in the present invention is accomplished by means of capacitively measuring the thickness of a dielectric layer on a conductive substrate. The measurement involves the dielectric layer, a flat electrode structure and a liquid interfacing the article and the electrode structure. Polishing slurry acts as the interfacing liquid. The electrode structure includes a measuring electrode, an insulator surrounding the measuring electrode, a guard electrode and another insulator surrounding the guard electrode. In the measurement a drive voltage is supplied to the measuring electrode, and in a bootstrap arrangement to a surrounding guard electrode, thereby measuring the capacitance of the dielectric layer of interest without interferring effect from shunt leakage resistance. The process and apparatus are useful not only for measuring the thickness of dielectric layers on conductive substrates in situ, during planarizing polishing, but also for measuring the dielectric thickness on substrates in other processes, e.g. measuring the dielectric layer thickness prior to or after an etching process.

Wafer heating apparatus and with ceramic substrate and dielectric layer having electrostatic chucking means

Abstract: A wafer heating apparatus can be obtained which prevents formation of a local gap caused by deflection or distortion, and the like, of a wafer at the time of heating the wafer so as to improve production yield of the heat treatment of the wafers. The apparatus includes a ceramic substrate, a heat generating resistive element embedded in the ceramic substrate, a film electrode formed on a front surface of the ceramic substrate, and a ceramic dielectric layer formed on the front surface of the ceramic substrate to coat the film electrode. A direct current power source is provided to generate Coulomb's force between the wafer and the film electrode via the dielectric layer to attract the wafer to a wafer-attracting surface of the dielectric layer, while heating the wafer attracted to the wafer-attracting surface by energizing the heat generating element through application of an electric current therethrough. A method of producing the wafer heating apparatus is also disclosed.

Wafer heaters for use in semiconductor-producing apparatus and heating units using such wafer heaters

Abstract: A wafer heater for use in a semiconductor producing apparatus or the like. The heater includes a discoidal substrate made of a dense ceramic, and a resistance heating element buried in the substrate. The surface of the substrate other than that surface upon which a wafer is to be placed for heating is a flat surface. A heating unit is also disclosed, which includes such a heater in a chamber for the semiconductor-producing apparatus. The heating unit further involves a hollow sheath of which inner pressure is not substantially varied even when the pressure inside the chamber changes and is joined to the heater, and a thermocouple inserted into the hollow sheath. Further, a projecting support portion may be provided on the surface of the substrate other than that surface upon which the wafer is to be placed for heating, and lead wires connected to the resistance heating element, wherein when the heater is placed in the chamber, the projecting support portion forms a gas-tight seal between the chamber, and the lead wires are taken out from the chamber such that the lead wires may not substantially be exposed to an inner space inside the chamber.

Non-destructive burn-in test socket for integrated circuit die

Abstract: Disclosed is a burn-in test socket which serves as a temporary package for integrated circuit die, multichip hybrid or a complete wafer without damaging the bonding pads or insulating passivation on the die during test and burn-in.

Polishing pad with uniform abrasion

Abstract: A polishing pad for semiconductor wafers (P), having a face (25) shaped by a series of voids (27, 37, 33). The voids are substantially the same size, but the frequency of the voids increases with increasing radial distance to provide a constant, or nearly constant, surface contact rate to a workpiece (P) such as a semiconductor wafer, in order to effect improved planarity of the workpiece.

Apparatus for endpoint detection during mechanical planarization of semiconductor wafers

Abstract: An apparatus for detecting a planar endpoint on a semiconductor wafer during mechanical planarization of the wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface. This change of friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contacted by the polishing surface. In a preferred form, the change in friction is detected by rotating the wafer and polishing surface with electric motors and measuring current changes on one or both of the motors. This current change can then be used to produce a signal to operate control means for adjusting or stopping the process.

III-V solar cells and doping processes

Abstract: Zinc diffusion procedures applicable for large scale manufacture of GaAs and GaSb cells used in tandem solar cells having a high energy conversion efficiency. The zinc doping and carrier concentration are restricted to be less than about 10 19 /cm 3 to obtain good light generated carrier collection and hence good short circuit currents. The amount of zinc that is available for diffusion during a drive-in heating step is restricted. Confinement of zinc and arsenic vapors during the heating step may be effected by use of a proximity source wafer or by an encapsulant layer. The zinc diffusion of GaSb is obtained by a homogeneous light diffusion that is followed by a patterned heavy diffusion to give low ohmic contact with the grid lines. Texture etching of the GaSb solar cell is also compatible with this diffusion process.

All a‐axis oriented YBa2Cu3O7−y‐PrBa2Cu3O7−z‐YBa2Cu3O7−y Josephson devices operating at 80 K

Abstract: The controllable, reproducible fabrication of nonhysteretic Josephson devices with excess-current weak-link characteristics at temperatures up to 80 K have been demonstrated. The devices are patterned from in situ deposited a-axis oriented YBa2Cu3O(7-y) - PrBa2Cu3O(7-y) - YBa2Cu3O(7-y) trilayers grown on SrTiO3(001) substrates. Control of the critical current density and resistance is achieved by varying the thickness of the PrBa2Cu3O(7-z) barrier layer. Critical current densities in excess of 10,000 A/sq cm have been reproducibly measured; good uniformity across the wafer is obtained with device parameters scaling with device area. Strong constant-voltage current steps are observed under 11.2 GHz microwave radiation at temperatures up to and above 80 K.

High step coverage silicon oxide thin films

Abstract: A process for preparing high step coverage silicon dioxide coatings on semiconductor wafers comprising the placing of the wafer to be coated in a process chamber, introducing disilane and nitrous oxide into the process chamber and maintaining the wafer in an atmosphere consisting essentially of a gaseous mixture of disilane and nitrous oxide and initiating and maintaining plasma enhanced chemical vacuum deposition of silicon dioxide from said gaseous mixture by applying radio frequency energy to the wafer to create a plasma adjacent the surface of said wafer is disclosed.

Real-time multi-zone semiconductor wafer temperature and process uniformity control system

Abstract: A real-time multi-zone semiconductor wafer temperature and process uniformity control system for use in association with a semiconductor wafer fabrication reactor comprises a multi-zone illuminator (130), a multi-point temperature sensor (132), and process control circuitry (150). The method and system of the invention significantly improved wafer (60) temperature control and process uniformity. The multi-zone illuminator module (130) selectively and controllably heats segments of the semiconductor wafer (60). Multi-point temperature sensor (132) independently performs pyrometry-based temperature measurements of predetermined points of the semiconductor wafer (60). Process control circuitry (150) operates in association with the multi-zone illuminator (130) and the multi-point temperature sensor (132) for receiving the temperature measurements and selectively controlling the illuminator module to maintain uniformity in the temperature measurements. A scatter module (116) also provides input to process control circuitry (150) for real-time emissivity compensation of the pyrometry-based temperature measurements of semiconductor wafer (60).

Boron nutride membrane in wafer structure

Abstract: A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.

Efficient Visible Photoluminescence from Porous Silicon

Abstract: It is shown that UV-excited porous Si (PS) exhibits an efficient visible photoluminescence (PL) at room temperature. The PS layers were formed by anodization of p-type and n-type single-crystal Si wafers in aqueous HF solutions. The peak wavelength of PL spectra depends on the anodization parameters including the resistivity and the conduction type of Si substrates. The PL spectra can be tuned to a higher energy side by either adjustment of the anodizing conditions or chemical etching after anodization. These remarkable results can be interpreted as a result of quantum size effects in PS.

Semiconductor wafer level package

Abstract: A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.

Double-dome reactor for semiconductor processing

Abstract: A thermal reactor for epitaxial deposition on a wafer comprises a double-dome vessel and dual heat sources. Each heat source comprises inner and outer circular arrays of infrared lamps. Circumferential heating uniformity is assured by the cylindrical symmetry of the vessel and the heating sources. Radial heating uniformity is provided by independent control of inner and outer heating arrays for both the top and bottom heat sources. The relative temperatures of wafer and susceptor are controlled by adjusting relative energies provided by the upper and lower heat sources so that backside migration. Reduced pressure operation is provided for by the convex top and bottom domes. Due to the provided control over transmitted energy distribution, a susceptor can have low thermal mass so that elevated temperature can be achieved more quickly and cooling can be facilitated as well. This improves throughput and reduces manufacturing costs per wafer. Reagent gas introduction can be axial or radial as desired.

Single wafer megasonic semiconductor wafer processing system

Abstract: A semiconductor wafer processing system utilizing a specially constructed wet processing chamber for a single wafer and a megasonic, or high frequency, energy dispensing system. The construction of the container causes megasonic energy to become intensified near the surface of the wafer, thereby providing more cleaning power, and resulting cleaning. The megasonic device may be mounted on a bottom wall dump valve. Also, the energy output may be used to rotate a wafer.

Silicon monolithic micromechanical gyroscope

Abstract: A monolithic silicon gyroscope is described which is completely batch fabricated on a silicon wafer. Only one side of the wafer is employed so the process is readily adaptable to any size wafer. The gimbals, flexures, and electrodes are all made on the same substrate so that a mass-producible instrument is realized. The process is compatible with the use of on-chip electronics, which will be required to maximize the performance of the instrument. The authors describe several methods of incorporating the electrodes within the device substrate. They enumerate the advantages of the monolithic construction, and mention potential areas of application. Initial test data showed a noise-limited rate detection capability of 4 deg/s at a 1-Hz bandwidth. >

Rotating sputtering apparatus for selected erosion

Abstract: A magnetron sputter source providing a predetermined erosion distribution over the surface of a sputter target material is described. When the distribution is uniform, close coupling of the sputter target with the substrate to be coated is achieved, resulting in improved collection efficiency of the sputtered material by the wafer and improved film thickness uniformity. Elimination of erosion grooves provide for greater target consumption and longer target life. The cathode magnetron sputter source includes a rotating magnet assembly of a specific shape and a specific magnetic strength provides the desired erosion distribution. The target may be dished to improve uniformity near the periphery of the wafer. The resulting magnetron cathode is used for the deposition of thin films. Further applications of uniform magnetron erosion or preselected erosion include uniform or preselected magnetron sputter etch or reactive ion etch and concurrent deposition and etch.

Particle detector for rough surfaces

Abstract: A surface inspection apparatus having multiple inspection stations to inspect a wafer for a number of characteristics. The wafer is placed on a chuck connected to a rack-and-pinion or equivalent system so that the wafer simultaneously rotates and translates under the fixed position of the inspection stations. A single light source may be used by all stations in turn. One station may be a particle detector with collection optics receiving a small select portion of the light scattered from the wafer surface. A second station may be a roughness detector with a collection system to direct a large portion of scattered light to a detector. A position sensitive detector may be used to determine the slope of the wafer surface at an inspection point when the wafer is not clamped to the chuck, giving a measure of surface deformation. These or other stations are positioned about either of two inspection points at which the beam from the light source may be directed. The inspection points are spaced one wafer radius apart to minimize the required wafer motion for a complete surface scan.

Selective metal electrodeposition process

Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing) , metal thickness uniformity, step coverage and environmental concerns. A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables. Using this process and the associated hardware, metal lines are selectively deposited with contacts or vias completely filled without the need for plasma etching the deposited metal.

Distributed polishing head

Abstract: A distributed polishing head assembly (17) has a flexible membrane (14), and a plurality of periodic polishing pads (12) that are attached to the flexible membrane (14). The polishing pads (12) are made from a flat semiconductor wafer that has been sawed into small pieces. The polishing head is rubbed against a semiconductor wafer (10) in order to planarize the wafer (10).

Method for fabrication of probe card for testing of semiconductor devices

Abstract: A flexible polyimide film is used to support an array of precisely located contact bumps which are used to probe die on a wafer of semiconductor circuits, or an unmounted integrated circuit die, several integrated circuits, or hybrid devices. By utilizing a standard I/O contact pattern for the flexible film and fabricating the membrane assembly of interconnects on an aluminum substrate, it is possible to produce a more reliable probe card, while reducing the fabrication time and costs for the probe card. The polyimide film must be selected to have a CTE of 3 to 5, which is only about 1/5 to 1/7 as great as the CTE of the aluminum substrate on which the film is formed. This produces a critical degree of compressive stress in the polyimide film, and a resulting "bow" of the film when the central area of the aluminum is etched away.