Recent progress in processing and properties of ZnO

Nanofabrication of magnetic storage media, where servo marks, discrete tracks or individual islands are defined, offer the prospect for improved performance and increased areal density. However, this increase in performance will require that new and additional processes be introduced into disk manufacturing. We review here the fundamental patterning and fabrication processes that have been proposed, along with their respective strengths and weaknesses and the potential advantages they may offer for magnetic recording. The increase in data density afforded by nanofabrication may have added significance as more conventional approaches to ever increasing density will encounter physical limitations set by the thermal stability of the recorded bits.

https://iopscience.iop.org/article/10.1088/0022-3727/38/12/R01/pdf

Nanofabricated and self-assembled magnetic structures as data storage media

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

/pdf/plasma-etching-yesterday-today-and-tomorrow-4a8eftp390.pdf

Plasma etching: Yesterday, today, and tomorrow

As new, advanced high-k dielectrics are being developed to replace SiO2 in future generations of microelectronics devices, understanding their etch characteristics becomes vital for integration into the manufacturing process. We report on the etch rates and possible mechanisms for one such dielectric, Zr1−xAlxOy (x≈0.2), in plasmas containing a mixture of Cl2 and BCl3, as a function of gas composition and ion impact energy. Higher concentrations of BCl3 enhance the etch rate as well as selectivity of Zr1−xAlxOy etching as compared to the etching of α-Si, whereas increasing ion energy increases the etching rates but decreases selectivity. In a high density helical resonator plasma, etching rates on the order of 700 A/min and 1:1 selectivity are typical. Angle-resolved x-ray photoelectron spectroscopy was used to study the composition of the upper ∼30 A of the film, before and at the end of the etching process. We found that the etching rate of Zr1−xAlxOy does not change with time for the range of Cl2/BCl3 ...

Etching of high-k dielectric Zr1−xAlxOy films in chlorine-containing plasmas

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20 With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/12 nm with leakage current 15) may be viable alternate gate dielectrics

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

The growth temperature dependence of the thin thermally oxidized Si(001)/SiO2 interface width was studied using synchrotron x‐ray diffraction. Nine samples with oxide thickness of about 100 A were studied, with growth temperatures ranging from 800 to 1200 °C. The oxides were prepared by rapid thermal oxidation. We found that interfacial roughness decreases linearly with increasing growth temperature, with a measured interface width of 2.84 A for the sample grown at 800 °C, and 1.76 A when grown at 1200 °C.

Growth temperature dependence of the si(001)/sio2 interface width

Thin films of Zr0.62Al0.38O1.8 are amorphous when deposited at room temperature by rf magnetron sputtering. Crystallization occurs during subsequent annealing in the temperature range of 700–1000 °C for times in the range of 10 s–100 h. The crystallite size and the fraction of the sample that had crystallized were determined using x-ray diffraction. The films were found to initially develop a low density of fairly large (∼8 nm) crystallites, while subsequent heat treatment was found to increase the density rather than the size of the crystallites. Crystallization can be described with a first-order rate equation; the rate constant is exponential in temperature with an effective activation energy of 6.6 eV. Films given a 10 s anneal at <850 °C develop a substantial density of 8 nm grains, making this specific composition an unsuitable candidate for replacing SiO2 as the gate oxide in hyperscaled field-effect transistors.

Crystallization kinetics in amorphous (Zr0.62Al0.38)O1.8 thin films

We have investigated the crystallization of amorphous oxides that are considered likely candidates to replace amorphous SiO2 as the gate dielectric in advanced field-effect transistors. To avoid crystallization, the mole fraction of main-group oxide in the Zr–Si–O, Zr–Al–O, and Hf–Si–O systems must be greater than 83%, 65%, and 78%, respectively, leading to a maximum useful dielectric constant of only 6.9, 12.7, and 6.6, respectively. We conclude that the silicate systems are not likely to be useful as replacements for SiO2, while aluminates are more promising.

L. Manchanda

Papers

Etching of high-k dielectric Zr1−xAlxOy films in chlorine-containing plasmas

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

Growth temperature dependence of the si(001)/sio2 interface width

Crystallization kinetics in amorphous (Zr0.62Al0.38)O1.8 thin films

Composition-dependent crystallization of alternative gate dielectrics